STATUS_OUT : out std_logic_vector (63 downto 0); -- bits for status registers
TRG_ENABLE_IN : in std_logic; -- trigger enable flag
TRG_INVERT_IN : in std_logic; -- trigger invert flag
+ COUNTERS_STATUS_OUT : out std_logic_vector (64 downto 0); -- 16b starting missing, multiple, spike, spurious-- gk 29.09.10
--Debug
DEBUG_OUT : out std_logic_vector (15 downto 0)
);
signal missing_tmg : std_logic;
-- gk 12.09.10
signal short_tmg_trg : std_logic;
-signal short_tmg_trg_q : std_logic;
-- gk 24.09.10
signal mult_trg_lock : std_logic;
signal prev_trg_reg : std_logic_vector(3 downto 0);
+-- gk 29.09.10
+signal multiple_ctr : unsigned(15 downto 0);
+signal missing_ctr : unsigned(15 downto 0);
+signal spikes_ctr : unsigned(15 downto 0);
+signal spurious_ctr : unsigned(15 downto 0);
+signal ctr_lock : std_logic;
+signal wrong_polarity : std_logic;
begin
-- state transitions
STATE_TRANSFORM: process( CURRENT_STATE, LVL1_TRG_RECEIVED_IN, LVL1_TRG_TYPE_IN(3), LVL1_TRG_INFORMATION_IN(7),
- LVL1_TRG_RELEASE_IN, timing_trg_found, timing_trg_rising, timeout_found, data_valid, short_tmg_trg_q )
+ LVL1_TRG_RELEASE_IN, timing_trg_found, timing_trg_rising, timeout_found, data_valid )
begin
NEXT_STATE <= IDLE; -- avoid latches
next_toc_ce <= '0';
end if;
end process COUNT_EDGES_AND_LENGTH_PROC;
+-- gk 29.09.10
+WRONG_POLAR_PROC : process(CLOCK)
+begin
+ if (RESET = '1') then
+ wrong_polarity <= '0';
+ elsif (trigger_length > 100) then
+ wrong_polarity <= '1';
+ end if;
+end process WRONG_POLAR_PROC;
+
---------------------------------------------------------------------------
-- Error bits
---------------------------------------------------------------------------
-next_error_pattern(31 downto 19) <= LVL1_ERROR_PATTERN_IN(31 downto 26);
+next_error_pattern(31 downto 26) <= LVL1_ERROR_PATTERN_IN(31 downto 26);
next_error_pattern(25) <= LVL1_ERROR_PATTERN_IN(25) or timeout_found; -- timeout
next_error_pattern(24) <= LVL1_ERROR_PATTERN_IN(24) or short_tmg_trg; -- spike detected
-next_error_pattern(23 downto 19 <= LVL1_ERROR_PATTERN_IN(23 downto 19);
+next_error_pattern(23 downto 19) <= LVL1_ERROR_PATTERN_IN(23 downto 19);
next_error_pattern(18) <= LVL1_ERROR_PATTERN_IN(18) or mult_trg_found; -- multiple timing triggers
next_error_pattern(17) <= LVL1_ERROR_PATTERN_IN(17) or invalid_trg; -- timing trigger missing
---------------------------------------------------------------------------
-- Status bits
---------------------------------------------------------------------------
-STATUS_OUT(63 downto 48) <= std_logic_vector(trigger_length);
-STATUS_OUT(47 downto 32) <= std_logic_vector(trigger_edge_count);
-STATUS_OUT(31 downto 16) <= lvl1_delay;
-STATUS_OUT(15) <= timing_trg_found;
-STATUS_OUT(14) <= data_valid;
-STATUS_OUT(13) <= mult_trg_found;
-STATUS_OUT(12) <= trg_num_match;
-STATUS_OUT(11) <= timeout_found;
-STATUS_OUT(10 downto 4) <= (others => '0');
-STATUS_OUT(3 downto 0) <= bsm_x;
+STAT_PROC : process(CLOCK)
+begin
+ if rising_edge(CLOCK) then
+ if (RESET = '1') then
+ STATUS_OUT <= (others => '0');
+ elsif (val_trg = '1') or (invalid_trg = '1') then
+ STATUS_OUT(63 downto 48) <= std_logic_vector(trigger_length);
+ STATUS_OUT(47 downto 32) <= std_logic_vector(trigger_edge_count);
+ STATUS_OUT(31 downto 16) <= lvl1_delay;
+ STATUS_OUT(15) <= timing_trg_found;
+ STATUS_OUT(14) <= data_valid;
+ STATUS_OUT(13) <= mult_trg_found;
+ STATUS_OUT(12) <= trg_num_match;
+ STATUS_OUT(11) <= timeout_found;
+ STATUS_OUT(10 downto 8) <= (others => '0');
+ STATUS_OUT(7) <= wrong_polarity;
+ STATUS_OUT(6) <= spurious_trg;
+ STATUS_OUT(5) <= missing_tmg;
+ STATUS_OUT(4) <= short_tmg_trg;
+ STATUS_OUT(3 downto 0) <= bsm_x;
+ end if;
+ end if;
+end process STAT_PROC;
+
+-- STATISTICS COUNTERS
+-- gk 29.09.10
+STAT_CTR_PROC : process(CLOCK)
+begin
+ if rising_edge(CLOCK) then
+ if (RESET = '1') then
+ multiple_ctr <= (others => '0');
+ missing_ctr <= (others => '0');
+ spikes_ctr <= (others => '0');
+ spurious_ctr <= (others => '0');
+ ctr_lock <= '0';
+ elsif (invalid_trg = '1') then
+ missing_ctr <= missing_ctr + to_unsigned(1,1);
+ elsif (timing_trg_found = '1') and (mult_trg_found = '1') and (ctr_lock = '0') then
+ multiple_ctr <= multiple_ctr + to_unsigned(1,1);
+ ctr_lock <= '1';
+ elsif ((prev_trg_reg(0) = '1') and (timing_trg_reg(0) = '0') and (prev_trg_reg(3) = '0')) then
+ spikes_ctr <= spikes_ctr + to_unsigned(1,1);
+ elsif (spurious_trg = '1') and (ctr_lock = '0') then
+ spurious_ctr <= spurious_ctr + to_unsigned(1,1);
+ ctr_lock <= '1';
+ elsif (invalid_trg = '0') and (mult_trg_found = '0') and (spurious_trg = '0') then
+ ctr_lock <= '0';
+ end if;
+ end if;
+end process STAT_CTR_PROC;
+COUNTERS_STATUS_OUT(15 downto 0) <= std_logic_vector(missing_ctr);
+COUNTERS_STATUS_OUT(31 downto 16) <= std_logic_vector(multiple_ctr);
+COUNTERS_STATUS_OUT(47 downto 32) <= std_logic_vector(spikes_ctr);
+COUNTERS_STATUS_OUT(63 downto 48) <= std_logic_vector(spurious_ctr);
---------------------------------------------------------------------------
-- Debug signals