USE SECONDARY NET "THE_MEDIA_4_PCSC/clk_rx_full[3]";
USE SECONDARY NET "gen_PCSD.THE_MEDIA_4_PCSD/clk_rx_full[1]";
+# read from SCI can be delayed due to long read strobe
+MULTICYCLE FROM ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
+# write strobe can be delayed due to A/D being stable after access
+MULTICYCLE TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
+
+# SCI write signal problem...
+#BLOCK NET gen_PCSB.THE_MEDIA_PCSB/sci_write_i;
+#BLOCK INTERCLOCKDOMAIN PATHS;
+
################################
FREQUENCY NET "gen_GBE.GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz;
SYNC_TX_PLL_IN => sync_tx_quad_i,
LINK_TX_READY_IN => link_tx_ready_i,
DESTROY_LINK_IN => x"0",
+ WAP_REQUESTED_IN => x"0",
--SFP Connection
SD_PRSNT_N_IN(0) => BACK_GPIO(1),
SD_PRSNT_N_IN(1) => '1',
SYNC_TX_PLL_IN => sync_tx_quad_i,
LINK_TX_READY_IN => link_tx_ready_i,
DESTROY_LINK_IN => x"0",
+ WAP_REQUESTED_IN => x"0",
--SFP Connection
SD_PRSNT_N_IN(0) => HUB_MOD0(5),
SD_PRSNT_N_IN(1) => HUB_MOD0(6),
SYNC_TX_PLL_IN => sync_tx_quad_i,
LINK_TX_READY_IN => link_tx_ready_i,
DESTROY_LINK_IN => x"0",
+ WAP_REQUESTED_IN => x"0",
--SFP Connection
SD_PRSNT_N_IN(0) => HUB_MOD0(5),
SD_PRSNT_N_IN(1) => HUB_MOD0(6),
SYNC_TX_PLL_IN => sync_tx_quad_i,
LINK_TX_READY_IN => link_tx_ready_i,
DESTROY_LINK_IN => x"0",
+ WAP_REQUESTED_IN => x"0",
--SFP Connection
SD_PRSNT_N_IN(0) => HUB_MOD0(3),
SD_PRSNT_N_IN(1) => HUB_MOD0(4),
SYNC_TX_PLL_IN => sync_tx_quad_i,
LINK_TX_READY_IN => link_tx_ready_i,
DESTROY_LINK_IN => x"0",
+ WAP_REQUESTED_IN => x"0",
--SFP Connection
SD_PRSNT_N_IN(0) => SFP_MOD0(0),
SD_PRSNT_N_IN(1) => HUB_MOD0(8),
FREQUENCY NET "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.gen_ipu_apl.gen_gbe.THE_GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz;
FREQUENCY NET "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.gen_ipu_apl.gen_gbe.THE_GBE/clk_125_rx_from_pcs[0]" 125 MHz;
LOCATE COMP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.gen_ipu_apl.gen_gbe.THE_GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD";
+
+# read from SCI can be delayed due to long read strobe
+MULTICYCLE FROM ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
+# write strobe can be delayed due to A/D being stable after access
+MULTICYCLE TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
+
+# SCI write signal problem...
+#BLOCK NET gen_PCSB.THE_MEDIA_PCSB/sci_write_i;
+#BLOCK INTERCLOCKDOMAIN PATHS;