new SPI register naming scheme, IF

diff --git a/fw_spiconfig.tex b/fw_spiconfig.tex
index 72b59b31f3f5b9a10a34b194a86b30b871b4bce3..3317ee5570348a9faad7ea949c31a3ec14df3984 100644 (file)
--- a/fw_spiconfig.tex
+++ b/fw_spiconfig.tex
@@ -5,9 +5,9 @@ Note that up to 16 commands can be sent to a board with one trbnet access: Load
  \begin{tabularx}{\textwidth}{c|c|X}
 \textbf{Bits} & \textbf{Name} & \textbf{Content} \\
 \hline
-31 -- 24 & Select & See table \ref{tab:spiselect}\\
+31 -- 24 & 8-Bit-Register & See table \ref{tab:spiselect}\\
 23 -- 20 & Command & Command, 0: read, 8: write, other: no operation \\
-19 -- 16 & Channel & Channel / Register select (0 -- 15)\\
+19 -- 16 & Subregister & Additional 4 bits for register select (0 -- 15)\\
 15 -- 0\newline (\& following$\dagger$)& Data & 16 Bit data payload for write commands\\
 
  \end{tabularx} 
@@ -18,7 +18,7 @@ Note that up to 16 commands can be sent to a board with one trbnet access: Load
 
 \begin{table}
  \begin{tabularx}{\textwidth}{c|c|c|X}
-\textbf{Value} & \textbf{Register} & \textbf{Name} & \textbf{Description} \\
+\textbf{Register} & \textbf{Subregister} & \textbf{Name} & \textbf{Description} \\
 \hline
 0x00 & any & PWM & Write/read settings for PWM channels 0 - 15.\\
 0x10 & 0--3 & UId/Temp & read unique id. 64 Bit Id is divided in 4 16 Bit words. (r/o)\\