architecture rx_control_arch of rx_control is
-type rx_state_t is (SLEEP, WAIT_1, FIRST, GET_DATA, GET_IDLE, GET_DLM, MAKE_RESET, START_RETR);
+type rx_state_t is (SLEEP, WAIT_1, FIRST, GET_DATA, GET_IDLE, GET_DLM, MAKE_RESET, START_RETR, GET_CRC);
signal rx_state : rx_state_t;
signal rx_state_bits : std_logic_vector(3 downto 0);
signal rx_packet_num : std_logic_vector(2 downto 0);
signal got_link_ready_i : std_logic := '0';
signal start_retr_i : std_logic;
signal start_retr_pos_i : std_logic_vector(7 downto 0);
+signal req_retr_i : std_logic;
+signal req_retr_pos_i : std_logic_vector(7 downto 0);
signal rx_dlm_i : std_logic;
signal rx_dlm_word_i : std_logic_vector(7 downto 0);
signal reset_cnt : unsigned(7 downto 0);
+signal crc_reset : std_logic;
+signal crc_q : std_logic_vector(7 downto 0);
+signal crc_en : std_logic;
+signal crc_data : std_logic_vector(7 downto 0);
+
+
begin
----------------------------------------------------------------------
ct_fifo_reset <= not RX_ALLOW_IN when rising_edge(CLK_200);
+----------------------------------------------------------------------
+-- CRC
+----------------------------------------------------------------------
+
+crc_data <= reg_rx_data_in when rising_edge(CLK_200);
+
+CRC_CALC : trb_net_CRC8
+ port map(
+ CLK => CLK_200,
+ RESET => crc_reset,
+ CLK_EN => crc_en,
+ DATA_IN => crc_data,
+ CRC_OUT => crc_q,
+ CRC_match => open
+ );
+
----------------------------------------------------------------------
-- Read incoming data
----------------------------------------------------------------------
wait until rising_edge(CLK_200);
ct_fifo_write <= '0';
start_retr_i <= '0';
+ req_retr_i <= '0';
rx_dlm_i <= '0';
idle_hist_i(3 downto 1) <= idle_hist_i(2 downto 0);
idle_hist_i(0) <= got_link_ready_i;
+ crc_en <= '0';
+ crc_reset <= '0';
case rx_state is
when SLEEP =>
case reg_rx_data_in is
when K_IDLE =>
rx_state <= GET_IDLE;
+ crc_reset <= '1';
when K_RST =>
rx_state <= MAKE_RESET;
reset_cnt <= x"00";
rx_state <= GET_DLM;
when K_REQ =>
rx_state <= START_RETR;
+ when K_EOP =>
+ rx_state <= GET_CRC;
when others => null;
end case;
else
rx_state <= GET_DATA;
+ crc_en <= '1';
end if;
when GET_IDLE =>
when GET_DATA =>
rx_state_bits <= x"4";
+ crc_en <= '1';
if reg_rx_k_in = '0' then
next_sop <= '0';
rx_data(15 downto 8)<= reg_rx_data_in;
else
rx_state <= SLEEP;
end if;
+
+ when GET_CRC => --TODO: mitzaehlen, of CRC nach 5 16-Bit-Paketen kommt
+ crc_reset <= '1';
+ rx_state <= FIRST;
+ if (crc_q = reg_rx_data_in) then
+ req_retr_i <= '1';
+ end if;
when GET_DLM =>
rx_state_bits <= x"5";
----------------------------------------------------------------------
GOT_LINK_READY <= got_link_ready_i;
-START_RETRANSMIT_OUT <= start_retr_i when rising_edge(CLK_200);
+--START_RETRANSMIT_OUT <= start_retr_i when rising_edge(CLK_200);
+START_RETRANSMIT_OUT_SYNC : pulse_sync
+ port map(
+ CLK_A_IN => CLK_200,
+ RESET_A_IN => RESET_IN,
+ PULSE_A_IN => start_retr_i,
+ CLK_B_IN => CLK_100,
+ RESET_B_IN => RESET_IN,
+ PULSE_B_OUT => START_RETRANSMIT_OUT
+ );
+
START_POSITION_OUT <= start_retr_pos_i when rising_edge(CLK_200);
RX_DLM <= rx_dlm_i when rising_edge(CLK_200);
RX_DLM_WORD <= rx_dlm_word_i when rising_edge(CLK_200);
-REQUEST_RETRANSMIT_OUT <= '0'; --TODO: check incoming data
+--REQUEST_RETRANSMIT_OUT <= req_retr_i when rising_edge(CLK_200); -- '0'; --TODO: check incoming data
+REQUEST_RETRANSMIT_OUT_SYNC : pulse_sync
+ port map(
+ CLK_A_IN => CLK_200,
+ RESET_A_IN => RESET_IN,
+ PULSE_A_IN => req_retr_i,
+ CLK_B_IN => CLK_100,
+ RESET_B_IN => RESET_IN,
+ PULSE_B_OUT => REQUEST_RETRANSMIT_OUT
+ );
+
+
REQUEST_POSITION_OUT <= x"00"; --TODO: check incoming data
SEND_LINK_RESET_OUT <= send_link_reset_i when rising_edge(CLK_200);
type state_t is (SEND_IDLE_L, SEND_IDLE_H, SEND_DATA_L, SEND_DATA_H, SEND_DLM_L, SEND_DLM_H,
- SEND_START_L, SEND_START_H, SEND_REQUEST_L, SEND_REQUEST_H,
+ SEND_START_L, SEND_START_H, SEND_REQUEST_L, SEND_REQUEST_H,
SEND_RESET, SEND_CHKSUM_L, SEND_CHKSUM_H); -- gk 05.10.10
signal current_state : state_t;
signal state_bits : std_logic_vector(3 downto 0);
TX_CD_OUT <= '0';
debug_sending_dlm <= '0';
first_idle <= '1';
+-- load_read_pointer_i <= '0';
case current_state is
when SEND_IDLE_L =>
TX_DATA_OUT <= K_IDLE;
when SEND_CHKSUM_H =>
TX_DATA_OUT <= crc_q;
-
+
when SEND_START_L =>
TX_DATA_OUT <= K_BGN;
TX_K_OUT <= '1';
current_state <= SEND_START_H;
when SEND_START_H =>
- TX_DATA_OUT <= std_logic_vector(ram_read_addr);
+ --TX_DATA_OUT <= std_logic_vector(ram_read_addr);
+ TX_DATA_OUT <= x"FF";
+ current_state <= SEND_DATA_L;
when SEND_REQUEST_L =>
TX_DATA_OUT <= K_REQ;
when others =>
current_state <= SEND_IDLE_L;
end case;
-
+
if current_state = SEND_START_H or
current_state = SEND_IDLE_H or
current_state = SEND_DATA_H or
current_state <= SEND_REQUEST_L;
elsif make_restart_i = '1' then
current_state <= SEND_START_L;
+-- load_read_pointer_i <= '1';
elsif send_dlm_i = '1' then
current_state <= SEND_DLM_L;
elsif (load_eop = '1') then
if RESET_IN = '1' then
make_restart_i <= '0';
restart_position_i <= (others => '0');
+ load_read_pointer_i <= '0';
elsif rising_edge(CLK_200) then
+ load_read_pointer_i <= '0';
if tx_allow_qtx = '0' then
make_restart_i <= '0';
restart_position_i <= (others => '0');
elsif start_retransmit_i = '1' then
make_restart_i <= '1';
restart_position_i <= restart_position_q;
+ load_read_pointer_i <= '1'; --prepare load at the same time
elsif current_state = SEND_START_L then
make_restart_i <= '0';
elsif current_state = SEND_START_H then
end if;
end if;
end process;
-
+
--Store DLM send
THE_STORE_DLM_PROC : process(CLK_200, RESET_IN)
begin
end if;
end process;
- load_read_pointer_i <= '1' when current_state = SEND_START_L else '0';
+ -- load_read_pointer_i <= '1' when current_state = SEND_START_L else '0';
+ -- ---in this scheme the load pointer comes too late
-- gk 05.10.10
crc_reset <= '1' when ((RESET_IN = '1') or (current_state = SEND_CHKSUM_H) or (current_state = SEND_START_H)) else '0';
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