new clock input for media interface in template

diff --git a/template/trb3sc_basic.vhd b/template/trb3sc_basic.vhd
index 200f19f087898d5b46fd82a7b85203b86fea6877..23e58890a044d1517a0353ebb3be0bf5dab47ca0 100644 (file)
--- a/template/trb3sc_basic.vhd
+++ b/template/trb3sc_basic.vhd
@@ -195,7 +195,8 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler
       IS_SYNC_SLAVE => c_YES
       )
     port map(
-      CLK           => clk_full_osc,
+      CLK_REF_FULL       => med2int(0).clk_full,
+      CLK_INTERNAL_FULL  => clk_full_osc,
       SYSCLK        => clk_sys,
       RESET         => reset_i,
       CLEAR         => clear_i,