SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- --SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
SLV_ADDR_IN : in std_logic_vector(15 downto 0);
SLV_ACK_OUT : out std_logic;
SLV_NO_MORE_DATA_OUT : out std_logic;
signal fifo_wren : std_logic_vector(3 downto 0) := (others => '0');
signal fifo_full_i : std_logic_vector(3 downto 0) := (others => '0');
+ signal reset_error_cnt_i : std_logic := '0';
+ type error_cnt_type is array (0 to c_used_serdes_channels - 1) of unsigned(31 downto 0);
+ signal error_cnt : error_cnt_type := (others => (others => '0'));
+
component InputSynchronizer
generic(depth : integer := 2;
width : integer := 1);
port map(clk => sysclk, rst => rst, input => rx_cdr_lol_s, sync_output => rx_cdr_lol_s_sync);
+ --error counter
+ error_counter_proc : process(sysclk) is
+ begin
+ if rising_edge(sysclk) then
+ if rst = '1' or reset_error_cnt_i = '1' then
+ error_cnt <= (others => (others => '0'));
+ else
+ for i in 0 to c_used_serdes_channels - 1 loop
+ if lsm_status_s_sync(i) = '1' and (rx_disp_err(i) = '1' or rx_cv_err(i) = '1') then
+ error_cnt(i) <= error_cnt(i) + 1;
+ else
+ error_cnt(i) <= error_cnt(i);
+ end if;
+ end loop;
+ end if;
+ end if;
+ end process error_counter_proc;
+
+
SLV_BUS : process(sysclk) is
begin
if rising_edge(sysclk) then
SLV_UNKNOWN_ADDR_OUT <= '0';
SLV_NO_MORE_DATA_OUT <= '0';
SLV_ACK_OUT <= '0';
+ reset_error_cnt_i <= '0';
+ --TODO: write this with channel select and not explicitly with registers
if SLV_READ_IN = '1' then
case SLV_ADDR_IN is
when x"0000" => --read counters are already synchronous to trb system clock
SLV_DATA_OUT(2 downto 0) <= rx_cdr_lol_s_sync(3) & rx_los_low_s_sync(3) & lsm_status_s_sync(3);
SLV_DATA_OUT(4 downto 3) <= rx_disp_err(3) & rx_cv_err(3);
SLV_ACK_OUT <= '1';
+ when x"0008" =>
+ SLV_DATA_OUT <= std_logic_vector(error_cnt(0));
+ SLV_ACK_OUT <= '1';
+ when x"0009" =>
+ SLV_DATA_OUT <= std_logic_vector(error_cnt(1));
+ SLV_ACK_OUT <= '1';
+ when x"000a" =>
+ SLV_DATA_OUT <= std_logic_vector(error_cnt(2));
+ SLV_ACK_OUT <= '1';
+ when x"000b" =>
+ SLV_DATA_OUT <= std_logic_vector(error_cnt(3));
+ SLV_ACK_OUT <= '1';
when others =>
SLV_UNKNOWN_ADDR_OUT <= '1';
end case;
+
elsif SLV_WRITE_IN = '1' then
- SLV_UNKNOWN_ADDR_OUT <= '1';
+ case SLV_ADDR_IN is
+ when x"000c" =>
+ reset_error_cnt_i <= SLV_DATA_IN(0);
+ when others =>
+ SLV_UNKNOWN_ADDR_OUT <= '1';
+ end case;
end if;
end if;
end if;
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- --SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
SLV_ADDR_IN : in std_logic_vector(15 downto 0);
SLV_ACK_OUT : out std_logic;
SLV_NO_MORE_DATA_OUT : out std_logic;
SLV_READ_IN => mupixdata_regio_read_enable_in_0,
SLV_WRITE_IN => mupixdata_regio_write_enable_in_0,
SLV_DATA_OUT => mupixdata_regio_data_out_0,
- --SLV_DATA_IN => mupixdata_regio_data_in_0,
+ SLV_DATA_IN => mupixdata_regio_data_in_0,
SLV_ADDR_IN => mupixdata_regio_addr_in_0,
SLV_ACK_OUT => mupixdata_regio_ack_out_0,
SLV_NO_MORE_DATA_OUT => mupixdata_regio_no_more_data_out_0,