--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+
+library ecp5um;
+use ecp5um.components.all;
+
+entity sedcheck is
+ port(
+ CLK : in std_logic;
+ ERROR_OUT : out std_logic;
+
+ CONTROL_IN : in std_logic_vector(3 downto 0);
+ DEBUG : out std_logic_vector(31 downto 0)
+ );
+end entity;
+
+
+architecture sed_arch of sedcheck is
+
+ component SEDFA
+ generic (
+ CHECKALWAYS : string :="DISABLED";
+ SED_CLK_FREQ : string :="3.5" ;
+ DEV_DENSITY : string :="2100L"
+ );
+ port (
+ SEDSTDBY : in std_logic;
+ SEDENABLE : in std_logic;
+ SEDSTART : in std_logic;
+ SEDFRCERR : in std_logic;
+ SEDERR : out std_logic;
+ SEDDONE : out std_logic;
+ SEDINPROG : out std_logic;
+ SEDCLKOUT : out std_logic
+ );
+ end component;
+
+ type state_t is (IDLE, INIT_1, INIT_2, INIT_3, START_1, START_2, WAITACTIVE, WAITDONE);
+ signal state : state_t;
+ signal state_bits : std_logic_vector(3 downto 0);
+
+ signal sed_edge : std_logic;
+ signal sed_clock_last : std_logic;
+
+ signal sed_clock : std_logic;
+ signal sed_done : std_logic;
+ signal sed_enable : std_logic;
+ signal sed_error : std_logic;
+ signal sed_inprogress : std_logic;
+ signal sed_start : std_logic;
+
+ signal sed_clock_q : std_logic;
+ signal sed_done_q : std_logic;
+ signal sed_error_q : std_logic;
+ signal sed_inprogress_q : std_logic;
+
+ signal status_i : std_logic_vector(31 downto 0);
+
+ signal run_counter : unsigned(7 downto 0) := (others => '0');
+ signal error_counter : unsigned(7 downto 0) := (others => '0');
+ signal timer : unsigned(22 downto 0);
+
+begin
+
+sed_clock_last <= sed_clock_q when rising_edge(CLK);
+sed_edge <= sed_clock_q and not sed_clock_last when rising_edge(CLK);
+
+sed_clock_q <= sed_clock when rising_edge(CLK);
+sed_done_q <= sed_done when rising_edge(CLK);
+sed_inprogress_q <= sed_inprogress when rising_edge(CLK);
+sed_error_q <= sed_error when rising_edge(CLK);
+
+
+---------------------------------------------------------------------------
+-- SED control state machine
+---------------------------------------------------------------------------
+proc_ctrl : process begin
+ wait until rising_edge(CLK);
+ timer <= timer + 1;
+ case state is
+ when IDLE =>
+ sed_enable <= '0';
+ sed_start <= '0';
+ if CONTROL_IN(0) = '1' then
+ state <= INIT_1;
+ timer <= (0 => '1', others => '0');
+ end if;
+ when INIT_1 =>
+ sed_enable <= '0';
+ sed_start <= '0';
+ if timer(5 downto 0) = 0 then
+ state <= INIT_2;
+ end if;
+ when INIT_2 =>
+ sed_enable <= '1';
+ sed_start <= '0';
+ if timer(5 downto 0) = 0 then
+ state <= INIT_3;
+ end if;
+ when INIT_3 =>
+ sed_enable <= '1';
+ sed_start <= '0';
+ if timer(5 downto 0) = 0 then
+ state <= START_1;
+ end if;
+ when START_1 =>
+ sed_enable <= '1';
+ sed_start <= '0';
+ if sed_edge = '1' then
+ state <= START_2;
+ end if;
+ when START_2 =>
+ sed_enable <= '1';
+ sed_start <= '1';
+ if sed_edge = '1' and sed_inprogress_q = '1' then
+ state <= WAITACTIVE;
+ end if;
+ when WAITACTIVE =>
+ sed_enable <= '1';
+ sed_start <= '1';
+ if sed_edge = '1' and sed_done_q = '0' then
+ state <= WAITDONE;
+ end if;
+ when WAITDONE =>
+ sed_enable <= '1';
+ sed_start <= '1';
+ if (sed_edge = '1' and sed_inprogress_q = '0' and sed_done_q = '1') then
+ state <= INIT_1;\r
+ timer <= (0 => '1', others => '0');
+ run_counter <= run_counter + 1;
+ if sed_error_q = '1' then
+ error_counter <= error_counter + 1;
+ end if;
+ end if;
+ end case;
+
+ if CONTROL_IN(0) = '0' or (timer = 0 and state /= IDLE) then
+ sed_enable <= '0';
+ state <= IDLE;
+ end if;
+
+end process;
+
+---------------------------------------------------------------------------
+-- Status Information
+---------------------------------------------------------------------------
+state_bits <= x"8" when state = IDLE else
+ x"1" when state = INIT_1 else
+ x"2" when state = INIT_2 else
+ x"3" when state = INIT_3 else
+ x"4" when state = START_1 else
+ x"5" when state = START_2 else
+ x"6" when state = WAITACTIVE else
+ x"7" when state = WAITDONE else
+-- x"9" when state = RESULT else
+ x"F";
+
+status_i(3 downto 0) <= state_bits;
+status_i(4) <= sed_clock_q;
+status_i(5) <= sed_enable;
+status_i(6) <= sed_start;
+status_i(7) <= sed_done_q;
+status_i(8) <= sed_inprogress_q;
+status_i(9) <= sed_error_q;
+status_i(10) <= not sed_edge;
+status_i(15 downto 11) <= (others => '0');
+status_i(23 downto 16) <= std_logic_vector(run_counter)(7 downto 0);
+status_i(31 downto 24) <= std_logic_vector(error_counter)(7 downto 0);
+
+ERROR_OUT <= sed_error;
+DEBUG <= status_i when rising_edge(CLK);
+
+---------------------------------------------------------------------------
+-- SED
+---------------------------------------------------------------------------
+THE_SED : SEDFA
+ generic map(
+ CHECKALWAYS => "DISABLED",
+ SED_CLK_FREQ => "3.5",
+ DEV_DENSITY => "2100L"
+ )
+ port map(
+ SEDSTDBY => '0',
+ SEDENABLE => sed_enable,
+ SEDSTART => sed_start,
+ SEDFRCERR => '0',
+ SEDERR => sed_error,
+ SEDDONE => sed_done,
+ SEDINPROG => sed_inprogress,
+ SEDCLKOUT => sed_clock
+ );
+
+
+end architecture;
<BaliProject version="3.2" title="L" device="LCMXO3LF-2100E-5UWG49CTR" default_implementation="L">
<Options/>
<Implementation title="L" dir="L" description="L" synthesis="synplify" default_strategy="Strategy1">
- <Options top="logicbox"/>
+ <Options def_top="uart_sctrl" top="logicbox"/>
<Source name="../logicbox.vhd" type="VHDL" type_short="VHDL">
<Options top_module="logicbox"/>
</Source>
- <Source name="../../../padiwa/source/uart_sctrl.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
<Source name="../../../trbnet/special/uart_rec.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
+ <Source name="../../code/sedcheck.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../code/uart_sctrl.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="L/L.xcf" type="Programming Project File" type_short="Programming">
+ <Options/>
+ </Source>
+ <Source name="Test/Test.spf" type="Simulation Project File" type_short="SPF">
+ <Options/>
+ </Source>
+ <Source name="sei.xcf" type="Programming Project File" type_short="Programming" excluded="TRUE">
+ <Options/>
+ </Source>
<Source name="../../pinout/logicbox.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
+ <Source name="../../../trb3/trb3_gbe/projectfrankfurt/powertest.pcf" type="Power Calculator" type_short="PCF" excluded="TRUE">
+ <Options/>
+ </Source>
</Implementation>
<Strategy name="Strategy1" file="LogicBox1.sty"/>
</BaliProject>
library machxo3lf;\r
use machxo3lf.all;\r
\r
+library work;\r
+use work.trb_net_std.all;\r
\r
entity logicbox is\r
port(\r
signal reg : std_logic_vector(31 downto 0);\r
signal last_config : std_logic_vector(3 downto 0);\r
\r
+ signal sed_error : std_logic;\r
+ signal sed_debug : std_logic_vector(31 downto 0);\r
+ signal controlsed_i : std_logic_vector(3 downto 0);\r
+ \r
component OSCH\r
generic (NOM_FREQ: string := "133.00");\r
port (\r
end process; \r
\r
LED <= led_i when led_highz = '0' else "ZZZZ";\r
+-- LED <= sed_debug(3 downto 0);\r
\r
---------------------------------------------------------------------------\r
-- UART\r
case uart_addr is\r
when x"00" => uart_tx_data <= x"0000000" & config;\r
when x"10" => uart_tx_data <= reg;\r
+ when x"ee" => uart_tx_data <= sed_debug;\r
end case;\r
elsif bus_write = '1' then\r
case uart_addr is\r
when x"10" => reg <= uart_rx_data;\r
+ when x"ee" => controlsed_i <= uart_rx_data(3 downto 0);\r
end case;\r
end if;\r
end process;\r
\r
\r
+THE_SED : entity work.sedcheck\r
+ port map(\r
+ CLK => clk_i,\r
+ ERROR_OUT => sed_error,\r
+ \r
+ CONTROL_IN => controlsed_i,\r
+ DEBUG => sed_debug\r
+ );\r
+ \r
\r
end architecture;\r
\r
jspc29 / logicbox.git / commitdiff