update SCI reader for ECP5

diff --git a/media_interfaces/med_ecp5_sfp_sync.vhd b/media_interfaces/med_ecp5_sfp_sync.vhd
index 109b4386f7171759e86d2d9878f7152a68bf5690..5b798839571aa534776d834b9ecd94165176241c 100644 (file)
--- a/media_interfaces/med_ecp5_sfp_sync.vhd
+++ b/media_interfaces/med_ecp5_sfp_sync.vhd
@@ -62,6 +62,7 @@ architecture med_ecp5_sfp_sync_arch of med_ecp5_sfp_sync is
 signal clk_200_ref       : std_logic;
 signal clk_rx_full : std_logic;
 signal clk_tx_full : std_logic;
+signal reset_n     : std_logic;
 
 signal tx_data           : std_logic_vector(7 downto 0);
 signal tx_k              : std_logic;
@@ -107,6 +108,7 @@ signal stat_med : std_logic_vector(31 downto 0);
 
 begin
 
+reset_n <= not RESET;
 clk_200_ref <= CLK_REF_FULL;
 
 SD_TXDIS_OUT <= not rx_ready when IS_SYNC_SLAVE = 1 else '0';   --slave only switches on when RX is ready
@@ -157,9 +159,9 @@ gen_pcs0 : if SERDES_NUM = 0 generate
       serdes_sync_0_sci_wrdata           => sci_data_in_i,
       serdes_sync_0_sci_rddata           => sci_data_out_i,
       serdes_sync_0_sci_addr             => sci_addr_i,
-      serdes_sync_0_sci_en_dual          => sci_ch_i(4), --?
+      serdes_sync_0_sci_en_dual          => reset_n, --sci_ch_i(4), --?
       serdes_sync_0_sci_sel_dual         => sci_ch_i(4),
-      serdes_sync_0_sci_en               => sci_ch_i(0), --?
+      serdes_sync_0_sci_en               => reset_n, --sci_ch_i(0), --?
       serdes_sync_0_sci_sel              => sci_ch_i(0),
       serdes_sync_0_sci_rd               => sci_read_i,
       serdes_sync_0_sci_wrn              => sci_write_i,

diff --git a/media_interfaces/sync/sci_reader.vhd b/media_interfaces/sync/sci_reader.vhd
index 8f17fe023bc90ce461d0c2b276f8df0af15e93bb..159bb19abf152078ca7a012b8745002af759afe7 100644 (file)
--- a/media_interfaces/sync/sci_reader.vhd
+++ b/media_interfaces/sync/sci_reader.vhd
@@ -42,6 +42,7 @@ type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GE
 signal sci_state         : sci_ctrl;
 signal sci_timer         : unsigned(12 downto 0) := (others => '0');
 signal wa_position       : std_logic_vector(15 downto 0);
+signal next_sci_wr       : std_logic;
 
 begin
 
@@ -73,12 +74,15 @@ begin
   wait until rising_edge(CLK);
   BUS_TX.ack <= '0';
   BUS_TX.nack <= '0';
+  
+  SCI_WR <= next_sci_wr;
+  
   case sci_state is
     when IDLE =>
       SCI_SEL     <= (others => '0');
       sci_reg_i   <= '0';
       SCI_RD      <= '0';
-      SCI_WR      <= '0';
+      next_sci_wr <= '0';
       sci_timer   <= sci_timer + 1;
       if BUS_RX.read = '1' or BUS_RX.write = '1' then
         SCI_SEL(0)    <= not BUS_RX.addr(6) and not BUS_RX.addr(7) and not BUS_RX.addr(8);
@@ -90,7 +94,7 @@ begin
         SCI_ADDR      <= BUS_RX.addr(5 downto 0);
         SCI_WRDATA    <= BUS_RX.data(7 downto 0);
         SCI_RD        <= BUS_RX.read  and not (BUS_RX.addr(6) and not BUS_RX.addr(7) and     BUS_RX.addr(8));
-        SCI_WR        <= BUS_RX.write and not (BUS_RX.addr(6) and not BUS_RX.addr(7) and     BUS_RX.addr(8));
+        next_sci_wr   <= BUS_RX.write and not (BUS_RX.addr(6) and not BUS_RX.addr(7) and     BUS_RX.addr(8));
         sci_state     <= SCTRL;
       elsif sci_timer(sci_timer'left) = '1' then
         sci_timer     <= (others => '0');
@@ -100,7 +104,7 @@ begin
       if sci_reg_i = '1' then
         BUS_TX.data   <= MEDIA_STATUS_REG_IN(32*(to_integer(unsigned(BUS_RX.addr(3 downto 0))))+31 downto 32*(to_integer(unsigned(BUS_RX.addr(3 downto 0)))));
         BUS_TX.ack    <= '1';
-        SCI_WR        <= '0';
+        next_sci_wr   <= '0';
         SCI_RD        <= '0';
         sci_state     <= IDLE;
       else
@@ -113,7 +117,7 @@ begin
     when SCTRL_FINISH =>
       BUS_TX.data(7 downto 0) <= SCI_RDDATA;
       BUS_TX.ack      <= '1';
-      SCI_WR          <= '0';
+      next_sci_wr     <= '0';
       SCI_RD          <= '0';
       sci_state       <= IDLE;