--- /dev/null
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+
+package config is
+
+
+------------------------------------------------------------------------------
+--Begin of design configuration
+------------------------------------------------------------------------------
+
+ constant FPGA_TYPE : integer := 3;
+--Runs with 120 MHz instead of 100 MHz
+ constant USE_120_MHZ : integer := c_NO;
+ constant USE_200MHZOSCILLATOR : integer := c_YES;
+ constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented.
+ constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)?
+
+--Use sync mode, RX clock for all parts of the FPGA
+ constant USE_RXCLOCK : integer := c_NO;
+
+--Address settings
+ constant INIT_ADDRESS : std_logic_vector := x"FFFF";
+ constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"FF";
+
+
+ constant INCLUDE_UART : integer := c_YES;
+ constant INCLUDE_SPI : integer := c_YES;
+ constant INCLUDE_ADC : integer := c_YES;
+ constant INCLUDE_I2C : integer := c_NO;
+ constant INCLUDE_DEBUG_INTERFACE: integer := c_YES;
+
+ --input monitor and trigger generation logic
+ constant INCLUDE_TRIGGER_LOGIC : integer := c_NO;
+ constant INCLUDE_STATISTICS : integer := c_NO;
+ constant TRIG_GEN_INPUT_NUM : integer := 32;
+ constant TRIG_GEN_OUTPUT_NUM : integer := 4;
+ constant MONITOR_INPUT_NUM : integer := 36;
+
+ constant USE_GBE : integer := c_YES;
+
+------------------------------------------------------------------------------
+--End of design configuration
+------------------------------------------------------------------------------
+
+
+------------------------------------------------------------------------------
+--Select settings by configuration
+------------------------------------------------------------------------------
+ type intlist_t is array(0 to 7) of integer;
+ type hw_info_t is array(0 to 7) of unsigned(31 downto 0);
+ constant HW_INFO_BASE : unsigned(31 downto 0) := x"95000000";
+
+ constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0);
+ constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0);
+
+ --declare constants, filled in body
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0);
+ constant CLOCK_FREQUENCY : integer;
+ constant MEDIA_FREQUENCY : integer;
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0);
+ constant BROADCAST_BITMASK : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1');
+
+end;
+
+package body config is
+--compute correct configuration mode
+
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector(
+ HW_INFO_BASE );
+ constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
+ constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
+
+function generateIncludedFeatures return std_logic_vector is
+ variable t : std_logic_vector(63 downto 0);
+ begin
+ t := (others => '0');
+ t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1
+ t(28 downto 28) := std_logic_vector(to_unsigned(0,1));
+ t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+ t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
+ t(45 downto 45) := std_logic_vector(to_unsigned(USE_GBE,1));
+ t(47 downto 47) := std_logic_vector(to_unsigned(INCLUDE_I2C,1));
+ t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
+ t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+ t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+ return t;
+ end function;
+
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;
+
+end package body;
--- /dev/null
+
+# implementation: "workdir"
+impl -add workdir -type fpga
+
+# device options
+set_option -technology LATTICE-ECP3
+set_option -part LFE3_150EA
+set_option -package FN1156C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -top_module "trb3sc_standalone"
+set_option -resource_sharing false
+
+# map options
+set_option -frequency 120
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 1
+set_option -pipe 1
+set_option -force_gsr false
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -compiler_compatible true
+
+set_option -max_parallel_jobs 3
+#set_option -automatic_compile_point 1
+#set_option -continue_on_error 1
+set_option -resolve_multiple_driver 1
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+# set result format/file last
+project -result_format "edif"
+project -result_file "workdir/trb3sc_standalone.edf"
+
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
+
+####################
+
+
+
+#Packages
+add_file -vhdl -lib work "workdir/version.vhd"
+add_file -vhdl -lib work "config.vhd"
+add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd"
+
+
+#Basic Infrastructure
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd"
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd"
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out200.vhd"
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd"
+add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd"
+
+
+#Fifos
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x8k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
+
+
+#Flash & Reload, Tools
+add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd"
+
+#SlowControl files
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
+
+#Media interface
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd"
+
+#TrbNet Endpoint
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_standalone_sctrl.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
+
+
+#GbE
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_protocol_selector.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/gbe_response_constructor_Ping.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/media/serdes_gbe_4ch.vhd"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/sgmii_channel_smi.v"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_pcs.v"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_cdr.v"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v"
+add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v"
+
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/ram_dp_true_2kx9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4096x9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32x8.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x72.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9_af.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb2.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2048x8x16.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_65536x18x9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/ip_mem.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_32kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9_af_cnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9_af_cnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2kx9x18_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4kx18x9_wcnt.vhd"
+
+
+
+
+
+
+
+add_file -vhdl -lib work "./trb3sc_standalone.vhd"
+#add_file -fpga_constraint "./synplify.fdc"
+
+
+
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.version.all;
+use work.config.all;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.trb_net16_hub_func.all;
+use work.version.all;
+use work.trb_net_gbe_components.all;
+use work.med_sync_define.all;
+
+entity trb3sc_standalone is
+ port(
+ CLK_SUPPL_PCLK : in std_logic; --125 MHz for GbE
+ CLK_CORE_PCLK : in std_logic; --Main Oscillator
+ CLK_EXT_PLL_LEFT : in std_logic; --External Clock
+ --CLK_SUPPL_PLL_LEFT : in std_logic; --not used
+ --CLK_SUPPL_PLL_RIGHT : in std_logic; --not used
+ --CLK_CORE_PLL_LEFT : in std_logic; --not used
+ --CLK_CORE_PLL_RIGHT : in std_logic; --not used
+ --CLK_EXT_PCLK : in std_logic; --not used
+ --CLK_EXT_PLL_RIGHT : in std_logic; --not used
+
+ TRIG_LEFT : in std_logic; --Trigger Input
+ --TRIG_PLL : in std_logic; --not used
+ --TRIG_RIGHT : in std_logic; --not used
+
+ --Backplane, all lines
+-- BACK_GPIO : inout std_logic_vector(15 downto 0);
+ BACK_LVDS : inout std_logic_vector( 1 downto 0);
+ BACK_3V3 : inout std_logic_vector( 3 downto 0);
+ --Backplane for slaves on trbv3scbp1
+ BACK_GPIO : inout std_logic_vector(3 downto 0);
+
+ --AddOn Connector
+ INP : in std_logic_vector(63 downto 0);
+
+ --KEL Connector
+ KEL : inout std_logic_vector(40 downto 1);
+ --X : out std_logic_vector(12 downto 1);
+
+ --Additional IO
+ HDR_IO : inout std_logic_vector(10 downto 1);
+ RJ_IO : inout std_logic_vector( 3 downto 0);
+ SPARE_IN : in std_logic_vector( 1 downto 0);
+
+ --LED
+ LED_GREEN : out std_logic;
+ LED_YELLOW : out std_logic;
+ LED_ORANGE : out std_logic;
+ LED_RED : out std_logic;
+ LED_RJ_GREEN : out std_logic_vector( 1 downto 0);
+ LED_RJ_RED : out std_logic_vector( 1 downto 0);
+ LED_WHITE : out std_logic_vector( 1 downto 0);
+ LED_SFP_GREEN : out std_logic_vector( 1 downto 0);
+ LED_SFP_RED : out std_logic_vector( 1 downto 0);
+
+ --SFP
+ SFP_LOS : in std_logic_vector( 1 downto 0);
+ SFP_MOD0 : in std_logic_vector( 1 downto 0);
+ SFP_MOD1 : inout std_logic_vector( 1 downto 0) := (others => 'Z');
+ SFP_MOD2 : inout std_logic_vector( 1 downto 0) := (others => 'Z');
+ SFP_TX_DIS : out std_logic_vector( 1 downto 0) := (others => '0');
+
+ --Serdes switch
+ PCSSW_ENSMB : out std_logic;
+ PCSSW_EQ : out std_logic_vector( 3 downto 0);
+ PCSSW_PE : out std_logic_vector( 3 downto 0);
+ PCSSW : out std_logic_vector( 7 downto 0);
+
+ --ADC
+ ADC_CLK : out std_logic;
+ ADC_CS : out std_logic;
+ ADC_DIN : out std_logic;
+ ADC_DOUT : in std_logic;
+
+ --Flash, 1-wire, Reload
+ FLASH_CLK : out std_logic;
+ FLASH_CS : out std_logic;
+ FLASH_IN : out std_logic;
+ FLASH_OUT : in std_logic;
+ PROGRAMN : out std_logic;
+ ENPIRION_CLOCK : out std_logic;
+ TEMPSENS : inout std_logic;
+
+ --Test Connectors
+ TEST_LINE : out std_logic_vector(15 downto 0)
+ );
+
+
+ attribute syn_useioff : boolean;
+ attribute syn_useioff of FLASH_CLK : signal is true;
+ attribute syn_useioff of FLASH_CS : signal is true;
+ attribute syn_useioff of FLASH_IN : signal is true;
+ attribute syn_useioff of FLASH_OUT : signal is true;
+
+end entity;
+
+architecture trb3sc_arch of trb3sc_standalone is
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ signal clk_sys, clk_full, clk_full_osc : std_logic;
+ signal GSR_N : std_logic;
+ signal reset_i : std_logic;
+ signal clear_i : std_logic;
+
+ signal time_counter : unsigned(31 downto 0) := (others => '0');
+ signal led : std_logic_vector(1 downto 0);
+ signal debug_clock_reset : std_logic_vector(31 downto 0);
+ signal debug_tools : std_logic_vector(31 downto 0);
+
+ --Media Interface
+ signal med2int : med2int_array_t(0 to 0);
+ signal int2med : int2med_array_t(0 to 0);
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
+
+ signal gsc_init_data : std_logic_vector(15 downto 0);
+ signal gsc_reply_data : std_logic_vector(15 downto 0);
+ signal gsc_init_read : std_logic;
+ signal gsc_reply_read : std_logic;
+ signal gsc_init_dataready : std_logic;
+ signal gsc_reply_dataready : std_logic;
+ signal gsc_init_packet_num : std_logic_vector(2 downto 0);
+ signal gsc_reply_packet_num : std_logic_vector(2 downto 0);
+ signal gsc_busy : std_logic;
+
+ signal reboot_from_gbe : std_logic;
+ signal reset_via_gbe : std_logic;
+ signal ctrlbus_rx, bussci_rx, bustools_rx, busrdo_rx, bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out : CTRLBUS_RX;
+ signal ctrlbus_tx, bussci_tx, bustools_tx, busrdo_tx, bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in : CTRLBUS_TX;
+
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+
+ signal sed_error_i : std_logic;
+ signal clock_select : std_logic;
+ signal bus_master_active : std_logic;
+
+ signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);
+
+ signal timer : TIMERS;
+ signal lcd_data : std_logic_vector(511 downto 0);
+
+ signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic;
+
+ --type a_t is array(1 to 16) of std_logic_vector(6000 downto 0);
+ --signal c : a_t;
+ --attribute syn_keep of c : signal is true;
+ --attribute syn_preserve of c : signal is true;
+
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+ attribute syn_keep of bussci_rx : signal is true;
+ attribute syn_preserve of bussci_rx : signal is true;
+ attribute syn_keep of bustools_rx : signal is true;
+ attribute syn_preserve of bustools_rx : signal is true;
+ attribute syn_keep of bustc_rx : signal is true;
+ attribute syn_preserve of bustc_rx : signal is true;
+
+
+
+ type uarr15 is array(0 to 7) of unsigned(15 downto 0);
+ signal data_counter : uarr15;
+ signal data_amount : unsigned(15 downto 0) := (others => '0');
+
+
+begin
+
+---------------------------------------------------------------------------
+-- Clock & Reset Handling
+---------------------------------------------------------------------------
+THE_CLOCK_RESET : entity work.clock_reset_handler
+ port map(
+ INT_CLK_IN => CLK_CORE_PCLK,
+ EXT_CLK_IN => CLK_EXT_PLL_LEFT,
+ NET_CLK_FULL_IN => open,
+ NET_CLK_HALF_IN => open,
+ RESET_FROM_NET => reset_via_gbe,
+ SEND_RESET_IN => '0',
+
+ BUS_RX => bustc_rx,
+ BUS_TX => bustc_tx,
+
+ RESET_OUT => reset_i,
+ CLEAR_OUT => clear_i,
+ GSR_OUT => GSR_N,
+
+ FULL_CLK_OUT => clk_full,
+ SYS_CLK_OUT => clk_sys,
+ REF_CLK_OUT => clk_full_osc,
+
+ ENPIRION_CLOCK => ENPIRION_CLOCK,
+ LED_RED_OUT => LED_RJ_RED,
+ LED_GREEN_OUT => LED_RJ_GREEN,
+ DEBUG_OUT => debug_clock_reset
+ );
+
+
+ ---------------------------------------------------------------------------
+-- GbE
+---------------------------------------------------------------------------
+ GBE : entity work.gbe_wrapper
+ generic map(
+ DO_SIMULATION => 0,
+ INCLUDE_DEBUG => 0,
+ USE_INTERNAL_TRBNET_DUMMY => 0,
+ USE_EXTERNAL_TRBNET_DUMMY => 0,
+ RX_PATH_ENABLE => 1,
+ FIXED_SIZE_MODE => 1,
+ INCREMENTAL_MODE => 1,
+ FIXED_SIZE => 100,
+ FIXED_DELAY_MODE => 1,
+ UP_DOWN_MODE => 0,
+ UP_DOWN_LIMIT => 100,
+ FIXED_DELAY => 100,
+
+ NUMBER_OF_GBE_LINKS => 4,
+ LINKS_ACTIVE => "0001",
+
+ LINK_HAS_READOUT => "0000",
+ LINK_HAS_SLOWCTRL => "0001",
+ LINK_HAS_DHCP => "0001",
+ LINK_HAS_ARP => "0001",
+ LINK_HAS_PING => "0001",
+ LINK_HAS_FWD => "0000"
+ )
+ port map(
+ CLK_SYS_IN => clk_sys,
+ CLK_125_IN => CLK_SUPPL_PCLK,
+ RESET => reset_i,
+ GSR_N => GSR_N,
+ -- Trigger
+ TRIGGER_IN => '0',
+ -- SFP
+ SD_PRSNT_N_IN(0) => SFP_MOD0(0),
+ SD_PRSNT_N_IN(3 downto 1)=> "111",
+ SD_LOS_IN(0) => SFP_LOS(0),
+ SD_LOS_IN(3 downto 1) => "111",
+ SD_TXDIS_OUT(0) => SFP_TX_DIS(0),
+ -- trigger channel
+ -- only for LINK_HAS_READOUT
+ CTS_NUMBER_IN => (others => '0'),
+ CTS_CODE_IN => (others => '0'),
+ CTS_INFORMATION_IN => (others => '0'),
+ CTS_READOUT_TYPE_IN => (others => '0'),
+ CTS_START_READOUT_IN => '0',
+ CTS_DATA_OUT => open,
+ CTS_DATAREADY_OUT => open,
+ CTS_READOUT_FINISHED_OUT => open,
+ CTS_READ_IN => '1',
+ CTS_LENGTH_OUT => open,
+ CTS_ERROR_PATTERN_OUT => open,
+ -- data channel
+ -- only for LINK_HAS_READOUT
+ FEE_DATA_IN => (others => '0'),
+ FEE_DATAREADY_IN => '0',
+ FEE_READ_OUT => open,
+ FEE_STATUS_BITS_IN => (others => '0'),
+ FEE_BUSY_IN => '0',
+ -- unique adresses
+ MC_UNIQUE_ID_IN => timer.uid,
+ MY_TRBNET_ADDRESS_IN => timer.network_address,
+ ISSUE_REBOOT_OUT => reboot_from_gbe,
+ -- slow control by GbE
+ GSC_CLK_IN => clk_sys,
+ GSC_INIT_DATAREADY_OUT => gsc_init_dataready,
+ GSC_INIT_DATA_OUT => gsc_init_data,
+ GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num,
+ GSC_INIT_READ_IN => gsc_init_read,
+ GSC_REPLY_DATAREADY_IN => gsc_reply_dataready,
+ GSC_REPLY_DATA_IN => gsc_reply_data,
+ GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num,
+ GSC_REPLY_READ_OUT => gsc_reply_read,
+ GSC_BUSY_IN => gsc_busy,
+ -- readout
+ BUS_IP_RX => busgbeip_rx, -- registers inside GbE
+ BUS_IP_TX => busgbeip_tx, -- registers inside GbE
+ BUS_REG_RX => busgbereg_rx, -- registers inside GbE
+ BUS_REG_TX => busgbereg_tx, -- registers inside GbE
+ -- Forwarder
+ FWD_DST_MAC_IN => (others => '0'),
+ FWD_DST_IP_IN => (others => '0'),
+ FWD_DST_UDP_IN => (others => '0'),
+ FWD_DATA_IN => (others => '0'),
+ FWD_DATA_VALID_IN(0) => '0',
+ FWD_SOP_IN(0) => '0',
+ FWD_EOP_IN(0) => '0',
+ FWD_READY_OUT(0) => open,
+ FWD_FULL_OUT(0) => open,
+ -- reset
+ MAKE_RESET_OUT => reset_via_gbe,
+ -- debug and status
+ STATUS_OUT => open, --open,
+ DEBUG_OUT => open --open
+ );
+
+-------------------------------------------------------------------------------
+-- SCTRL endpoint for GbE standalone
+-------------------------------------------------------------------------------
+ THE_ENDPOINT: entity trb_net16_endpoint_standalone_sctrl
+ generic map(
+ FIFO_TO_INT_DEPTH => 6,
+ FIFO_TO_APL_DEPTH => 6,
+ APL_WRITE_ALL_WORDS => c_NO,
+ INIT_ADDRESS => INIT_ADDRESS,
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"FF",
+ REGIO_INIT_ENDPOINT_ID => x"0001",
+ REGIO_USE_VAR_ENDPOINT_ID => c_NO,
+ REGIO_USE_1WIRE_INTERFACE => c_YES
+ )
+
+ port map(
+ -- Misc
+ CLK => clk_sys,
+ RESET => reset_i,
+ CLK_EN => '1',
+ --Port to GbE
+ GSC_INIT_DATAREADY_IN => gsc_init_dataready,
+ GSC_INIT_DATA_IN => gsc_init_data,
+ GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num,
+ GSC_INIT_READ_OUT => gsc_init_read,
+ GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready,
+ GSC_REPLY_DATA_OUT => gsc_reply_data,
+ GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num,
+ GSC_REPLY_READ_IN => gsc_reply_read,
+ GSC_BUSY_OUT => gsc_busy,
+ GBE_MAKE_RESET_IN => reset_via_gbe,
+ --Slow Control Port
+ --common registers 0x00-0x2F
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg,
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg,
+ REGIO_COMMON_STAT_STROBE_OUT => open,
+ REGIO_COMMON_CTRL_STROBE_OUT => open,
+ --internal data port
+ BUS_RX => ctrlbus_rx,
+ BUS_TX => ctrlbus_tx,
+ --Data port - external master (e.g. Flash or Debug)
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+ --Sensors & ID
+ ONEWIRE_INOUT => TEMPSENS,
+ -- Generic stuff
+ TIMERS_OUT => timer,
+ MY_ADDRESS_OUT => open
+ );
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+
+
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
+ generic map(
+ PORT_NUMBER => 5,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"8100", 4 => x"8300", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 8, 4 => 8, others => 0),
+ PORT_MASK_ENABLE => 1
+ )
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+
+ REGIO_RX => ctrlbus_rx,
+ REGIO_TX => ctrlbus_tx,
+
+ BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
+ BUS_RX(1) => bussci_rx, --SCI Serdes
+ BUS_RX(2) => bustc_rx, --Clock switch
+ BUS_RX(3) => busgbeip_rx,
+ BUS_RX(4) => busgbereg_rx,
+ BUS_TX(0) => bustools_tx,
+ BUS_TX(1) => bussci_tx,
+ BUS_TX(2) => bustc_tx,
+ BUS_TX(3) => busgbeip_tx,
+ BUS_TX(4) => busgbereg_tx,
+
+ STAT_DEBUG => open
+ );
+
+---------------------------------------------------------------------------
+-- Control Tools
+---------------------------------------------------------------------------
+ THE_TOOLS: entity work.trb3sc_tools
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+
+ --Flash & Reload
+ FLASH_CS => FLASH_CS,
+ FLASH_CLK => FLASH_CLK,
+ FLASH_IN => FLASH_OUT,
+ FLASH_OUT => FLASH_IN,
+ PROGRAMN => PROGRAMN,
+ REBOOT_IN => common_ctrl_reg(15),
+ --SPI
+ SPI_CS_OUT => spi_cs,
+ SPI_MOSI_OUT=> spi_mosi,
+ SPI_MISO_IN => spi_miso,
+ SPI_CLK_OUT => spi_clk,
+ --Header
+ HEADER_IO => HDR_IO,
+
+ --ADC
+ ADC_CS => ADC_CS,
+ ADC_MOSI => ADC_DIN,
+ ADC_MISO => ADC_DOUT,
+ ADC_CLK => ADC_CLK,
+ --Trigger & Monitor
+ MONITOR_INPUTS => open, --KEL(32 downto 1),--(others => '0'),
+ TRIG_GEN_INPUTS => open, --KEL(32 downto 1),--(others => '0'),
+ TRIG_GEN_OUTPUTS => open, --X(8 downto 5),--open,
+ --SED
+ SED_ERROR_OUT => sed_error_i,
+ --Slowcontrol
+ BUS_RX => bustools_rx,
+ BUS_TX => bustools_tx,
+ --Control master for default settings
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+ DEBUG_OUT => debug_tools
+ );
+
+---------------------------------------------------------------------------
+-- Switches
+---------------------------------------------------------------------------
+--Serdes Select
+ PCSSW_ENSMB <= '0';
+ PCSSW_EQ <= x"0";
+ PCSSW_PE <= x"F";
+ PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1
+
+---------------------------------------------------------------------------
+-- I/O
+---------------------------------------------------------------------------
+
+ RJ_IO <= "0000";
+
+-- BACK_GPIO <= (others => 'Z');
+ BACK_LVDS <= (others => '0');
+ BACK_3V3 <= (others => 'Z');
+
+
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+ --LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2)
+ LED_GREEN <= debug_clock_reset(0);
+ LED_ORANGE <= debug_clock_reset(1);
+ LED_RED <= not sed_error_i;
+ LED_YELLOW <= debug_clock_reset(2);
+ LED_WHITE(0) <= time_counter(26) and time_counter(19);
+ LED_WHITE(1) <= time_counter(20);
+ LED_SFP_GREEN <= "11"; --SFP Link Status
+ LED_SFP_RED <= "11"; --SFP RX/TX
+
+---------------------------------------------------------------------------
+-- Test Circuits
+---------------------------------------------------------------------------
+ process begin
+ wait until rising_edge(clk_sys);
+ time_counter <= time_counter + 1;
+ if reset_i = '1' then
+ time_counter <= (others => '0');
+ end if;
+ end process;
+
+TEST_LINE <= (others => '0');
+
+
+
+end architecture;
+
+
+
jspc29 / trb3sc.git / commitdiff