*** empty log message ***

diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd
index a4954d28d9a146b523eea0e36f85677c6a698fda..3e70ffafac3103718ab4f9ba299c51d5ee0f8125 100644 (file)
--- a/trb_net16_api_base.vhd
+++ b/trb_net16_api_base.vhd
@@ -687,7 +687,7 @@ begin
                 next_state_to_apl <= sa_IDLE;
               end if;
             elsif API_TYPE = 1 then
-              if state_to_int /= IDLE then
+              if master_start = '1' then
                 next_state_to_apl <= sa_IDLE;
               end if;
             end if;

diff --git a/xilinx/virtex2/xilinx_fifo_dualport_18x1k.xco b/xilinx/virtex2/xilinx_fifo_dualport_18x1k.xco
index c63d98f47d230ce1beecb3246a13842299c404af..964c002c3b51af215f76d8d6517d1c899744565f 100644 (file)
--- a/xilinx/virtex2/xilinx_fifo_dualport_18x1k.xco
+++ b/xilinx/virtex2/xilinx_fifo_dualport_18x1k.xco
@@ -2,7 +2,7 @@
 SET flowvendor = Foundation_iSE
 SET vhdlsim = True
 SET verilogsim = True
-SET workingdirectory = /d/jspc22/trb/ot_trb/ise8
+SET workingdirectory = .
 SET speedgrade = -5
 SET simulationfiles = Behavioral
 SET asysymbol = True