tidy up some files and make the compilation working.
--- /dev/null
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+#################################################################
+# Basic Settings
+#################################################################
+
+ #SYSCONFIG MCCLK_FREQ = 2.5;
+
+ #FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+ #FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
+ #FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+ #FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
+
+#################################################################
+# Clock I/O
+#################################################################
+LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20";
+LOCATE COMP "CLK_PCLK_LEFT" SITE "M4";
+LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";
+LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1";
+LOCATE COMP "CLK_GPLL_LEFT" SITE "U25";
+
+DEFINE PORT GROUP "CLK_group" "CLK*" ;
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25;
+
+
+#################################################################
+# Trigger I/O
+#################################################################
+
+#Trigger from fan-out
+LOCATE COMP "TRIGGER_LEFT" SITE "V3";
+LOCATE COMP "TRIGGER_RIGHT" SITE "N24";
+IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ;
+
+
+#################################################################
+# To central FPGA
+#################################################################
+
+LOCATE COMP "FPGA5_COMM_0" SITE "AD4";
+LOCATE COMP "FPGA5_COMM_1" SITE "AE3";
+LOCATE COMP "FPGA5_COMM_2" SITE "AA7";
+LOCATE COMP "FPGA5_COMM_3" SITE "AB7";
+LOCATE COMP "FPGA5_COMM_4" SITE "AD3";
+LOCATE COMP "FPGA5_COMM_5" SITE "AC4";
+LOCATE COMP "FPGA5_COMM_6" SITE "AE2";
+LOCATE COMP "FPGA5_COMM_7" SITE "AF3";
+LOCATE COMP "FPGA5_COMM_8" SITE "AE4";
+LOCATE COMP "FPGA5_COMM_9" SITE "AF4";
+LOCATE COMP "FPGA5_COMM_10" SITE "V10";
+LOCATE COMP "FPGA5_COMM_11" SITE "W10";
+DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
+IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+
+LOCATE COMP "TEST_LINE_0" SITE "A5";
+LOCATE COMP "TEST_LINE_1" SITE "A6";
+LOCATE COMP "TEST_LINE_2" SITE "G8";
+LOCATE COMP "TEST_LINE_3" SITE "F9";
+LOCATE COMP "TEST_LINE_4" SITE "D9";
+LOCATE COMP "TEST_LINE_5" SITE "D10";
+LOCATE COMP "TEST_LINE_6" SITE "F10";
+LOCATE COMP "TEST_LINE_7" SITE "E10";
+LOCATE COMP "TEST_LINE_8" SITE "A8";
+LOCATE COMP "TEST_LINE_9" SITE "B8";
+LOCATE COMP "TEST_LINE_10" SITE "G10";
+LOCATE COMP "TEST_LINE_11" SITE "G9";
+LOCATE COMP "TEST_LINE_12" SITE "C9";
+LOCATE COMP "TEST_LINE_13" SITE "C10";
+LOCATE COMP "TEST_LINE_14" SITE "H10";
+LOCATE COMP "TEST_LINE_15" SITE "H11";
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 SLEWRATE=FAST;
+
+#################################################################
+# Connection to AddOn
+#################################################################
+#All DQ groups from one bank are grouped.
+#All DQS are inserted in the DQ lines at position 6 and 7
+#DQ 6-9 are shifted to 8-11
+#Order per bank is kept, i.e. adjacent numbers have adjacent pins
+#all DQ blocks are 6+2+4=12 Pins wide, only DQUL3 and DQUR0 are 6+2+2=10.
+#even numbers are positive LVDS line, odd numbers are negative LVDS line
+#DQUL can be switched to 1.8V
+
+
+
+# nXyter 1
+
+LOCATE COMP "NX1_TESTPULSE_OUT" SITE "T7"; #DQLL1_8 #46
+LOCATE COMP "NX1_MAIN_CLK_OUT" SITE "AB1"; #DQLL2_2 #29
+LOCATE COMP "NX1_RESET_OUT" SITE "V6"; #DQLL2_8 #45
+#LOCATE COMP "NX1_DATA_CLK_IN" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69
+LOCATE COMP "NX1_DATA_CLK_IN" SITE "K4"; #DQSUL2_T #62 see DQUL3_8_OUTOFLANE
+
+LOCATE COMP "NX1_I2C_SM_RESET_OUT" SITE "P4"; #DQLL1_4 #34
+LOCATE COMP "NX1_I2C_REG_RESET_OUT" SITE "R3"; #DQLL1_5 #36
+LOCATE COMP "NX1_I2C_SDA_INOUT" SITE "R5"; #DQLL1_6 #42
+LOCATE COMP "NX1_I2C_SCL_INOUT" SITE "R6"; #DQLL1_7 #44
+
+LOCATE COMP "NX1_ADC_D_IN" SITE "B2"; #DQUL0_0 #74
+LOCATE COMP "NX1_ADC_A_IN" SITE "D4"; #DQUL0_2 #78
+LOCATE COMP "NX1_ADC_NX_IN" SITE "C3"; #DQUL0_4 #82
+LOCATE COMP "NX1_ADC_DCLK_IN" SITE "G5"; #DQSUL0_T #86
+LOCATE COMP "NX1_ADC_B_IN" SITE "E3"; #DQUL0_6 #90
+LOCATE COMP "NX1_ADC_FCLK_IN" SITE "H6"; #DQUL0_8 #94
+LOCATE COMP "NX1_ADC_SAMPLE_CLK_OUT" SITE "H5"; #DQUL1_6 #89
+
+LOCATE COMP "NX1_SPI_SDIO_INOUT" SITE "G2"; #DQUL1_0 #73
+LOCATE COMP "NX1_SPI_SCLK_OUT" SITE "F2"; #DQUL1_2 #77
+LOCATE COMP "NX1_SPI_CSB_OUT" SITE "C2"; #DQUL1_4 #81
+
+LOCATE COMP "NX1_TIMESTAMP_IN_0" SITE "K2"; #DQUL2_0 #50
+LOCATE COMP "NX1_TIMESTAMP_IN_1" SITE "J4"; #DQUL2_2 #54
+LOCATE COMP "NX1_TIMESTAMP_IN_2" SITE "D1"; #DQUL2_4 #58
+LOCATE COMP "NX1_TIMESTAMP_IN_3" SITE "E1"; #DQUL2_6 #66
+
+#LOCATE COMP "NX1_TIMESTAMP_IN_4" SITE "L5"; #DQUL2_8 #70
+LOCATE COMP "NX1_TIMESTAMP_IN_4" SITE "L2"; #DQUL3_6 #
+
+LOCATE COMP "NX1_TIMESTAMP_IN_5" SITE "H2"; #DQUL3_0 #49
+LOCATE COMP "NX1_TIMESTAMP_IN_6" SITE "K3"; #DQUL3_2 #53
+LOCATE COMP "NX1_TIMESTAMP_IN_7" SITE "H1"; #DQUL3_4 #57
+
+
+
+#DEFINE PORT GROUP "LVDS_group1" "NX1_TIMESTAMP*" ;
+#IOBUF GROUP "LVDS_group1" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+IOBUF PORT "NX1_TIMESTAMP_IN_0" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+IOBUF PORT "NX1_TIMESTAMP_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+IOBUF PORT "NX1_TIMESTAMP_IN_2" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+IOBUF PORT "NX1_TIMESTAMP_IN_3" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+IOBUF PORT "NX1_TIMESTAMP_IN_4" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+IOBUF PORT "NX1_TIMESTAMP_IN_5" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+IOBUF PORT "NX1_TIMESTAMP_IN_6" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+IOBUF PORT "NX1_TIMESTAMP_IN_7" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+
+#DEFINE PORT GROUP "LVDS_group2" "NX1_ADC*IN" ;
+#IOBUF GROUP "LVDS_group2" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+IOBUF PORT "NX1_ADC_D_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+IOBUF PORT "NX1_ADC_A_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+IOBUF PORT "NX1_ADC_DCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+IOBUF PORT "NX1_ADC_NX_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+IOBUF PORT "NX1_ADC_B_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+IOBUF PORT "NX1_ADC_FCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+IOBUF PORT "NX1_ADC_SAMPLE_CLK_OUT" IO_TYPE=LVDS25;
+
+IOBUF PORT "NX1_DATA_CLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
+IOBUF PORT "NX1_TESTPULSE_OUT" IO_TYPE=LVDS25;
+IOBUF PORT "NX1_MAIN_CLK_OUT" IO_TYPE=LVDS25;
+IOBUF PORT "NX1_RESET_OUT" IO_TYPE=LVDS25;
+
+IOBUF PORT "NX1_I2C_SM_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN;
+IOBUF PORT "NX1_I2C_REG_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
+IOBUF PORT "NX1_I2C_SDA_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
+IOBUF PORT "NX1_I2C_SCL_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
+
+IOBUF PORT "NX1_SPI_SDIO_INOUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=4;
+IOBUF PORT "NX1_SPI_SCLK_OUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=4;
+IOBUF PORT "NX1_SPI_CSB_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4;
+
+# Nxyter Debug Lines Addon Board
+LOCATE COMP "NX1_DEBUG_LINE_1" SITE "R25"; #DQLR2_0 #170
+LOCATE COMP "NX1_DEBUG_LINE_3" SITE "R26"; #DQLR2_1 #172
+LOCATE COMP "NX1_DEBUG_LINE_5" SITE "T25"; #DQLR2_2 #174
+LOCATE COMP "NX1_DEBUG_LINE_7" SITE "T24"; #DQLR2_3 #176
+LOCATE COMP "NX1_DEBUG_LINE_9" SITE "T26"; #DQLR2_4 #178
+LOCATE COMP "NX1_DEBUG_LINE_11" SITE "U26"; #DQLR2_5 #180
+LOCATE COMP "NX1_DEBUG_LINE_13" SITE "U24"; #DQLR2_6 #186
+LOCATE COMP "NX1_DEBUG_LINE_15" SITE "V24"; #DQLR2_7 #188
+LOCATE COMP "NX1_DEBUG_LINE_14" SITE "W23"; #DQLR1_0 #169
+LOCATE COMP "NX1_DEBUG_LINE_12" SITE "W22"; #DQLR1_1 #171
+LOCATE COMP "NX1_DEBUG_LINE_10" SITE "AA25"; #DQLR1_2 #173
+LOCATE COMP "NX1_DEBUG_LINE_8" SITE "Y24"; #DQLR1_3 #175
+LOCATE COMP "NX1_DEBUG_LINE_6" SITE "AA26"; #DQLR1_4 #177
+LOCATE COMP "NX1_DEBUG_LINE_4" SITE "AB26"; #DQLR1_5 #179
+LOCATE COMP "NX1_DEBUG_LINE_2" SITE "AA24"; #DQLR1_6 #185
+LOCATE COMP "NX1_DEBUG_LINE_0" SITE "AA23"; #DQLR1_7 #187
+
+DEFINE PORT GROUP "NX1_DEBUG_LINE_group" "NX1_DEBUG_LINE_*" ;
+IOBUF GROUP "NX1_DEBUG_LINE_group" IO_TYPE=LVCMOS25 SLEWRATE=FAST;
+
+#################################################################
+# Additional Lines to AddOn
+#################################################################
+
+#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
+#all lines are input only
+#line 4/5 go to PLL input
+#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194
+#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196
+#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198
+#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200
+
+
+
+#################################################################
+# Flash ROM and Reboot
+#################################################################
+
+LOCATE COMP "FLASH_CLK" SITE "B12";
+LOCATE COMP "FLASH_CS" SITE "E11";
+LOCATE COMP "FLASH_DIN" SITE "E12";
+LOCATE COMP "FLASH_DOUT" SITE "A12";
+
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+
+LOCATE COMP "PROGRAMN" SITE "B11";
+IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+
+
+#################################################################
+# Misc
+#################################################################
+LOCATE COMP "TEMPSENS" SITE "A13";
+IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+
+#coding of FPGA number
+LOCATE COMP "CODE_LINE_1" SITE "AA20";
+LOCATE COMP "CODE_LINE_0" SITE "Y21";
+IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+
+#terminated differential pair to pads
+#LOCATE COMP "SUPPL" SITE "C14";
+#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
+
+
+#################################################################
+# LED
+#################################################################
+LOCATE COMP "LED_GREEN" SITE "F12";
+LOCATE COMP "LED_ORANGE" SITE "G13";
+LOCATE COMP "LED_RED" SITE "A15";
+LOCATE COMP "LED_YELLOW" SITE "A16";
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12;
+++ /dev/null
-TARGET=trb3_periph_nxyter
-FAMILYNAME=LatticeECP3
-DEVICENAME=LFE3-150EA
-PACKAGE=FPBGA672
-SPEEDGRADE=8
-
-TIMESTAMP=$(shell date '+%s')
-VERSION=$(shell cat version-major-minor.txt)
-
-# ------------------------------------------------------------------------------------
-
-.PHONY: all
-all: workdir/$(TARGET).bit
-
-.PHONY: clean
-clean:
- rm -rf workdir/*
-
-.PHONY: distclean
-distclean:
- rm -rf workdir/*
-
-.PHONY: checkenv
-checkenv:
- @echo ""
- @echo "----------------------------------------------------------------------"
- @echo "--------------- Check Lattice Environment ---------------"
- @echo "----------------------------------------------------------------------"
- @if [ -n "${LM_LICENSE_FILE}" ] ; then \
- echo "Lattice Environment is: ${LM_LICENSE_FILE}"; \
- else \
- echo "------> Lattice Environment is not set"; \
- exit 1; \
- fi
-
-# ------------------------------------------------------------------------------------
-
-# Bitgen
-workdir/$(TARGET).bit: workdir/$(TARGET).ncd
- @$(MAKE) report
-
- @echo ""
- @echo "----------------------------------------------------------------------"
- @echo "-------------- Bitgen ------------------------------------------------"
- @echo "----------------------------------------------------------------------"
- cd workdir && \
- bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $(TARGET).ncd \
- $(TARGET).bit $(TARGET).prf
-
- @$(MAKE) error
-
-# Place and Route (multipar)
-workdir/$(TARGET).ncd: workdir/$(TARGET)_map.ncd
- @echo ""
- @echo "----------------------------------------------------------------------"
- @echo "-------------- Place and Route (multipar)-----------------------------"
- @echo "----------------------------------------------------------------------"
- rm -rf workdir/$(TARGET).ncd workdir/$(TARGET).dir
- cd workdir && \
- par -f ../$(TARGET).p2t $(TARGET)_map.ncd $(TARGET).dir $(TARGET).prf
- cp workdir/$(TARGET).dir/*.ncd workdir/$(TARGET).ncd
-
-# Mapper
-workdir/$(TARGET)_map.ncd: workdir/$(TARGET).ngd $(TARGET).lpf
- @echo ""
- @echo "----------------------------------------------------------------------"
- @echo "-------------- Mapper ------------------------------------------------"
- @echo "----------------------------------------------------------------------"
- cd workdir && \
- map -retime -split_node -a $(FAMILYNAME) -p $(DEVICENAME) \
- -t $(PACKAGE) -s $(SPEEDGRADE) $(TARGET).ngd -pr $(TARGET).prf \
- -o $(TARGET)_map.ncd -mp $(TARGET).mrp $(TARGET).lpf
-
-# EDIF 2 NGD
-workdir/$(TARGET).ngd: workdir/$(TARGET).edf
- @echo ""
- @echo "----------------------------------------------------------------------"
- @echo "-------------- EDIF 2 NGD---------------------------------------------"
- @echo "----------------------------------------------------------------------"
- cd workdir && \
- edif2ngd -l $(FAMILYNAME) -d $(DEVICENAME) \$(TARGET).edf $(TARGET).ngo
- cd workdir && \
- edfupdate -t $(TARGET).tcy -w $(TARGET).ngo -m $(TARGET).ngo \
- $(TARGET).ngx
- cd workdir && \
- ngdbuild -a $(FAMILYNAME) -d $(DEVICENAME) -dt $(TARGET).ngo \
- $(TARGET).ngd
-
-# VHDL / Verilog Compiler
-workdir/$(TARGET).edf:
- @echo ""
- @echo "----------------------------------------------------------------------"
- @echo "--------------- Build All --------------------------------------------"
- @echo "----------------------------------------------------------------------"
- @$(MAKE) checkenv
- @$(MAKE) workdir
- @$(MAKE) version
-
- @echo ""
- @echo "----------------------------------------------------------------------"
- @echo "--------------- VHDL Compiler ----------------------------------------"
- @echo "----------------------------------------------------------------------"
- synpwrap -prj $(TARGET).prj || \
- (grep "@E" workdir/$(TARGET).srr && exit 2)
-
-# ------------------------------------------------------------------------------------
-
-# Version File
-.PHONY: version
-version:
- @echo ""
- @echo "----------------------------------------------------------------------"
- @echo "--------------- Version File -----------------------------------------"
- @echo "----------------------------------------------------------------------"
- @echo "-- attention, automatically generated. Don't change by hand." > version.vhd
- @echo "library ieee;" >> version.vhd
- @echo "USE IEEE.std_logic_1164.ALL;" >> version.vhd
- @echo "USE IEEE.std_logic_ARITH.ALL;" >> version.vhd
- @echo "USE IEEE.std_logic_UNSIGNED.ALL;" >> version.vhd
- @echo "use ieee.numeric_std.all;" >> version.vhd
- @echo "" >> version.vhd
- @echo "package version is" >> version.vhd
- @echo "" >> version.vhd
- @echo " constant VERSION_NUMBER_TIME : integer := $(TIMESTAMP);" >> version.vhd
- @echo -n " constant VERSION_NUMBER : integer := " >> version.vhd
- @echo "to_integer(x\"$(VERSION)\");" >> version.vhd
- @echo "" >> version.vhd
- @echo "end package version;" >> version.vhd
- @cat version.vhd
-
-# Setup Workdir
-.PHONY: workdir
-workdir:
- @echo ""
- @echo "----------------------------------------------------------------------"
- @echo "-------------- Setup Workdir -----------------------------------------"
- @echo "----------------------------------------------------------------------"
- mkdir -p workdir
- cd workdir && ../../base/linkdesignfiles.sh
- cp $(TARGET).lpf workdir/$(TARGET).lpf
- cat $(TARGET)_constraints.lpf >> workdir/$(TARGET).lpf
- cp nodelist.txt workdir/
-
-# Timing Report
-.PHONY: report
-report:
- @echo ""
- @echo "----------------------------------------------------------------------"
- @echo "-------------- Timing Report -----------------------------------------"
- @echo "----------------------------------------------------------------------"
- cd workdir && \
- iotiming -s $(TARGET).ncd $(TARGET).prf
- cd workdir && \
- trce -c -v 15 -o $(TARGET).twr.setup $(TARGET).ncd $(TARGET).prf
- cd workdir && \
- trce -hld -c -v 5 -o $(TARGET).twr.hold $(TARGET).ncd $(TARGET).prf
- cd workdir && \
- ltxt2ptxt $(TARGET).ncd
-
-# Error Check
-.PHONY: error
-error:
- @echo ""
- @echo "----------------------------------------------------------------------"
- @echo "-------------- Error Check -----------------------------------------"
- @echo "----------------------------------------------------------------------"
- @echo -e "\n$(TARGET).mrp:"
- @grep "Semantic error" ./workdir/$(TARGET).mrp || exit 0
-
- @echo -e "\n$(TARGET).twr.setup:"
- @grep 'Error: The following path exceeds requirements by' ./workdir/$(TARGET).twr.setup \
- || exit 0
-
- @echo -e "\n$(TARGET).twr.hold:"
- @grep "Error:" ./workdir/$(TARGET).twr.hold || exit 0
-
- @echo -e "\nCircuit Loops:"
- @grep "potential circuit loops" ./workdir/* || exit 0
-
-# ------------------------------------------------------------------------------------
-# Extract dependencies from project file
-#.PHONY: $(TARGET).dep
-#$(TARGET).dep:
-# @echo ""
-# @echo "----------------------------------------------------------------------"
-# @echo "--------------- Extract Dependencies from Project File ---------------"
-# @echo "----------------------------------------------------------------------"
-# grep 'add_file' $(TARGET).prj | grep -v '#' | sed -r 's/^.*"(.*)"$$/\1/' \
-# | xargs echo "workdir/$(TARGET).edf:" > $(TARGET).dep
-# grep 'map_dep' $(TARGET).prj | grep -v '#' | sed -r 's/^.*"(.*)"$$/\1/' \
-# | xargs echo "workdir/$(TARGET)_map.ncd:" >> $(TARGET).dep
-#
-#-include $(TARGET).dep
-
--- /dev/null
+../../trb3sc/scripts/compile.pl
\ No newline at end of file
+++ /dev/null
-#!/usr/bin/perl
-use Data::Dumper;
-use warnings;
-use strict;
-
-
-
-
-###################################################################################
-#Settings for this project
-my $TOPNAME = "trb3_periph"; #Name of top-level entity
-my $lattice_path = '/usr/local/opt/lattice_diamond/diamond/3.2';
-my $synplify_path = '/usr/local/opt/synplify/I-2013.09-SP1/';
-my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
-my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
-###################################################################################
-
-
-use FileHandle;
-
-$ENV{'SYNPLIFY'}=$synplify_path;
-$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
-#$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
-
-my $FAMILYNAME="LatticeECP3";
-my $DEVICENAME="LFE3-150EA";
-my $PACKAGE="FPBGA672";
-my $SPEEDGRADE="8";
-
-
-#create full lpf file
-system("cp ./$TOPNAME"."_nxyter.lpf workdir/$TOPNAME.lpf");
-system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf");
-
-#set -e
-#set -o errexit
-
-#generate timestamp
-my $t=time;
-my $fh = new FileHandle(">version.vhd");
-die "could not open file" if (! defined $fh);
-print $fh <<EOF;
-
---## attention, automatically generated. Don't change by hand.
-library ieee;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use ieee.numeric_std.all;
-
-package version is
-
- constant VERSION_NUMBER_TIME : integer := $t;
-
-end package version;
-EOF
-$fh->close;
-
-system("env| grep LM_");
-my $r = "";
-my $c = "";
-
-$c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
-$r=execute($c, "do_not_exit" );
-
-
-chdir "workdir";
-$fh = new FileHandle("<$TOPNAME".".srr");
-my @a = <$fh>;
-$fh -> close;
-
-foreach (@a)
-{
- if(/\@E:/)
- {
- print STDERR "\n";
- $c="cat $TOPNAME.srr | grep \"\@E\"";
- system($c);
- print STDERR "\n\n";
- exit 129;
- }
-}
-
-
-$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
-
-$c=qq| $lattice_path/ispfpga/bin/lin64/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin64/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin64/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
-execute($c);
-
-my $tpmap = $TOPNAME . "_map" ;
-
-$c=qq|$lattice_path/ispfpga/bin/lin64/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
-execute($c);
-
-system("rm -vf $TOPNAME.ncd");
-system("rm -vf $TOPNAME.dir/*");
-
-$c=qq|$lattice_path/ispfpga/bin/lin64/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.dir" "$TOPNAME.prf"|;
-execute($c, "do_not_exit");
-
-print STDERR "Do 0\n";
-
-system("cp -va ${TOPNAME}.dir/*.ncd ./${TOPNAME}.ncd");
-
-print STDERR "Do 1\n";
-
-
-# IOR IO Timing Report
-$c=qq|$lattice_path/ispfpga/bin/lin64/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-print STDERR "Do 2\n";
-
-# TWR Timing Report
-$c=qq|$lattice_path/ispfpga/bin/lin64/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-print STDERR "Do 3\n";
-
-$c=qq|$lattice_path/ispfpga/bin/lin64/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-print STDERR "Do 4\n";
-
-$c=qq|$lattice_path/ispfpga/bin/lin64/ltxt2ptxt $TOPNAME.ncd|;
-execute($c);
-
-print STDERR "Do 5\n";
-
-$c=qq|$lattice_path/ispfpga/bin/lin64/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|;
-# $c=qq|$lattice_path/ispfpga/bin/lin64/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|;
-
-print STDERR "Do 6\n";
-
-execute($c);
-
-chdir "..";
-
-exit;
-
-sub execute {
- my ($c, $op) = @_;
- #print STDERR "option: $op \n";
- $op = "" if(!$op);
- print STDERR "\n\ncommand to execute: $c \n";
- $r=system($c);
- if($r) {
- print STDERR "$!";
- if($op ne "do_not_exit") {
- print STDERR "------- EXIT by function execute --------\n";
- exit;
- }
- }
-
- return $r;
-
-}
+++ /dev/null
-#!/bin/sh
-
-. /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env
-
-./compile_munich32.pl
-
-#grep -q 'Error:' ./workdir/trb3_periph.twr.setup && echo "Timing Errors found in trb3_periph.twr.setup"
-grep 'Error: The following path exceeds requirements by' ./workdir/trb3_periph.twr.setup
-grep 'Error:' ./workdir/trb3_periph.twr.hold
-grep 'potential circuit loops' ./workdir/*
-
-echo "Script DONE!"
--- /dev/null
+TOPNAME => "trb3_periph_blank",
+lm_license_file_for_synplify => "1702\@jspc29", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_par => "1702\@jspc29",
+lattice_path => '/d/jspc29/lattice/diamond/3.6_x64',
+synplify_path => '/d/jspc29/lattice/synplify/J-2014.09-SP2/',
+synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
+#synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
+
+nodelist_file => 'nodes_frankfurt.txt',
+pinout_file => 'trb3_periph_ada',
+
+#Include only necessary lpf files
+#pinout_file => '', #name of pin-out file, if not equal TOPNAME
+include_TDC => 0,
+include_GBE => 0,
+
+#Report settings
+firefox_open => 0,
+twr_number_of_errors => 20,
+
+Familyname => 'LatticeECP3',
+Devicename => 'LFE3-150EA',
+Package => 'FPBGA672',
+Speedgrade => '8',
\ No newline at end of file
--- /dev/null
+Familyname => 'LatticeECP3',
+Devicename => 'LFE3-150EA',
+Package => 'FPBGA672',
+Speedgrade => '8',
+
+TOPNAME => "trb3_periph_nxyter",
+project_path => "nxyter",
+lm_license_file_for_synplify => "27000\@lxcad01.gsi.de",
+lm_license_file_for_par => "1702\@hadeb05.gsi.de",
+lattice_path => '/opt/lattice/diamond/3.6_x64',
+synplify_path => '/opt/synplicity/K-2015.09',
+#synplify_command => "/opt/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
+synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp",
+#pinout_file => '../nxyter/trb3_periph_nxyter',
+nodelist_file => '../nodes_lxhadeb07.txt',
+
+#Include only necessary lpf files
+include_TDC => 0,
+include_GBE => 0,
+
+#Report settings
+firefox_open => 0,
+twr_number_of_errors => 20,
--- /dev/null
+-w
+-y
+-l 5
+#-m nodelist.txt # Controlled by the compile.pl script.
+#-n 1 # Controlled by the compile.pl script.
+-s 12
+-t 1
+-c 1
+-e 2
+-i 15
+-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:
+
+
+#General PAR Command Line Options
+# -w With this option, any files generated will overwrite existing files
+# (e.g., any .par, .pad files).
+# -y Adds the Delay Summary Report in the .par file and creates the delay
+# file (in .dly format) at the end of the par run.
+#
+#PAR Placement Command Line Options
+# -l Specifies the effort level of the design from 1 (simplest designs)
+# to 5 (most complex designs).
+# -m Multi-tasking option. Controlled by the compile.pl script.
+# -n Sets the number of iterations performed at the effort level
+# specified by the -l option. Controlled by the compile.pl script.
+# -s Save the number of best results for this run.
+# -t Start placement at the specified cost table. Default is 1.
+#
+#PAR Routing Command Line Options
+# -c Run number of cost-based cleanup passes of the router.
+# -e Run number of delay-based cleanup passes of the router on
+# completely-routed designs only.
+# -i Run a maximum number of passes, stopping earlier only if the routing
+# goes to 100 percent completion and all constraints are met.
+#
+#PAR Explorer Command Line Options
+# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is
+# compatible with all Lattice FPGA device families; however, most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families.
+# parCDR Enable the congestion-driven router (CDR) algorithm.
+# Congestion-driven options like parCDR and parCDP can improve
+# performance given a design with multiple congestion “hotspots.” The
+# Layer > Congestion option of the Design Planner Floorplan View can
+# help visualize routing congestion. Large congested areas may prevent
+# the options from finding a successful solution.
+# CDR is compatible with all Lattice FPGA device families however most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families.
+# paruseNBR NBR Router or Negotiation-based routing option. Supports all
+# FPGA device families except LatticeXP and MachXO.
+# When turned on, an alternate routing engine from the traditional
+# Rip-up-based routing selection (RBR) is used. This involves an
+# iterative routing algorithm that routes connections to achieve
+# minimum delay cost. It does so by computing the demand on each
+# routing resource and applying cost values per node. It will
+# complete when an optimal solution is arrived at or the number of
+# iterations is reached.
+# parPathBased Path-based placement option. Path-based timing driven
+# placement will yield better performance and more
+# predictable results in many cases.
+# parHold Additional hold time correction option. This option
+# forces the router to automatically insert extra wires to compensate for the
+# hold time violation.
+# parHoldLimit This option allows you to set a limit on the number of
+# hold time violations to be processed by the auto hold time correction option
+# parHold.
+# parPlcInLimit Cannot find in the online help
+# parPlcInNeighborSize Cannot find in the online help
+#######################################################################
+
+
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
BLOCK RD_DURING_WR_PATHS ;
# Basic Settings
#################################################################
- #SYSCONFIG MCCLK_FREQ = 2.5;
-
- #FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
- #FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
- #FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
- #FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
+# nXyter FEB Clock Setup:
+#
+# CLK_PCLK_RIGHT : real Oszillator 200MHz
+# CLK_PCLK_RIGHT --> PLL#0 --> clk_100_i -----> Main Clock all entities
+#
+# CLK_PCLK_RIGHT --> nx_main_clk 1+2
+# (250 MHz) -----> nXyter Main Clock 1+2
+# |
+# |----> FPGA Timestamp Entity 1+2
+#
+# nx_main_clk 1+2 --> nXyter Data Clk
+# (1/2 = 125MHz) -----> FPGA Data Receiver
+# |
+# |----> Johnson 1/4 --> ADC SCLK
+#
+# ADC_DATA_CLK --> ADC Data Clk -----> FPGA ADC Handler
+# DDR (187.5 MHz)
-#################################################################
-# Clock I/O
-#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20";
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4";
-LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";
-LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1";
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25";
-DEFINE PORT GROUP "CLK_group" "CLK*" ;
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25;
+# Speed for the configuration Flash access
+SYSCONFIG MCCLK_FREQ = 20;
+FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+FREQUENCY PORT NX1_DATA_CLK_IN 125 MHz;
+FREQUENCY PORT NX1_ADC_DCLK_IN 187.5 MHz;
+FREQUENCY NET "nXyter_FEE_board_0/nx_data_receiver_1/DDR_DATA_CLK" 93.750000 MHz;
+USE PRIMARY NET "CLK_PCLK_RIGHT_c";
+USE PRIMARY NET "clk_100_i";
+USE PRIMARY NET "nx_main_clk";
+USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/DDR_DATA_CLK";
+
#################################################################
-# Trigger I/O
-#################################################################
-
-#Trigger from fan-out
-LOCATE COMP "TRIGGER_LEFT" SITE "V3";
-LOCATE COMP "TRIGGER_RIGHT" SITE "N24";
-IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
-IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ;
+# Reset Nets
+#################################################################
+# GSR_NET NET "GSR_N";
#################################################################
-# To central FPGA
+# Locate Serdes and media interfaces
#################################################################
-LOCATE COMP "FPGA5_COMM_0" SITE "AD4";
-LOCATE COMP "FPGA5_COMM_1" SITE "AE3";
-LOCATE COMP "FPGA5_COMM_2" SITE "AA7";
-LOCATE COMP "FPGA5_COMM_3" SITE "AB7";
-LOCATE COMP "FPGA5_COMM_4" SITE "AD3";
-LOCATE COMP "FPGA5_COMM_5" SITE "AC4";
-LOCATE COMP "FPGA5_COMM_6" SITE "AE2";
-LOCATE COMP "FPGA5_COMM_7" SITE "AF3";
-LOCATE COMP "FPGA5_COMM_8" SITE "AE4";
-LOCATE COMP "FPGA5_COMM_9" SITE "AF4";
-LOCATE COMP "FPGA5_COMM_10" SITE "V10";
-LOCATE COMP "FPGA5_COMM_11" SITE "W10";
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-
-LOCATE COMP "TEST_LINE_0" SITE "A5";
-LOCATE COMP "TEST_LINE_1" SITE "A6";
-LOCATE COMP "TEST_LINE_2" SITE "G8";
-LOCATE COMP "TEST_LINE_3" SITE "F9";
-LOCATE COMP "TEST_LINE_4" SITE "D9";
-LOCATE COMP "TEST_LINE_5" SITE "D10";
-LOCATE COMP "TEST_LINE_6" SITE "F10";
-LOCATE COMP "TEST_LINE_7" SITE "E10";
-LOCATE COMP "TEST_LINE_8" SITE "A8";
-LOCATE COMP "TEST_LINE_9" SITE "B8";
-LOCATE COMP "TEST_LINE_10" SITE "G10";
-LOCATE COMP "TEST_LINE_11" SITE "G9";
-LOCATE COMP "TEST_LINE_12" SITE "C9";
-LOCATE COMP "TEST_LINE_13" SITE "C10";
-LOCATE COMP "TEST_LINE_14" SITE "H10";
-LOCATE COMP "TEST_LINE_15" SITE "H11";
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 SLEWRATE=FAST;
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ;
+REGION "MEDIA_UPLINK" "R102C95D" 13 25;
+LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
#################################################################
-# Connection to AddOn
+# Relax some of the timing constraints
#################################################################
-#All DQ groups from one bank are grouped.
-#All DQS are inserted in the DQ lines at position 6 and 7
-#DQ 6-9 are shifted to 8-11
-#Order per bank is kept, i.e. adjacent numbers have adjacent pins
-#all DQ blocks are 6+2+4=12 Pins wide, only DQUL3 and DQUR0 are 6+2+2=10.
-#even numbers are positive LVDS line, odd numbers are negative LVDS line
-#DQUL can be switched to 1.8V
-
-
-
-# nXyter 1
-
-LOCATE COMP "NX1_TESTPULSE_OUT" SITE "T7"; #DQLL1_8 #46
-LOCATE COMP "NX1_MAIN_CLK_OUT" SITE "AB1"; #DQLL2_2 #29
-LOCATE COMP "NX1_RESET_OUT" SITE "V6"; #DQLL2_8 #45
-#LOCATE COMP "NX1_DATA_CLK_IN" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69
-LOCATE COMP "NX1_DATA_CLK_IN" SITE "K4"; #DQSUL2_T #62 see DQUL3_8_OUTOFLANE
-
-LOCATE COMP "NX1_I2C_SM_RESET_OUT" SITE "P4"; #DQLL1_4 #34
-LOCATE COMP "NX1_I2C_REG_RESET_OUT" SITE "R3"; #DQLL1_5 #36
-LOCATE COMP "NX1_I2C_SDA_INOUT" SITE "R5"; #DQLL1_6 #42
-LOCATE COMP "NX1_I2C_SCL_INOUT" SITE "R6"; #DQLL1_7 #44
-
-LOCATE COMP "NX1_ADC_D_IN" SITE "B2"; #DQUL0_0 #74
-LOCATE COMP "NX1_ADC_A_IN" SITE "D4"; #DQUL0_2 #78
-LOCATE COMP "NX1_ADC_NX_IN" SITE "C3"; #DQUL0_4 #82
-LOCATE COMP "NX1_ADC_DCLK_IN" SITE "G5"; #DQSUL0_T #86
-LOCATE COMP "NX1_ADC_B_IN" SITE "E3"; #DQUL0_6 #90
-LOCATE COMP "NX1_ADC_FCLK_IN" SITE "H6"; #DQUL0_8 #94
-LOCATE COMP "NX1_ADC_SAMPLE_CLK_OUT" SITE "H5"; #DQUL1_6 #89
-
-LOCATE COMP "NX1_SPI_SDIO_INOUT" SITE "G2"; #DQUL1_0 #73
-LOCATE COMP "NX1_SPI_SCLK_OUT" SITE "F2"; #DQUL1_2 #77
-LOCATE COMP "NX1_SPI_CSB_OUT" SITE "C2"; #DQUL1_4 #81
-
-LOCATE COMP "NX1_TIMESTAMP_IN_0" SITE "K2"; #DQUL2_0 #50
-LOCATE COMP "NX1_TIMESTAMP_IN_1" SITE "J4"; #DQUL2_2 #54
-LOCATE COMP "NX1_TIMESTAMP_IN_2" SITE "D1"; #DQUL2_4 #58
-LOCATE COMP "NX1_TIMESTAMP_IN_3" SITE "E1"; #DQUL2_6 #66
-
-#LOCATE COMP "NX1_TIMESTAMP_IN_4" SITE "L5"; #DQUL2_8 #70
-LOCATE COMP "NX1_TIMESTAMP_IN_4" SITE "L2"; #DQUL3_6 #
-
-LOCATE COMP "NX1_TIMESTAMP_IN_5" SITE "H2"; #DQUL3_0 #49
-LOCATE COMP "NX1_TIMESTAMP_IN_6" SITE "K3"; #DQUL3_2 #53
-LOCATE COMP "NX1_TIMESTAMP_IN_7" SITE "H1"; #DQUL3_4 #57
-
-
-
-#DEFINE PORT GROUP "LVDS_group1" "NX1_TIMESTAMP*" ;
-#IOBUF GROUP "LVDS_group1" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_TIMESTAMP_IN_0" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_TIMESTAMP_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_TIMESTAMP_IN_2" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_TIMESTAMP_IN_3" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_TIMESTAMP_IN_4" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_TIMESTAMP_IN_5" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_TIMESTAMP_IN_6" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_TIMESTAMP_IN_7" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-
-#DEFINE PORT GROUP "LVDS_group2" "NX1_ADC*IN" ;
-#IOBUF GROUP "LVDS_group2" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_ADC_D_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_ADC_A_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_ADC_DCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_ADC_NX_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_ADC_B_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_ADC_FCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_ADC_SAMPLE_CLK_OUT" IO_TYPE=LVDS25;
-
-IOBUF PORT "NX1_DATA_CLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off;
-IOBUF PORT "NX1_TESTPULSE_OUT" IO_TYPE=LVDS25;
-IOBUF PORT "NX1_MAIN_CLK_OUT" IO_TYPE=LVDS25;
-IOBUF PORT "NX1_RESET_OUT" IO_TYPE=LVDS25;
-
-IOBUF PORT "NX1_I2C_SM_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN;
-IOBUF PORT "NX1_I2C_REG_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
-IOBUF PORT "NX1_I2C_SDA_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
-IOBUF PORT "NX1_I2C_SCL_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
-
-IOBUF PORT "NX1_SPI_SDIO_INOUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=4;
-IOBUF PORT "NX1_SPI_SCLK_OUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=4;
-IOBUF PORT "NX1_SPI_CSB_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4;
-
-# Nxyter Debug Lines Addon Board
-LOCATE COMP "NX1_DEBUG_LINE_1" SITE "R25"; #DQLR2_0 #170
-LOCATE COMP "NX1_DEBUG_LINE_3" SITE "R26"; #DQLR2_1 #172
-LOCATE COMP "NX1_DEBUG_LINE_5" SITE "T25"; #DQLR2_2 #174
-LOCATE COMP "NX1_DEBUG_LINE_7" SITE "T24"; #DQLR2_3 #176
-LOCATE COMP "NX1_DEBUG_LINE_9" SITE "T26"; #DQLR2_4 #178
-LOCATE COMP "NX1_DEBUG_LINE_11" SITE "U26"; #DQLR2_5 #180
-LOCATE COMP "NX1_DEBUG_LINE_13" SITE "U24"; #DQLR2_6 #186
-LOCATE COMP "NX1_DEBUG_LINE_15" SITE "V24"; #DQLR2_7 #188
-LOCATE COMP "NX1_DEBUG_LINE_14" SITE "W23"; #DQLR1_0 #169
-LOCATE COMP "NX1_DEBUG_LINE_12" SITE "W22"; #DQLR1_1 #171
-LOCATE COMP "NX1_DEBUG_LINE_10" SITE "AA25"; #DQLR1_2 #173
-LOCATE COMP "NX1_DEBUG_LINE_8" SITE "Y24"; #DQLR1_3 #175
-LOCATE COMP "NX1_DEBUG_LINE_6" SITE "AA26"; #DQLR1_4 #177
-LOCATE COMP "NX1_DEBUG_LINE_4" SITE "AB26"; #DQLR1_5 #179
-LOCATE COMP "NX1_DEBUG_LINE_2" SITE "AA24"; #DQLR1_6 #185
-LOCATE COMP "NX1_DEBUG_LINE_0" SITE "AA23"; #DQLR1_7 #187
-
-DEFINE PORT GROUP "NX1_DEBUG_LINE_group" "NX1_DEBUG_LINE_*" ;
-IOBUF GROUP "NX1_DEBUG_LINE_group" IO_TYPE=LVCMOS25 SLEWRATE=FAST;
-#################################################################
-# Additional Lines to AddOn
-#################################################################
+#SPI Interface
+REGION "REGION_SPI" "R9C108D" 20 20 DEVSIZE;
+LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
-#all lines are input only
-#line 4/5 go to PLL input
-#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194
-#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196
-#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198
-#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200
+#################################################
+# Muelleimer:
+# #LOCATE COMP "pll_adc_clk_1/PLLInst_0" SITE "PLL_R43C5" ;
+#
+#################################################
+MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 50 ns;
-#################################################################
-# Flash ROM and Reboot
-#################################################################
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reset_nx_main_clk_in_ff*" 30 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/trigger_busy_ff*" 30 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/fast_clear_ff*" 30 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_delay*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_length*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_enable*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/calibration_trigger_o*" 50 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/timestamp_calib_trigger_c*" 20 ns;
-LOCATE COMP "FLASH_CLK" SITE "B12";
-LOCATE COMP "FLASH_CS" SITE "E11";
-LOCATE COMP "FLASH_DIN" SITE "E12";
-LOCATE COMP "FLASH_DOUT" SITE "A12";
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_generator_*/internal_trigger_o*" 100 ns;
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/reset_nx_main_clk_in_ff*" 30 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_reset_ff*" 10 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_hold_o_*" 30 ns;
-LOCATE COMP "PROGRAMN" SITE "B11";
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_nx_timestamp_clk_in_ff*" 30 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/merge_handler_reset_i*" 30 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_reset_handler_cnx_ff*" 30 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_handler_start_r*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/johnson_counter_sync_r*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_delay_s*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_finedelb_r*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_dphase_r*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sampling_clk_reset*" 100 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_dt_error_ctr_r*" 100 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/timestamp_dt_error_ctr_*" 100 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/merge_error_ctr_r*" 100 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_sclk_ok_f*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type_r*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_reset_o*" 100 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_synced_rr*" 100 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type_f*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_mode_r_*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/cts_trigger_delay_*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_offset_*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_width_*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_time_max_*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/fpga_timestamp_offset_*" 100 ns;
+
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_event_buffer_*/fifo_almost_full_thr_*" 100 ns;
-#################################################################
-# Misc
-#################################################################
-LOCATE COMP "TEMPSENS" SITE "A13";
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#coding of FPGA number
-LOCATE COMP "CODE_LINE_1" SITE "AA20";
-LOCATE COMP "CODE_LINE_0" SITE "Y21";
-IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/debug_multiplexer_*/port_select_*" 500 ns;
-#terminated differential pair to pads
-#LOCATE COMP "SUPPL" SITE "C14";
-#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_adc_dt_error_ctr_*" 100 ns;
+MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_timestamp_dt_error_ctr_*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_error_status_i_*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/adc_ad9228_data_handler*/adc_locked_o*" 100 ns;
+
+MULTICYCLE TO GROUP "TEST_LINE_group" 500.000000 ns ;
+MULTICYCLE TO GROUP "NX1_DEBUG_LINE_group" 500.000000 ns ;
+MAXDELAY TO GROUP "TEST_LINE_group" 500.000000 ns ;
+MAXDELAY TO GROUP "NX1_DEBUG_LINE_group" 500.000000 ns ;
#################################################################
-# LED
+# Constraints for nxyter inputs
#################################################################
-LOCATE COMP "LED_GREEN" SITE "F12";
-LOCATE COMP "LED_ORANGE" SITE "G13";
-LOCATE COMP "LED_RED" SITE "A15";
-LOCATE COMP "LED_YELLOW" SITE "A16";
-DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12;
+
+# look at .par and .twr.setup file for clocks
+# IN .mrp you find the semantic errors
+
+PROHIBIT PRIMARY NET "NX1_DATA_CLK_IN_c";
+PROHIBIT SECONDARY NET "NX1_DATA_CLK_IN_c";
+
+DEFINE PORT GROUP "NX1_IN" "NX1_TIMESTAMP_*";
+INPUT_SETUP GROUP "NX1_IN" 1.5 ns HOLD 1.5 ns CLKPORT="NX1_DATA_CLK_IN";
#add_file options
-add_file -vhdl -lib work "version.vhd"
+add_file -vhdl -lib work "workdir/version.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
add_file -vhdl -lib "work" "../base/trb3_components.vhd"
add_file -vhdl -lib "work" "source/adc_spi_sendbyte.vhd"
add_file -vhdl -lib "work" "source/adc_spi_readbyte.vhd"
add_file -vhdl -lib "work" "source/adc_ad9228.vhd"
-add_file -vhdl -lib "work" "source/adc_ad9228_data_handler.vhd"
+#add_file -vhdl -lib "work" "source/adc_ad9228_data_handler.vhd"
add_file -vhdl -lib "work" "source/nx_fpga_timestamp.vhd"
add_file -vhdl -lib "work" "source/nx_trigger_generator.vhd"
+++ /dev/null
-#######################################################################
-
-
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-
-#################################################################
-# Basic Settings
-#################################################################
-
-# nXyter FEB Clock Setup:
-#
-# CLK_PCLK_RIGHT : real Oszillator 200MHz
-# CLK_PCLK_RIGHT --> PLL#0 --> clk_100_i -----> Main Clock all entities
-#
-# CLK_PCLK_RIGHT --> nx_main_clk 1+2
-# (250 MHz) -----> nXyter Main Clock 1+2
-# |
-# |----> FPGA Timestamp Entity 1+2
-#
-# nx_main_clk 1+2 --> nXyter Data Clk
-# (1/2 = 125MHz) -----> FPGA Data Receiver
-# |
-# |----> Johnson 1/4 --> ADC SCLK
-#
-# ADC_DATA_CLK --> ADC Data Clk -----> FPGA ADC Handler
-# DDR (187.5 MHz)
-
-
-# Speed for the configuration Flash access
-SYSCONFIG MCCLK_FREQ = 20;
-
-FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-FREQUENCY PORT NX1_DATA_CLK_IN 125 MHz;
-FREQUENCY PORT NX1_ADC_DCLK_IN 187.5 MHz;
-FREQUENCY NET "nXyter_FEE_board_0/nx_data_receiver_1/DDR_DATA_CLK" 93.750000 MHz;
-
-USE PRIMARY NET "CLK_PCLK_RIGHT_c";
-USE PRIMARY NET "clk_100_i";
-USE PRIMARY NET "nx_main_clk";
-USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/DDR_DATA_CLK";
-
-#################################################################
-# Reset Nets
-#################################################################
-
-# GSR_NET NET "GSR_N";
-
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ;
-REGION "MEDIA_UPLINK" "R102C95D" 13 25;
-LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
-
-#################################################################
-# Relax some of the timing constraints
-#################################################################
-
-#SPI Interface
-REGION "REGION_SPI" "R9C108D" 20 20 DEVSIZE;
-LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
-
-#################################################
-# Muelleimer:
-# #LOCATE COMP "pll_adc_clk_1/PLLInst_0" SITE "PLL_R43C5" ;
-#
-#################################################
-
-
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 50 ns;
-
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reset_nx_main_clk_in_ff*" 30 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/trigger_busy_ff*" 30 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/fast_clear_ff*" 30 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_delay*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_length*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_enable*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/calibration_trigger_o*" 50 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/timestamp_calib_trigger_c*" 20 ns;
-
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_generator_*/internal_trigger_o*" 100 ns;
-
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/reset_nx_main_clk_in_ff*" 30 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_reset_ff*" 10 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_hold_o_*" 30 ns;
-
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_nx_timestamp_clk_in_ff*" 30 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/merge_handler_reset_i*" 30 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_reset_handler_cnx_ff*" 30 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_handler_start_r*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/johnson_counter_sync_r*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_delay_s*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_finedelb_r*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_dphase_r*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sampling_clk_reset*" 100 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_dt_error_ctr_r*" 100 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/timestamp_dt_error_ctr_*" 100 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/merge_error_ctr_r*" 100 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_sclk_ok_f*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type_r*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_reset_o*" 100 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_synced_rr*" 100 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type_f*" 100 ns;
-
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_mode_r_*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/cts_trigger_delay_*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_offset_*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_width_*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_time_max_*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/fpga_timestamp_offset_*" 100 ns;
-
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_event_buffer_*/fifo_almost_full_thr_*" 100 ns;
-
-
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/debug_multiplexer_*/port_select_*" 500 ns;
-
-
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_adc_dt_error_ctr_*" 100 ns;
-MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_timestamp_dt_error_ctr_*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_error_status_i_*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/adc_ad9228_data_handler*/adc_locked_o*" 100 ns;
-
-MULTICYCLE TO GROUP "TEST_LINE_group" 500.000000 ns ;
-MULTICYCLE TO GROUP "NX1_DEBUG_LINE_group" 500.000000 ns ;
-MAXDELAY TO GROUP "TEST_LINE_group" 500.000000 ns ;
-MAXDELAY TO GROUP "NX1_DEBUG_LINE_group" 500.000000 ns ;
-
-#################################################################
-# Constraints for nxyter inputs
-#################################################################
-
-# look at .par and .twr.setup file for clocks
-# IN .mrp you find the semantic errors
-
-PROHIBIT PRIMARY NET "NX1_DATA_CLK_IN_c";
-PROHIBIT SECONDARY NET "NX1_DATA_CLK_IN_c";
-
-DEFINE PORT GROUP "NX1_IN" "NX1_TIMESTAMP_*";
-INPUT_SETUP GROUP "NX1_IN" 1.5 ns HOLD 1.5 ns CLKPORT="NX1_DATA_CLK_IN";
jspc29 / trb3.git / commitdiff