--- /dev/null
+
+# implementation: "workdir"
+impl -add workdir -type fpga
+
+# device options
+set_option -technology ECP5UM
+set_option -part LFE5UM_85F
+set_option -package BG756C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -top_module "trb5sc_mimosis"
+set_option -resource_sharing false
+set_option -vhdl2008 true
+
+# map options
+set_option -frequency 120
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 1
+set_option -pipe 1
+set_option -forcegsr false
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -compiler_compatible true
+set_option -multi_file_compilation_unit 1
+
+set_option -max_parallel_jobs 3
+#set_option -automatic_compile_point 1
+#set_option -continue_on_error 1
+set_option -resolve_multiple_driver 1
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+# set result format/file last
+project -result_format "edif"
+project -result_file "workdir/trb5sc_mimosis.edf"
+set_option log_file "workdir/trb5sc_project.srf"
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
+
+####################
+
+add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd"
+
+#Packages
+add_file -vhdl -lib work "workdir/version.vhd"
+add_file -vhdl -lib work "config.vhd"
+add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd"
+
+#Basic Infrastructure
+add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd"
+add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd"
+
+
+#Fifos
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.vhd"
+
+
+#Flash & Reload, Tools
+add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/common_i2c.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd"
+
+#SlowControl files
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
+
+#Media interface
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd"
+
+
+#########################################
+#channel 0, backplane
+#add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd"
+#add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v"
+
+#channel 1, SFP
+#add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd"
+#add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v"
+##########################################
+
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd"
+add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v"
+
+
+#TrbNet Endpoint
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd"
+add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd"
+
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd"
+
+add_file -vhdl -lib work "./cores/mimosis_inp.vhd"
+add_file -vhdl -lib work "./cores/testout.vhd"
+add_file -vhdl -lib work "./code/MimosisInput.vhd"
+add_file -vhdl -lib work "./code/InputStage.vhd"
+add_file -vhdl -lib work "./code/WordAlign.vhd"
+add_file -vhdl -lib work "./cores/pll_200_160/pll_200_160.vhd"
+
+
+
+#GbE
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_wrapper.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_med_interface_single.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd"
+add_file -verilog -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/serdes_gbe_softlogic.v"
+# Choose your SerDes location here
+#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch0/serdes_gbe.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch1/serdes_gbe.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch0/serdes_gbe.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch1/serdes_gbe.vhd"
+
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x72.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx16x8_mb2.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_65536x18x9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9_af_cnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd"
+
+
+
+
+
+
+
+
+
+add_file -vhdl -lib work "./trb5sc_mimosis.vhd"
+#add_file -fpga_constraint "./synplify.fdc"
+
+
+
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.version.all;\r
+use work.config.all;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+use work.trb3_components.all;\r
+use work.med_sync_define.all;\r
+\r
+entity trb5sc_mimosis is\r
+ port(\r
+ CLK_200 : in std_logic;\r
+ CLK_125 : in std_logic;\r
+ CLK_EXT : in std_logic;\r
+\r
+ TRIG_IN_BACKPL : in std_logic; --Reference Time\r
+ TRIG_IN_RJ45 : in std_logic; --Reference Time\r
+ IN_SELECT_EXT_CLOCK : in std_logic;\r
+\r
+ SPARE : out std_logic_vector(1 downto 0); -- trigger output 2+3\r
+ BACK_GPIO : inout std_logic_vector(3 downto 0); --0: Serdes out, 1: Serdes in, 2,3: trigger output 0+1\r
+\r
+ SFP_TX_DIS : out std_logic;\r
+ SFP_LOS : in std_logic;\r
+ SFP_MOD_0 : in std_logic;\r
+\r
+ --AddOn\r
+ --FE_GPIO : inout std_logic_vector(11 downto 0);\r
+ --FE_CLK : out std_logic_vector( 2 downto 1);\r
+ --FE_DIFF : inout std_logic_vector(63 downto 0);\r
+ --INP : inout std_logic_vector(63 downto 0);\r
+ --LED_ADDON : out std_logic_vector(5 downto 0);\r
+ LED_ADDON_SFP_ORANGE : out std_logic_vector(1 downto 0);\r
+ LED_ADDON_SFP_GREEN : out std_logic_vector(1 downto 0);\r
+ LED_ADDON_RJ : out std_logic_vector(1 downto 0);\r
+ SFP_ADDON_TX_DIS : out std_logic_vector(1 downto 0);\r
+ SFP_ADDON_LOS : in std_logic_vector(1 downto 0);\r
+\r
+ RJ : inout std_logic_vector(3 downto 0);\r
+ H1 : inout std_logic_vector(4 downto 0);\r
+ H2 : inout std_logic_vector(4 downto 0);\r
+ H3 : inout std_logic_vector(4 downto 0);\r
+ H4 : inout std_logic_vector(4 downto 0);\r
+ H5 : inout std_logic_vector(3 downto 0);\r
+ H6 : inout std_logic_vector(4 downto 0);\r
+ H7 : inout std_logic_vector(4 downto 0);\r
+\r
+ PIN : out std_logic_vector(8 downto 1);\r
+\r
+ MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic;\r
+\r
+ --ADC\r
+ ADC_SCLK : out std_logic;\r
+ ADC_NCS : out std_logic;\r
+ ADC_MOSI : out std_logic;\r
+ ADC_MISO : in std_logic;\r
+ --Flash, Reload\r
+ FLASH_SCLK : out std_logic;\r
+ FLASH_NCS : out std_logic;\r
+ FLASH_MOSI : out std_logic;\r
+ FLASH_MISO : in std_logic;\r
+ FLASH_HOLD : out std_logic;\r
+ FLASH_WP : out std_logic;\r
+ PROGRAMN : out std_logic;\r
+ --I2C\r
+ I2C_SDA : inout std_logic;\r
+ I2C_SCL : inout std_logic;\r
+ TMP_ALERT : in std_logic;\r
+\r
+ --GBTSCA\r
+ SCA_RX : in std_logic_vector(1 downto 0);\r
+ SCA_TX : out std_logic_vector(1 downto 0);\r
+ SCA_CLK : out std_logic_vector(1 downto 0);\r
+\r
+ --LED\r
+ LED : out std_logic_vector(8 downto 1);\r
+ LED_SFP_YELLOW : out std_logic;\r
+ LED_SFP_GREEN : out std_logic;\r
+ LED_SFP_RED : out std_logic;\r
+ LED_RJ_GREEN : out std_logic_vector(1 downto 0);\r
+ LED_RJ_RED : out std_logic_vector(1 downto 0);\r
+ LED_EXT_CLOCK : out std_logic;\r
+\r
+ --Other Connectors\r
+ TEST : inout std_logic_vector(14 downto 1); --on v1 only\r
+ --COMMON_SDA, COMMON_SCL : inout std_logic\r
+ HDR_IO : inout std_logic_vector(15 downto 0) --23..16 on v2 only\r
+ );\r
+\r
+ attribute syn_useioff : boolean;\r
+ attribute syn_useioff of FLASH_NCS : signal is true;\r
+ attribute syn_useioff of FLASH_SCLK : signal is true;\r
+ attribute syn_useioff of FLASH_MOSI : signal is true;\r
+ attribute syn_useioff of FLASH_MISO : signal is true;\r
+\r
+end entity;\r
+\r
+\r
+architecture arch of trb5sc_mimosis is\r
+\r
+ attribute syn_keep : boolean;\r
+ attribute syn_preserve : boolean;\r
+\r
+ signal clk_sys, clk_full, clk_full_osc, clk_160, clk_320, clk_40, clk_80 : std_logic;\r
+ signal GSR_N : std_logic;\r
+ signal reset_i : std_logic;\r
+ signal clear_i : std_logic;\r
+ signal trigger_in_i : std_logic;\r
+\r
+ attribute syn_keep of GSR_N : signal is true;\r
+ attribute syn_preserve of GSR_N : signal is true;\r
+\r
+ signal debug_clock_reset : std_logic_vector(31 downto 0);\r
+ signal external_clock_lock : std_logic := '0';\r
+ signal debug_tools : std_logic_vector(31 downto 0);\r
+\r
+ --Media Interface\r
+ signal med2int : med2int_array_t(0 to 0);\r
+ signal int2med : int2med_array_t(0 to 0);\r
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);\r
+ signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic;\r
+\r
+\r
+ signal readout_rx : READOUT_RX;\r
+ signal readout_tx : readout_tx_array_t(0 to 0);\r
+\r
+ signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in, busmimosis_tx, busi2c_tx, busgbtcore_tx, busgbeip_tx, busgbereg_tx, busfwd_tx : CTRLBUS_TX;\r
+ signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busmimosis_rx, busi2c_rx, busgbtcore_rx, busgbeip_rx, busgbereg_rx, busfwd_rx : CTRLBUS_RX;\r
+\r
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
+\r
+ signal sed_error_i : std_logic;\r
+ signal clock_select : std_logic;\r
+ signal bus_master_active : std_logic;\r
+ signal flash_ncs_i : std_logic;\r
+\r
+ signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);\r
+ signal header_io_i : std_logic_vector(10 downto 1);\r
+ signal timer : TIMERS;\r
+ signal add_reg : std_logic_vector(31 downto 0);\r
+ alias led_off : std_logic is add_reg(0);\r
+\r
+ signal out_data : std_logic_vector(15 downto 0);\r
+ signal out_i : std_logic_vector( 7 downto 0);\r
+ signal inp_i : std_logic_vector( 7 downto 0);\r
+ signal gbe_status : std_logic_vector(15 downto 0);\r
+\r
+ signal i2c_reg_0, i2c_reg_1 : std_logic_vector(31 downto 0);\r
+ signal i2c_reg_2 : std_logic_vector(31 downto 0);\r
+ signal i2c_reg_4, i2c_reg_5 : std_logic_vector(31 downto 0);\r
+ signal mimosis_scl_drv, mimosis_sda_drv : std_logic;\r
+ signal i2c_go_100, i2c_go : std_logic;\r
+ signal i2c_reg_5_40 : std_logic_vector(31 downto 0);\r
+ signal counter : unsigned(23 downto 0);\r
+\r
+ --signal fwd_dst_mac : std_logic_vector(47 downto 0);\r
+ --signal fwd_dst_ip : std_logic_vector(31 downto 0);\r
+ --signal fwd_dst_port : std_logic_vector(15 downto 0);\r
+ --signal fwd_data : std_logic_vector(7 downto 0);\r
+ --signal fwd_datavalid : std_logic;\r
+ --signal fwd_sop : std_logic;\r
+ --signal fwd_eop : std_logic;\r
+ --signal fwd_ready : std_logic;\r
+ --signal fwd_full : std_logic;\r
+ --signal fwd_length : std_logic_vector(15 downto 0);\r
+ --signal fwd_do_send : std_logic;\r
+\r
+begin\r
+\r
+\r
+ trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK);\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Clock & Reset Handling\r
+---------------------------------------------------------------------------\r
+ THE_CLOCK_RESET : entity work.clock_reset_handler\r
+ port map(\r
+ CLOCK_IN => CLK_200,\r
+ RESET_FROM_NET => med2int(0).stat_op(13),\r
+ SEND_RESET_IN => med2int(0).stat_op(15),\r
+\r
+ BUS_RX => bustc_rx,\r
+ BUS_TX => bustc_tx,\r
+\r
+ RESET_OUT => reset_i,\r
+ CLEAR_OUT => clear_i,\r
+ GSR_OUT => GSR_N,\r
+\r
+ REF_CLK_OUT => clk_full,\r
+ SYS_CLK_OUT => clk_sys,\r
+ RAW_CLK_OUT => clk_full_osc,\r
+\r
+ DEBUG_OUT => debug_clock_reset\r
+ );\r
+\r
+ THE_160_PLL : entity work.pll_200_160\r
+ port map(\r
+ CLKI => clk_full_osc,\r
+ CLKOP => clk_160,\r
+ CLKOS => clk_320,\r
+ CLKOS2=> clk_40\r
+ CLKOS3=> clk_80\r
+ );\r
+\r
+ H5(3) <= clk_320;\r
+ RJ(0) <= clk_40;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- TrbNet Uplink\r
+---------------------------------------------------------------------------\r
+\r
+ THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync\r
+ generic map(\r
+ SERDES_NUM => SERDES_NUM,\r
+ USE_NEW_ECP5_RESET => 0,\r
+ IS_SYNC_SLAVE => c_YES\r
+ )\r
+ port map(\r
+ CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full,\r
+ CLK_INTERNAL_FULL => clk_full_osc,\r
+ SYSCLK => clk_sys,\r
+ RESET => reset_i,\r
+ CLEAR => clear_i,\r
+ --Internal Connection\r
+ MEDIA_MED2INT => med2int(0),\r
+ MEDIA_INT2MED => int2med(0),\r
+\r
+ --Sync operation\r
+ RX_DLM => open,\r
+ RX_DLM_WORD => open,\r
+ TX_DLM => open,\r
+ TX_DLM_WORD => open,\r
+\r
+ --SFP Connection\r
+ SD_PRSNT_N_IN => sfp_prsnt_i,\r
+ SD_LOS_IN => sfp_los_i,\r
+ SD_TXDIS_OUT => sfp_txdis_i,\r
+ --Control Interface\r
+ BUS_RX => bussci_rx,\r
+ BUS_TX => bussci_tx,\r
+ -- Status and control port\r
+ STAT_DEBUG => med_stat_debug(63 downto 0),\r
+ CTRL_DEBUG => open\r
+ );\r
+\r
+ gen_sfp_con : if SERDES_NUM = 1 generate\r
+ sfp_los_i <= SFP_LOS;\r
+ sfp_prsnt_i <= SFP_MOD_0;\r
+ SFP_TX_DIS <= sfp_txdis_i;\r
+ end generate;\r
+ gen_bpl_con : if SERDES_NUM = 0 generate\r
+ sfp_los_i <= BACK_GPIO(1);\r
+ sfp_prsnt_i <= BACK_GPIO(1);\r
+ BACK_GPIO(0) <= sfp_txdis_i;\r
+ end generate;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Endpoint\r
+---------------------------------------------------------------------------\r
+ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record\r
+ generic map (\r
+ ADDRESS_MASK => x"FFFF",\r
+ BROADCAST_BITMASK => BROADCAST_BITMASK,\r
+ REGIO_INIT_ENDPOINT_ID => x"0001",\r
+ REGIO_USE_1WIRE_INTERFACE => c_I2C,\r
+ TIMING_TRIGGER_RAW => c_YES,\r
+ --Configure data handler\r
+ DATA_INTERFACE_NUMBER => 1,\r
+ DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE,\r
+ DATA_BUFFER_WIDTH => 32,\r
+ DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE,\r
+ TRG_RELEASE_AFTER_DATA => c_YES,\r
+ HEADER_BUFFER_DEPTH => 9,\r
+ HEADER_BUFFER_FULL_THRESH => 2**9-16,\r
+ USE_GBE => USE_GBE\r
+ )\r
+\r
+ port map(\r
+ -- Misc\r
+ CLK => clk_sys,\r
+ RESET => reset_i,\r
+ CLK_125 => CLK_125,\r
+ CLEAR_N => GSR_N,\r
+\r
+ -- Media direction port\r
+ MEDIA_MED2INT => med2int(0),\r
+ MEDIA_INT2MED => int2med(0),\r
+\r
+ --Timing trigger in\r
+ TRG_TIMING_TRG_RECEIVED_IN => trigger_in_i,\r
+\r
+ READOUT_RX => readout_rx,\r
+ READOUT_TX => readout_tx,\r
+\r
+ --Slow Control Port\r
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00\r
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20\r
+ BUS_RX => ctrlbus_rx,\r
+ BUS_TX => ctrlbus_tx,\r
+ BUS_MASTER_IN => bus_master_in,\r
+ BUS_MASTER_OUT => bus_master_out,\r
+ BUS_MASTER_ACTIVE => bus_master_active,\r
+\r
+ ONEWIRE_INOUT => open,\r
+ I2C_SCL => I2C_SCL,\r
+ I2C_SDA => I2C_SDA,\r
+ --Timing registers\r
+ TIMERS_OUT => timer,\r
+ STATUS_GBE_OUT=> gbe_status\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- Bus Handler\r
+---------------------------------------------------------------------------\r
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record\r
+ generic map(\r
+ PORT_NUMBER => 5,\r
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"de00", 5 => x"8100", 6 => x"8300", 7 => x"8400", others => x"0000"),\r
+ PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 5, 5 => 8, 6 => 8, 7 => 8, others => 0),\r
+ PORT_MASK_ENABLE => 1\r
+ )\r
+ port map(\r
+ CLK => clk_sys,\r
+ RESET => reset_i,\r
+\r
+ REGIO_RX => ctrlbus_rx,\r
+ REGIO_TX => ctrlbus_tx,\r
+\r
+ BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED\r
+ BUS_RX(1) => bussci_rx, --SCI Serdes\r
+ BUS_RX(2) => bustc_rx, --Clock switch\r
+ BUS_RX(3) => busmimosis_rx,\r
+ BUS_RX(4) => busgbtcore_rx,\r
+ -- BUS_RX(4) => busi2c_rx,\r
+ -- BUS_RX(5) => busgbeip_rx,\r
+ -- BUS_RX(6) => busgbereg_rx,\r
+ -- BUS_RX(7) => busfwd_rx,\r
+ BUS_TX(0) => bustools_tx,\r
+ BUS_TX(1) => bussci_tx,\r
+ BUS_TX(2) => bustc_tx,\r
+ BUS_TX(3) => busmimosis_tx,\r
+ BUS_TX(4) => busgbtcore_tx,\r
+ -- BUS_TX(4) => busi2c_tx,\r
+ -- BUS_TX(5) => busgbeip_tx,\r
+ -- BUS_TX(6) => busgbereg_tx,\r
+ -- BUS_TX(7) => busfwd_tx,\r
+ STAT_DEBUG => open\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- Control Tools\r
+---------------------------------------------------------------------------\r
+ THE_TOOLS : entity work.trb3sc_tools\r
+ generic map(\r
+ ADC_CMD_1 => x"2c3cb",\r
+ ADC_CMD_2 => x"1d5cb",\r
+ ADC_CMD_3 => x"1e3cb",\r
+ ADC_CMD_4 => x"2f5cb",\r
+ ADC_CMD_T => x"1F393"\r
+ )\r
+ port map(\r
+ CLK => clk_sys,\r
+ RESET => reset_i,\r
+\r
+ --Flash & Reload\r
+ FLASH_CS => flash_ncs_i,\r
+ FLASH_CLK => FLASH_SCLK,\r
+ FLASH_IN => FLASH_MISO,\r
+ FLASH_OUT => FLASH_MOSI,\r
+ PROGRAMN => PROGRAMN,\r
+ REBOOT_IN => common_ctrl_reg(15),\r
+ --SPI\r
+ SPI_CS_OUT => spi_cs,\r
+ SPI_MOSI_OUT => spi_mosi,\r
+ SPI_MISO_IN => spi_miso,\r
+ SPI_CLK_OUT => spi_clk,\r
+ --Header\r
+ --HEADER_IO => open,\r
+ HEADER_IO(7) => HDR_IO(6),\r
+ HEADER_IO(8) => HDR_IO(7),\r
+ ADDITIONAL_REG => add_reg,\r
+ --ADC\r
+ ADC_CS => ADC_NCS,\r
+ ADC_MOSI => ADC_MOSI,\r
+ ADC_MISO => ADC_MISO,\r
+ ADC_CLK => ADC_SCLK,\r
+ --Trigger & Monitor\r
+ MONITOR_INPUTS => (others => '0'),\r
+ TRIG_GEN_INPUTS => (others => '0'),\r
+ TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2),\r
+ TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0),\r
+ --SED\r
+ SED_ERROR_OUT => sed_error_i,\r
+ --Slowcontrol\r
+ BUS_RX => bustools_rx,\r
+ BUS_TX => bustools_tx,\r
+ --Control master for default settings\r
+ BUS_MASTER_IN => bus_master_in,\r
+ BUS_MASTER_OUT => bus_master_out,\r
+ BUS_MASTER_ACTIVE => bus_master_active,\r
+ DEBUG_OUT => debug_tools\r
+ );\r
+\r
+--counter <= counter + '1' when rising_edge(clk_sys);\r
+--HDR_IO <= std_logic_vector(counter(15 downto 0));\r
+--LED <= std_logic_vector(counter(23 downto 16));\r
+\r
+ --COMMON_SDA(6) <= '0' when (add_reg(31) = '1') else 'Z';\r
+ --COMMON_SCL(7) <= '0' when (add_reg(30) = '1') else 'Z';\r
+\r
+ FLASH_HOLD <= '1';\r
+ FLASH_WP <= '1';\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- GBT-SCA\r
+---------------------------------------------------------------------------\r
+ THE_GBT_CORE : entity work.gbt_core\r
+ port map(\r
+ CLK_sys => clk_sys,\r
+ CLK => clk_40,\r
+\r
+ RESET => reset_i,\r
+\r
+ BUS_RX => busgbtcore_rx,\r
+ BUS_TX => busgbtcore_tx,\r
+\r
+ ELINK_RX => 0,\r
+ ELINK_TX => open\r
+ );\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- LED\r
+---------------------------------------------------------------------------\r
+\r
+ LED_SFP_GREEN <= not med2int(0).stat_op(9);\r
+ LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11));\r
+ LED_SFP_YELLOW <= not med2int(0).stat_op(8);\r
+ LED <= x"FF";\r
+ LED_RJ_GREEN(1)<= not external_clock_lock or led_off; --on if external clock used\r
+ LED_RJ_GREEN(0)<= '1' when SERDES_NUM = 0 or led_off = '1' else '0'; --on if SFP is used (next to SFP)\r
+ LED_RJ_RED(1) <= external_clock_lock or led_off; --on if internal clock used\r
+ LED_RJ_RED(0) <= '1' when SERDES_NUM = 1 or led_off = '1' else '0'; --on if backplane is used (next to SFP)\r
+ LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off; --on if trigger/clock from RJ45 is used\r
+\r
+ TEST(13 downto 1) <= (others => '0');\r
+ TEST(14) <= flash_ncs_i; --for v1 boards\r
+\r
+ FLASH_NCS <= flash_ncs_i;\r
+\r
+ LED_ADDON_RJ <= "00";\r
+ LED_ADDON_SFP_GREEN(0) <= (gbe_status(0) and gbe_status(1) and gbe_status(2));\r
+ LED_ADDON_SFP_GREEN(1) <= '0';\r
+ LED_ADDON_SFP_ORANGE(0) <= (gbe_status(3) or gbe_status(4));\r
+ LED_ADDON_SFP_ORANGE(1) <= '0';\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- GBT Core\r
+---------------------------------------------------------------------------\r
+ THE_GBT_CORE : entity work.gbt_core\r
+ port map(\r
+ CLK_SYS => clk_sys,\r
+ CLK => clk_80,\r
+ RESET => reset_i,\r
+\r
+ BUS_RX => busgbtcore_rx,\r
+ BUS_TX => busgbtcore_tx,\r
+\r
+ ELINK_RX => H3(0),\r
+ ELINK_TX => H3(2)\r
+ );\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Input stage\r
+---------------------------------------------------------------------------\r
+ THE_MIMOSIS : entity work.MimosisInput\r
+ port map(\r
+ CLK => clk_160,\r
+ CLK_SYS => clk_sys,\r
+ RESET => reset_i,\r
+\r
+ INPUT => inp_i,\r
+\r
+ BUSRDO_RX => readout_rx,\r
+ BUSRDO_TX => readout_tx(0),\r
+\r
+ BUS_RX => busmimosis_rx,\r
+ BUS_TX => busmimosis_tx\r
+ );\r
+\r
+-- inp_i <= H2(3 downto 0) & H1(3 downto 0);\r
+ inp_i <= H2(3) & H1(3) & H2(2) & H1(2) & H2(1) & H1(1) & H2(0) & H1(0);\r
+-------------------------------------------------------------------------------\r
+-- No trigger/data endpoint included\r
+-------------------------------------------------------------------------------\r
+-- readout_tx(0).data_finished <= '1';\r
+-- readout_tx(0).data_write <= '0';\r
+-- readout_tx(0).busy_release <= '1';\r
+\r
+ SFP_ADDON_TX_DIS <= (others => '0');\r
+end architecture;\r
jspc29 / trb5sc.git / commitdiff