some additional debugging

diff --git a/special/trb_net_bridge_pcie_endpoint_hub.vhd b/special/trb_net_bridge_pcie_endpoint_hub.vhd
index 2e1116f8652b72dcaee6b51b3c026d7815c74b5c..6f63adecedb47e8f827fad6191a9262de62feae3 100644 (file)
--- a/special/trb_net_bridge_pcie_endpoint_hub.vhd
+++ b/special/trb_net_bridge_pcie_endpoint_hub.vhd
@@ -103,7 +103,7 @@ end entity;
 
 architecture trb_net_bridge_pcie_endpoint_hub_arch of trb_net_bridge_pcie_endpoint_hub is
 
-  signal reset_i : std_logic;
+  signal reset_trbnet_i : std_logic;
   signal clk_en  : std_logic;
 
   signal buf_med_ctrl_op : std_logic_vector(NUM_LINKS*16-1 downto 0);
@@ -136,6 +136,7 @@ architecture trb_net_bridge_pcie_endpoint_hub_arch of trb_net_bridge_pcie_endpoi
   signal my_address              : std_logic_vector(15 downto 0);
   signal timer_ticks             : std_logic_vector(1 downto 0);
   signal hub_ctrl_debug          : std_logic_vector(31 downto 0);
+  signal hub_stat_debug          : std_logic_vector(31 downto 0);
 
   signal link_not_up             : std_logic;
   signal apl_stat                : std_logic_vector(31 downto 0);
@@ -228,6 +229,14 @@ architecture trb_net_bridge_pcie_endpoint_hub_arch of trb_net_bridge_pcie_endpoi
   signal df_empty            : std_logic_vector(1 downto 0);
   signal df_read             : std_logic_vector(1 downto 0);
 
+
+  signal debugfifo_write   : std_logic;
+  signal debugfifo_read    : std_logic;
+  signal debugfifo_empty   : std_logic;
+  signal debugfifo_full    : std_logic;
+  signal debugfifo_out     : std_logic_vector(31 downto 0);          
+  signal debugfifo_in      : std_logic_vector(31 downto 0);          
+  
 begin
 
   APL_MY_ADDRESS_IN <= x"FCCC";
@@ -240,11 +249,12 @@ begin
       COMPILE_VERSION            => (others => '0'),
       HARDWARE_VERSION           => x"73000000",
       HUB_CTRL_BROADCAST_BITMASK => x"FF",
+      HUB_USED_CHANNELS          => (c_NO,c_NO,c_NO,c_YES),
       CLOCK_FREQUENCY            => 150,
       USE_ONEWIRE                => c_NO,
       BROADCAST_SPECIAL_ADDR     => x"FF",
       MII_NUMBER                 => NUM_LINKS,
-      MII_IS_UPLINK              => (NUM_LINKS => c_YES, NUM_LINKS+1 => c_YES, 0 => c_YES, others => c_NO), --NUM_LINKS => c_YES, NUM_LINKS+1 => c_YES,
+      MII_IS_UPLINK              => (others => c_YES), --NUM_LINKS => c_YES, NUM_LINKS+1 => c_YES,
       MII_IS_DOWNLINK            => (others => c_YES), --NUM_LINKS => c_YES, NUM_LINKS+1 => c_YES,
       MII_IS_UPLINK_ONLY         => (others => c_NO), --NUM_LINKS => c_YES,
       INIT_UNIQUE_ID             => x"1111222233334444",
@@ -254,7 +264,7 @@ begin
       )
     port map (
       CLK    => CLK,
-      RESET  => RESET_TRBNET,
+      RESET  => reset_trbnet_i,
       CLK_EN => '1',
 
       --Media interfacces
@@ -305,7 +315,7 @@ begin
       COMMON_STAT_REGS   => common_stat,
       MPLEX_CTRL         => (others => '0'),
       CTRL_DEBUG         => hub_ctrl_debug,
-      STAT_DEBUG         => open
+      STAT_DEBUG         => hub_stat_debug
       );
 
   hub_ctrl_debug(2 downto 0)  <= not ERROR_OK;
@@ -329,7 +339,7 @@ begin
       port map (
         --  Misc
         CLK    => CLK,
-        RESET  => RESET_TRBNET,
+        RESET  => reset_trbnet_i,
         CLK_EN => '1',
         -- APL Transmitter port
         APL_DATA_IN           => APL_DATA_IN(i*16+15 downto i*16),
@@ -463,10 +473,18 @@ begin
             bus_data_i <= status_dma_core(127 downto 96);
           when x"78" =>
             bus_data_i <= status_dma_core(159 downto 128);
+          when x"79" =>
+            bus_data_i <= buf_api_stat_fifo_to_int(2*32+31 downto 2*32);
+          when x"7a" =>
+            bus_data_i <= buf_api_stat_fifo_to_apl(2*32+31 downto 2*32);
+          when x"7b" =>
+            bus_data_i <= hub_stat_debug;
           when x"E0" =>
             bus_data_i <= df_data(31 downto 0);
           when x"E1" =>
             bus_data_i <= df_data(63 downto 32);
+          when x"EE" =>
+            bus_data_i <= debugfifo_out;
           when others         =>
             bus_data_i <= x"EE000000"; --"1000000000000000000" & CTRL(31 downto 19);
         end case;
@@ -526,7 +544,29 @@ begin
 
 df_read(0) <= '1' when BUS_ADDR_IN(15 downto 0) = x"0e00" and bus_read_i = '1' else '0';
 df_read(1) <= '1' when BUS_ADDR_IN(15 downto 0) = x"0e01" and bus_read_i = '1' else '0';
-    
+
+
+--------------------------------
+-- Debug bus communication
+--------------------------------
+
+debugfifo_read <= '1' when (bus_read_i='1' and BUS_ADDR_IN(15 downto 0) = x"0e0e") or debugfifo_full = '1' else '0';
+debugfifo_write <= '1' when (bus_read_i or bus_write_i) = '1' and BUS_ADDR_IN(11 downto 0) /= x"702" and BUS_ADDR_IN(11 downto 0) /= x"273" and BUS_ADDR_IN(11 downto 8) /= x"e" else '0';
+debugfifo_in    <= bus_write_i & BUS_ADDR_IN(10 downto 0) & BUS_WDAT_IN(19 downto 0);
+
+DEBUG_FIFO : fifo_32x512
+    port map(
+        Data  => debugfifo_in,
+        Clock => CLK,
+        WrEn  => debugfifo_write,
+        RdEn  => debugfifo_read, 
+        Reset => RESET, 
+        Q     => debugfifo_out,
+        Empty => debugfifo_empty,
+        Full  => debugfifo_full
+        );
+
+        
 --------------------------------
 -- connection to API
 --------------------------------
@@ -767,7 +807,9 @@ THE_DMA_CORE : dma_core
 
   SEND_RESET_OUT <= not send_reset_counter(10);
   MAKE_RESET_OUT <= '1' when and_all(std_logic_vector(send_reset_counter(9 downto 0))) = '1' or (BUS_ADDR_IN = x"00000011" and bus_write_i = '1') else '0';
-
+  reset_trbnet_i <= '1' when RESET_TRBNET = '1' or (BUS_ADDR_IN = x"00000012" and bus_write_i = '1') else '0';
+  
+  
   process(CLK)
     begin
       if rising_edge(CLK) then

diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd
index 5275859a157f091072a5cd5044c8b83133e1331e..11918d61a9a6e65cd721f7afb6caa8a0ec184357 100644 (file)
--- a/trb_net16_api_base.vhd
+++ b/trb_net16_api_base.vhd
@@ -1006,38 +1006,39 @@ INT_MASTER_DATAREADY_OUT  <= buf_INT_MASTER_DATAREADY_OUT;
 --Debugging & Status Signals
 ---------------------------------------------------------------------
 
-  STAT_FIFO_TO_INT(2 downto 0)   <= fifo_to_int_data_in(2 downto 0);
-  STAT_FIFO_TO_INT(3)            <= fifo_to_int_write;
-  STAT_FIFO_TO_INT(6 downto 4)   <= buf_INT_MASTER_PACKET_NUM_OUT;
-  STAT_FIFO_TO_INT(7)            <= buf_INT_MASTER_DATAREADY_OUT;
-  STAT_FIFO_TO_INT(8)            <= INT_MASTER_READ_IN;
-  STAT_FIFO_TO_INT(11 downto 9)  <= fifo_to_int_data_out(2 downto 0);
-  STAT_FIFO_TO_INT(12)           <= fifo_to_int_read;
-  STAT_FIFO_TO_INT(13)           <= fifo_to_int_read_before;
-  STAT_FIFO_TO_INT(14)           <= fifo_to_int_full;
-  STAT_FIFO_TO_INT(15)           <= fifo_to_int_empty;
-  STAT_FIFO_TO_INT(16)           <= next_APL_DATAREADY_OUT;
-  STAT_FIFO_TO_INT(17)           <= sbuf_to_apl_free;
-  STAT_FIFO_TO_INT(18)           <= fifo_to_apl_read_before;
-  STAT_FIFO_TO_INT(19)           <= slave_running;
-  STAT_FIFO_TO_INT(20)           <= buf_APL_RUN_OUT;
-  STAT_FIFO_TO_INT(21)           <= master_running;
-  STAT_FIFO_TO_INT(24 downto 22) <= next_INT_MASTER_PACKET_NUM_OUT;
-  STAT_FIFO_TO_INT(25)           <= next_INT_MASTER_DATAREADY_OUT;
-  STAT_FIFO_TO_INT(28 downto 26) <= state_bits_to_int;
-  STAT_FIFO_TO_INT(31 downto 29) <= state_bits_to_apl;
-
-  STAT_FIFO_TO_APL(2 downto 0)   <= fifo_to_apl_data_in(2 downto 0);
-  STAT_FIFO_TO_APL(3)            <= fifo_to_apl_write;
+  STAT_FIFO_TO_INT(2 downto 0)   <= fifo_to_int_data_in(2 downto 0);  
+  STAT_FIFO_TO_INT(3)            <= fifo_to_int_write;                
+  STAT_FIFO_TO_INT(6 downto 4)   <= buf_INT_MASTER_PACKET_NUM_OUT;    
+  STAT_FIFO_TO_INT(7)            <= buf_INT_MASTER_DATAREADY_OUT;     
+  STAT_FIFO_TO_INT(8)            <= INT_MASTER_READ_IN;               
+  STAT_FIFO_TO_INT(11 downto 9)  <= fifo_to_int_data_out(2 downto 0); 
+  STAT_FIFO_TO_INT(12)           <= fifo_to_int_read;                 
+  STAT_FIFO_TO_INT(13)           <= fifo_to_int_read_before;          
+  STAT_FIFO_TO_INT(14)           <= fifo_to_int_full;                 
+  STAT_FIFO_TO_INT(15)           <= fifo_to_int_empty;                
+  STAT_FIFO_TO_INT(16)           <= next_APL_DATAREADY_OUT;           
+  STAT_FIFO_TO_INT(17)           <= sbuf_to_apl_free;                 
+  STAT_FIFO_TO_INT(18)           <= fifo_to_apl_read_before;          
+  STAT_FIFO_TO_INT(19)           <= slave_running;                    
+  STAT_FIFO_TO_INT(20)           <= buf_APL_RUN_OUT;                  
+  STAT_FIFO_TO_INT(21)           <= master_running;                   
+  STAT_FIFO_TO_INT(24 downto 22) <= next_INT_MASTER_PACKET_NUM_OUT;   
+  STAT_FIFO_TO_INT(25)           <= next_INT_MASTER_DATAREADY_OUT;    
+  STAT_FIFO_TO_INT(28 downto 26) <= state_bits_to_int;                
+  STAT_FIFO_TO_INT(31 downto 29) <= state_bits_to_apl;                
+
+  STAT_FIFO_TO_APL(2 downto 0)   <= fifo_to_apl_data_in(2 downto 0);  
+  STAT_FIFO_TO_APL(3)            <= fifo_to_apl_write;                
   STAT_FIFO_TO_APL(7 downto 4)   <= (others => '0');
-  STAT_FIFO_TO_APL(9 downto 8)   <= fifo_to_apl_data_out(1 downto 0);
-  STAT_FIFO_TO_APL(10)           <= reg_APL_DATAREADY_OUT;
-  STAT_FIFO_TO_APL(11)           <= fifo_to_apl_read;
-  STAT_FIFO_TO_APL(12)           <= INT_SLAVE_DATAREADY_IN;
-  STAT_FIFO_TO_APL(13)           <= reg_INT_SLAVE_READ_OUT;
-  STAT_FIFO_TO_APL(14)           <= fifo_to_apl_full;
-  STAT_FIFO_TO_APL(15)           <= fifo_to_apl_empty;
+  STAT_FIFO_TO_APL(9 downto 8)   <= fifo_to_apl_data_out(1 downto 0); 
+  STAT_FIFO_TO_APL(10)           <= reg_APL_DATAREADY_OUT;            
+  STAT_FIFO_TO_APL(11)           <= fifo_to_apl_read;                 
+  STAT_FIFO_TO_APL(12)           <= INT_SLAVE_DATAREADY_IN;           
+  STAT_FIFO_TO_APL(13)           <= reg_INT_SLAVE_READ_OUT;           
+  STAT_FIFO_TO_APL(14)           <= fifo_to_apl_full;                 
+  STAT_FIFO_TO_APL(15)           <= fifo_to_apl_empty;                
   --STAT_FIFO_TO_APL(13 downto 12) <= (others => '0');
-  STAT_FIFO_TO_APL(31 downto 16) <= (others => '0');
+  STAT_FIFO_TO_APL(18 downto 16) <= master_counter;
+  STAT_FIFO_TO_APL(31 downto 19) <= (others => '0');
 
 end architecture;

diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd
index a7a7954df46b96cbdd39734bf93315aaf61eef47..66cdbbed6a850e2988d1f03a19178b4becc3741d 100644 (file)
--- a/trb_net16_hub_base.vhd
+++ b/trb_net16_hub_base.vhd
@@ -1732,8 +1732,10 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1');
 --   
 --   buf_STAT_DEBUG(15) <= buf_to_hub_INIT_DATAREADY(0*4+3);
   
-  buf_STAT_DEBUG(31 downto 16) <= (others => '0');
-
+  
+  buf_STAT_DEBUG( 3 downto 0 ) <= STAT_TIMEOUT(3*32+3 downto 3*32);
+  buf_STAT_DEBUG( 7 downto 4 ) <= HUB_CTRL_final_activepoints(3*32+3 downto 3*32);
+  
 
   IOBUF_STAT_INIT_OBUF_DEBUG <= iobuf_stat_init_obuf_debug_i;
   IOBUF_STAT_REPLY_OBUF_DEBUG <= iobuf_stat_reply_obuf_debug_i;