\item[0x86: Downlinks] Configuration of the Ports. Each bit gives the configuration of one port: 1 if this port is configured as downlink, 0 if not.
\item[0x87: IPU channel state] Shows the current state of the state machine handling the IPU channel.
\begin{description}
- \item[0 - 3:] FSM state
+ \item[Bit 0 - 3] FSM state
\begin{description}
\item[0x0] IDLE
\item[0x1] Waiting for reply
\item[0xB] Waiting for init channel to finish
\item[0xF] Default value
\end{description}
- \item[4 - 9:] don't care
- \item[10 - 12:] current packet counter
- \item[13 - 15:] read pointer to DHDR memory
+ \item[Bit 4 - 9] don't care
+ \item[Bit 10 - 12] current packet counter
+ \item[Bit 13 - 15] read pointer to DHDR memory
\end{description}
\item[0x88 - 0x8B: Timeouts $\dagger$] One register for each TrbNet channel. Each bit gives the status of one port: 1 if there was a timeout on this port, 0 otherwise. These registers are cleared after being read.
\item[0x8C - 0x8F: Waiting for ACK] One register for each TrbNet channel. Each bit gives the status of one port: 1 if data transmission on this port is stopped because the receiver did not acknowledge previous EOB words, 0 otherwise.
\item Bit 16 - 23: Errorbits 0 - 7 on IPU channel
\item Bit 24 - 31: Errorbits 16 - 23 on IPU channel
\end{itemize}
- \item[0x4030 - 0x403F] Inclusive busy counter. One register for each port counting the time the port is busy (waiting for the reply after a trigger has been sent). Writing to 0x4030 clears all counters.
- \item[0x4040 - 0x404F] Exclusive busy counter. One register for each port counting the time this port and only this port is busy (waiting for the reply after a trigger has been sent). Writing to 0x4040 clears all counters.
- \item[0x4050] Here, the global time also accessible in register 0x50 is readable. This allows to do a simultaneous readout with the busy counter registers to get exact time information.
+ \item[0x4030 - 0x403F: Inclusive busy counter]One register for each port counting the time the port is busy (waiting for the reply after a trigger has been sent). Writing to 0x4030 clears all counters.
+ \item[0x4040 - 0x404F: Exclusive busy counter] One register for each port counting the time this port and only this port is busy (waiting for the reply after a trigger has been sent). Writing to 0x4040 clears all counters.
+ \item[0x4050: Global Time] Here, the global time also accessible in register 0x50 is readable. This allows to do a simultaneous readout with the busy counter registers to get exact time information.
\end{description}
$\dagger$: Register is not reset during network reset
\subsection{RegIO Data Port}
\begin{description}
- \item[0x0000 - 0x00FF] Standard internal RegIO addresses
- \item[0x1000 - 0x3FFF] Reserved in hub\_base for monitoring features
- \item[0x4000 - 0x7FFF] Reserved in hub\_base
- \item[0x8000 - 0xBFFF] Forwarded to \portname{REGIO} ports of hub\_base, reserved for GbE
- \item[0xC000 - 0xFFFF] Forwarded to \portname{REGIO} ports of hub\_base, reserved for board specific funtions, e.g. 0xD000 - 0xD2FF for Flash programming
+ \item[0x0000 - 0x00FF:] Standard internal RegIO addresses
+ \item[0x1000 - 0x3FFF:] Reserved in hub\_base for monitoring features
+ \item[0x4000 - 0x7FFF:] Reserved in hub\_base
+ \item[0x8000 - 0xBFFF:] Forwarded to \portname{REGIO} ports of hub\_base, reserved for GbE
+ \item[0xC000 - 0xFFFF:] Forwarded to \portname{REGIO} ports of hub\_base, reserved for board specific funtions, e.g. 0xD000 - 0xD2FF for Flash programming
\end{description}