end process;
--- -------------------------------------------------
--- -- Debug Registers
--- -------------------------------------------------
--- debug_reg(3 downto 0) <= rx_fsm_state;
--- debug_reg(4) <= rx_k;
--- debug_reg(5) <= rx_error;
--- debug_reg(6) <= rx_los_low;
--- debug_reg(7) <= rx_cdr_lol;
---
--- debug_reg(8) <= tx_k;
--- debug_reg(9) <= tx_pll_lol;
--- debug_reg(10) <= lsm_status;
--- debug_reg(11) <= make_link_reset_i;
--- debug_reg(15 downto 12) <= tx_fsm_state;
--- -- debug_reg(31 downto 24) <= tx_data;
---
--- debug_reg(16) <= '0';
--- debug_reg(17) <= tx_allow;
--- debug_reg(18) <= RESET;
--- debug_reg(19) <= CLEAR;
--- debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8);
---
--- debug_reg(35 downto 32) <= wa_position(3 downto 0);
--- debug_reg(36) <= debug_tx_control_i(6);
--- debug_reg(39 downto 37) <= "000";
--- debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0);
STAT_DEBUG <= (others => '0'); --debug_reg;
generated_status : for i in 0 to 3 generate
- STAT_OP(i)(15) <= send_link_reset_i(i) when rising_edge(SYSCLK);\r
- STAT_OP(i)(14) <= '0';\r
- STAT_OP(i)(13) <= internal_make_link_reset_out(i) when rising_edge(SYSCLK); --make trbnet reset\r
- STAT_OP(i)(12) <= '0';\r
- STAT_OP(i)(11) <= '0';\r
- STAT_OP(i)(10) <= rx_allow(i);\r
- STAT_OP(i)(9) <= tx_allow(i);\r
- STAT_OP(i)(8) <= got_link_ready_i(i) when rising_edge(rx_half_clk(i));\r
- STAT_OP(i)(7) <= send_link_reset_i(i);\r
- STAT_OP(i)(6) <= make_link_reset_i(i);\r
- STAT_OP(i)(5) <= request_retr_i(i);\r
- STAT_OP(i)(4) <= start_retr_i(i);\r
- STAT_OP(i)(3 downto 0) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7";\r
+ STAT_OP(i*16 + 15) <= send_link_reset_i(i) when rising_edge(SYSCLK);\r
+ STAT_OP(i*16 + 14) <= '0';\r
+ STAT_OP(i*16 + 13) <= internal_make_link_reset_out(i) when rising_edge(SYSCLK); --make trbnet reset\r
+ STAT_OP(i*16 + 12) <= '0';\r
+ STAT_OP(i*16 + 11) <= '0';\r
+ STAT_OP(i*16 + 10) <= rx_allow(i);\r
+ STAT_OP(i*16 + 9) <= tx_allow(i);\r
+ STAT_OP(i*16 + 8) <= got_link_ready_i(i) when rising_edge(rx_half_clk(i));\r
+ STAT_OP(i*16 + 7) <= send_link_reset_i(i);\r
+ STAT_OP(i*16 + 6) <= make_link_reset_i(i);\r
+ STAT_OP(i*16 + 5) <= request_retr_i(i);\r
+ STAT_OP(i*16 + 4) <= start_retr_i(i);\r
+ STAT_OP(i*16 + 3 downto i*16) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7";\r
end generate;
end med_ecp3_sfp_4_sync_down_arch;
constant c_QUAD_DATA_WIDTH : integer := 4*c_DATA_WIDTH;
constant c_QUAD_NUM_WIDTH : integer := 4*c_NUM_WIDTH;
- constant c_QUAD_MUX_WIDTH : integer := 3; --!!!\r
+ constant c_QUAD_MUX_WIDTH : integer := 3; --\r
subtype t_HUB_BIT is std_logic_vector(c_HUB_CHILDREN-1 downto 0);
type t_HUB_NUM is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(c_NUM_WIDTH-1 downto 0);
);
end component;
- component med_ecp3_sfp_4_sync_down is
+ component med_ecp3_sfp_4_sync_down
generic( SERDES_NUM : integer range 0 to 3 := 0;
IS_SYNC_SLAVE : integer := c_NO); --select slave mode
port(
SCI_NACK => sci2_nack,\r
\r
--Status and control port\r
- STAT_OP(0) => med_stat_op(1*16+15 downto 1*16),\r
- STAT_OP(1) => med_stat_op(6*16+15 downto 6*16),\r
- STAT_OP(2) => med_stat_op(2*16+15 downto 2*16),\r
- STAT_OP(3) => med_stat_op(4*16+15 downto 4*16),\r
-\r
- CTRL_OP(0) => med_ctrl_op(1*16+15 downto 1*16),\r
- CTRL_OP(1) => med_ctrl_op(6*16+15 downto 6*16),\r
- CTRL_OP(2) => med_ctrl_op(2*16+15 downto 2*16),\r
- CTRL_OP(3) => med_ctrl_op(4*16+15 downto 4*16),\r
+ STAT_OP(15 downto 0) => med_stat_op(1*16+15 downto 1*16),\r
+ STAT_OP(31 downto 16) => med_stat_op(6*16+15 downto 6*16),\r
+ STAT_OP(47 downto 32) => med_stat_op(2*16+15 downto 2*16),\r
+ STAT_OP(63 downto 48) => med_stat_op(4*16+15 downto 4*16),\r
+\r
+ CTRL_OP(15 downto 0) => med_ctrl_op(1*16+15 downto 1*16),\r
+ CTRL_OP(31 downto 16) => med_ctrl_op(6*16+15 downto 6*16),\r
+ CTRL_OP(47 downto 32) => med_ctrl_op(2*16+15 downto 2*16),\r
+ CTRL_OP(63 downto 48) => med_ctrl_op(4*16+15 downto 4*16),\r
\r
STAT_DEBUG => open,\r
CTRL_DEBUG => (others => '0')\r