Try with 80 again

diff --git a/ADC/config.vhd b/ADC/config.vhd
index 9204326957b338f9fd61c95cf0b522b5b4f10b11..6d6bf785c74c17074bb44fafa9cf3beb1396cda6 100644 (file)
--- a/ADC/config.vhd
+++ b/ADC/config.vhd
@@ -30,7 +30,7 @@ package config is
 --note that not all READOUT_MODEs will lead to timing-error free designs
 --the READOUT_MODE_PSA mode is usually only working with 40MHz
 --the READOUT_MODE_CFD mode is more robust against clock domain crossing issues 
-    constant ADC_SAMPLING_RATE      : integer := 64;
+    constant ADC_SAMPLING_RATE      : integer := 80;
     
 --These are currently used for the included features table only
     constant ADC_BASELINE_LOGIC     : integer := c_YES;