--- /dev/null
+
+all: main clean
+
+pdflatex := pdflatex
+bibtex8 := bibtex8
+
+.PHONY: main
+main: main.tex biblio.bib
+ $(pdflatex) main.tex
+ $(pdflatex) main.tex
+
+
+.PHONY: clean
+clean:
+ -@rm *.toc *.log *.aux *.out *.bbl *.blg
+
--- /dev/null
+\subsection{Going synchronous}
+
+As the TrbNet in its current version lacks the support for fully synchronous operation,
+a first step will be to change the serial links into fully synchronous operation.
+
+This involves a clock distribution and recovery scheme, and also has side effects on
+the old way of sending resets. As synchronous links will --- by nature -- always be established
+from the inner part to the outer part of the DAQ network, the "old style" reset will not be
+appropriate for the new system. Links will not be destroyed by a reset anymore.
+
+The system will handle clock and links as following:
+
+\begin{itemize*}
+ \item The CTS will contain the "true" Master Port. The Link clock used on the CTS board
+ will be distributed to all boards in the system.
+ \item The internal logic of boards will stay on 100MHz, the link clock will be
+ independent of the internal 100MHz clock. Going to 125MHZ on links will allow using
+ low power bidi SFPs.
+ \item Any Slave Port in the system will keep its board in reset state unless a clock
+ could be recovered from the Uplink.
+ \item Branches and boards can be hard reset by disabling the corresponding Master Port
+ SFP transmitter. No complex komma based central reset is necessary anymore.
+ \item The recovered RX clock will be used on all TX SerDes channels of a FPGA, including
+ the downlink. All RX SerDes will synchronize on WordAlignmentZero only.
+ This allows simple round trip delay measurements.
+\end{itemize*}
+
+The system behaviour should not change in a user noticeable way. Link establishment may take a
+bit longer, due to waiting for a stable recovered RX clock. The WordAlignment may also
+increase link establishment time, as bit position zero is mandatory, and some attempts may be needed
+to lock a link for that specific bit position.
--- /dev/null
+\subsection{Link establishment}
+
+Due to the usage of recovered RX clock in all FPGAs, the link establishment
+has to be carefully handled, to avoid starting up a link while the needed
+clock is not available or not stable yet.
+
+The med{\_}sync{\_}ctrl block has been reworked for that issue, with some important changes
+to the med{\_}ecpX{\_}sfp{\_}sync block instantiating it:
+
+\begin{itemize*}
+ \item There is only one TX reset control per FPGA now, not one per SerDes channed used.
+ \item All TX SerDes channels are reset and synchronized at once.
+ \item Every RX SerDes channel gets its own RX reset control.
+ \item As new building block, a simple RX LSM is included to check the link establishment.
+ \item Ideally, only one med{\_}ecpX{\_}sfp{\_}sync block will be available, which can be configured
+ to the usage needed in the design.
+ \item The design will have to take care to correctly wire the med{\_}ecpX{\_}sfp{\_}sync blocks,
+ while all internally necessary adjustments are steered by generics.
+ \item Both TX and RX control deliver one status signal which clearly defines that the link
+ can be used to transmit or receive kommas.
+\end{itemize*}
+
+The link establishment process is explained on a hub FPGA slave port as example:
+
+\begin{itemize*}
+ \item The hub FPGA is in reset while no fiber is connected or the master port it is connected
+ to has its TX{\_}DIS line set.
+ \item HUB SP: A stream of IDLE kommas is received, so the RX reset sequence is completed
+ and a lock to incoming kommas by the FPGA internal state machine is made.
+ \item HUB SP: Once WAP=0 is achieved, the RX reset control will declare the RX recovered clock stable,
+ and initiate the TX reset sequence. LINK{\_}RX{\_}READY is set, while toggling IDLEs are received,
+ the uplink is stable now.
+ \item HUB SP: The TX reset sequence waits for all QUADs in use to lock on the TX reference clock (i.e.
+ the recovered RX clock from slave port), and sync all TX Serializers to bit 0. LINK{\_}TX{\_}READY is set.
+ \item HUB SP: The TX control sends a togglinge idle sequence after the downlink is stable.
+ \item HUB SP: The RX LSM will check for a sequence of toggling IDLEs, and after detection set the
+ LINK{\_}HALF{\_}DONE signal.
+ \item CTS MP: the toggling IDLEs are received, a RX reset sequence is performed and a lock
+ to WAP=0 made. This will set LINK{\_}RX{\_}READY in the master port, and change the toggling IDLEs in the uplink
+ to steady IDLEs (IDLE1).
+ \item HUB SP: The RX LSM detects a series of steady IDLEs, and switches to LINK{\_}FULL{\_}DONE internally.
+ The TX control is instructed to send steady IDLEs now. Both UP and DL are considered stable, and TrbNet
+ payloads (as well as special kommas) can be sent and received now.
+ \item CTS MP: The RX LSM detects a series of steady IDLEs, and switches to LINK{\_}FULL{\_}DONE internally.
+ Both UP and DL are considered stable, and TrbNet payloads as well as special kommas are enabled now.
+\end{itemize*}
+
+
--- /dev/null
+\subsection{New resets}
+
+Resets will be handled differently.
+
+\begin{itemize*}
+ \item Resets do not destroy links by default.
+ \item Hard reset is done by destroying the recovered RX clock.
+ \item TrbNet sent resets are only handled by RX state machine.
+ \item The only valid source of resets beside is the GbE.
+\end{itemize*}
+
+As noted before, a master reset will be included in the new TrbNet.
+
+Any master port in the system will keep its SFP transmitter in "turned off" mode while
+being in reset, and can also control it for sending a hard reset to all boards connected.
+
+The current reset sequence (handled by a timed broadcast of RST kommas (0xfe) will be
+replaced by a much simpler scheme: a reset komma will consist of one RST komma character,
+followed by one data byte. RST kommas are unconditionally forwarded from any slave port
+to all master ports available, turning them into a broadcast komma.
+
+The RX control state machine will simply set a register with reception of a RST komma, and
+provides up to 8 independent reset lines, which should be assigned to dedicated groups of
+functions (like FE logic, trigger logic, buffers, whatever).
--- /dev/null
+\subsection{Nomenclature used in this section}
+\begin{itemize*}
+ \item \textbf{Master Port (MP)}: a serial link port which initiates a connection.
+ In this document, a MP always points "outwards" from CTS to FEs.
+ \item \textbf{Slave Port (SP)}: a serial link port which connects to a master port.
+ In this document, a SP always points "inwards" from FEs to CTS.
+ \item \textbf{Uplink (UL)}: the serial connection between a MP and a SP.
+ From CTS point of view, data is transmitted from CTS towards FE on an UL.
+ \item \textbf{Downlink (DL):} the serial connection between a SP and a MP.
+ From CTS point of view, data is transmitted from FEs towards CTS on a DL.
+\end{itemize*}
+
+To avoid confusion with regard of political correctness, the terms mentioned above
+are being used without political intent.
+
+No animals were harmed writing this document.
+
+The following kommas will be used in the DeepSea TrbNet branch:
+
+\begin{table}[ht]
+\begin{center}
+\begin{tabular}{|c|c|c|c|}
+ \hline
+ \textbf{Name} & \textbf{Full Name} & \textbf{K Character} & \textbf{D Character}\\
+\hline\hline
+IDLE& Idle & BC & C5 (idle0) or 50 (idle1)\\
+SOP & Start of Packet & DC & reserved for packet delimiter\\
+EOP & End of Packet & FD & reserved for packet delimiter \\
+BGN & Begin of Transmission & 1C & reserved for retransmission\\
+REQ & Retransmit Request & 7C & reserved for retransmission\\
+DLM & DLM & FB & Deterministic Latency Message \\
+& & 3C & \\
+& & 5C & \\
+& & 9C & \\
+& & FC & \\
+& & F7 & \\
+RST & Reset & FE & bit-coded reset lines\\
+\hline
+\end{tabular}
+\caption{Comma Characters}
+\end{center}
+\end{table}
\ No newline at end of file
--- /dev/null
+\subsection{Proposed Changes}
+\begin{itemize*}
+ \item The central FPGA
+ \item All FPGA run on a central clock, each network node recovers the clock from the optical link and uses it as the main clock source for all design components.
+ \item Low-level messages with deterministic latency can be inserted in the data stream and forwarded in the direction toward the front-ends
+ \item Links toward the front-ends run in bit-synchronous mode, i.e. the word alignment of the Serdes is always locked on Bit 0.
+ \item Links toward the read-out run in clock-synchronous mode only, i.e. the round-trip time for a packet can be measured with one word length (currently 5 ns) precision only.
+\end{itemize*}
+
+
\section{Media Interfaces}
\input{SyncMediaInterface}
+\cleardoublepage
+\part{DeepSea TrbNet}
+ \section{Redefining TrbNet}
+ \input{DS_Nomenclature.tex}
+ \input{DS_GoingSynchronous.tex}
+ \input{DS_NewResets.tex}
+ \input{DS_LinkEstablishment.tex}
+
\cleardoublepage
\begin{appendices}
\section{TDC Online Calibration}
jspc29 / daqdocu.git / commitdiff