WAPZ included, uplink seems to work now

diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd
index fcdcb31ac6915fdfe7e25b9583fbf8495e40f1bc..f384c549cb44dc95acb2bd284b19ad00267f018b 100644 (file)
--- a/tdctemplate/trb3sc_tdctemplate.vhd
+++ b/tdctemplate/trb3sc_tdctemplate.vhd
@@ -147,12 +147,11 @@ architecture trb3sc_arch of trb3sc_tdctemplate is
   attribute syn_preserve of bustc_rx    : signal is true;
   
   signal tx_pll_lol_qd_b_i : std_logic;
-  signal rst_qd_c_i        : std_logic;
-  signal tx_pcs_rst_ch_c_i : std_logic;
+  signal tx_pll_lol_all_i  : std_logic;
   signal sync_tx_quad_i    : std_logic;
+  signal tx_clk_avail_i    : std_logic;
   signal link_tx_ready_i   : std_logic;
-  signal tx_reset_i        : std_logic;
-  signal tx_clock_avail_i  : std_logic;
+  signal tx_pcs_rst_i      : std_logic;
   signal debug_i           : std_logic_vector(31 downto 0);
   signal rx_dlm_i          : std_logic;
   signal word_sync_i       : std_logic;
@@ -213,7 +212,6 @@ end generate;
 ---------------------------------------------------------------------------
 -- TrbNet Uplink
 ---------------------------------------------------------------------------
-
   THE_MEDIA_INTERFACE : entity med_ecp3_sfp_sync_all_RS
     generic map(
       SERDES_NUM         => 3,
@@ -248,21 +246,23 @@ end generate;
       RX_RST_WORD_OUT    => open,
       TX_RST_IN          => '0',
       TX_RST_WORD_IN     => x"00",
+      -- sync operation
       WORD_SYNC_IN       => word_sync_i, -- downlink synced to uplink
       WORD_SYNC_OUT      => word_sync_i,
-      MASTER_CLK_IN      => master_clk_i, -- downlink uses upling clock
+      MASTER_CLK_IN      => master_clk_i, -- downlink uses uplink clock
       MASTER_CLK_OUT     => master_clk_i,
-      MASTER_RESET_OUT   => master_reset_i, --open,
+      GLOBAL_RESET_IN    => master_reset_i,
+      GLOBAL_RESET_OUT   => master_reset_i,
+      TX_PLL_LOL_IN      => tx_pll_lol_all_i,
+      TX_PLL_LOL_OUT     => tx_pll_lol_qd_b_i,
+      TX_CLK_AVAIL_OUT   => tx_clk_avail_i,
+      TX_PCS_RST_IN      => tx_pcs_rst_i,
+      SYNC_TX_PLL_IN     => sync_tx_quad_i,
+      LINK_TX_READY_IN   => link_tx_ready_i,
       DESTROY_LINK_IN(0) => '0', 
       DESTROY_LINK_IN(1) => '0',
       DESTROY_LINK_IN(2) => '0',
       DESTROY_LINK_IN(3) => '0',
-      LINK_TX_READY_IN   => link_tx_ready_i,
-      TX_PLL_LOL_OUT     => tx_pll_lol_qd_b_i,
-      TX_RESET_OUT       => tx_reset_i,
-      SYNC_TX_PLL_IN     => sync_tx_quad_i,
-      RST_QUAD_IN        => rst_qd_c_i,
-      RST_TX_PCS_IN      => tx_pcs_rst_ch_c_i,
       --SFP Connection
       SD_PRSNT_N_IN(0)   => '1',
       SD_LOS_IN(0)       => '1',
@@ -285,54 +285,52 @@ end generate;
       DEBUG_OUT          => debug_i
     );
 
-  SFP_TX_DIS(0) <= '0' when USE_GBE = 1 else '1';
-
-  tx_clock_avail_i <= not tx_reset_i; -- change ports!
-  
-  THE_MAIN_TX_RESET: main_tx_reset_RS
+  THE_MAIN_TX_RST: main_tx_reset_RS
   generic map(
     SIM_MODE    => 0
   )
-  port map(
-    CLEAR                => clear_i,
+  port map (
+    CLEAR                => '0',
     LOCALCLK             => clk_full_osc,
     TX_PLL_LOL_QD_A_IN   => '0',
     TX_PLL_LOL_QD_B_IN   => tx_pll_lol_qd_b_i,
     TX_PLL_LOL_QD_C_IN   => '0',
     TX_PLL_LOL_QD_D_IN   => '0',
-    TX_CLOCK_AVAIL_IN    => tx_clock_avail_i, -- for testing...
-    RST_QD_C_OUT         => rst_qd_c_i,
-    TX_PCS_RST_CH_C_OUT  => tx_pcs_rst_ch_c_i,
+    TX_PLL_LOL_OUT       => tx_pll_lol_all_i,
+    TX_CLOCK_AVAIL_IN    => tx_clk_avail_i,
+    TX_PCS_RST_CH_C_OUT  => tx_pcs_rst_i,
     SYNC_TX_QUAD_OUT     => sync_tx_quad_i,
     LINK_TX_READY_OUT    => link_tx_ready_i,
-    STATE_OUT            => tx_reset_state --open
+    STATE_OUT            => tx_reset_state
   );
 
+  SFP_TX_DIS(0) <= '0' when USE_GBE = 1 else '1';
+
   --HDR_IO(10 downto 1) <= (others => '0');
-  HDR_IO(10)   <= master_reset_i;
-  HDR_IO(9)    <= clear_i;
-  HDR_IO(8)    <= tx_pll_lol_qd_b_i;
-  HDR_IO(7)    <= tx_clock_avail_i;
-  HDR_IO(6)    <= rst_qd_c_i;
-  HDR_IO(5)    <= tx_pcs_rst_ch_c_i;
-  HDR_IO(4)    <= tx_reset_state(3); --sync_tx_quad_i;
-  HDR_IO(3)    <= tx_reset_state(2); --'0';
-  HDR_IO(2)    <= tx_reset_state(1); --rx_dlm_i;
-  HDR_IO(1)    <= tx_reset_state(0); --'0';
+  HDR_IO(10)   <= tx_reset_state(3);
+  HDR_IO(9)    <= tx_reset_state(2);
+  HDR_IO(8)    <= tx_reset_state(1);
+  HDR_IO(7)    <= tx_reset_state(0);
+  HDR_IO(6)    <= '0';
+  HDR_IO(5)    <= '0';
+  HDR_IO(4)    <= '0';
+  HDR_IO(3)    <= '0';
+  HDR_IO(2)    <= rx_dlm_i;
+  HDR_IO(1)    <= '0';
 
   TEST_LINE <= debug_i(15 downto 0);
   
 --  TEST_LINE(0)  <= tx_pll_lol_qd_b_i;
---  TEST_LINE(1)  <= rst_qd_c_i;
---  TEST_LINE(2)  <= tx_pcs_rst_ch_c_i;
+--  TEST_LINE(1)  <= '0';
+--  TEST_LINE(2)  <= '0';
 --  TEST_LINE(3)  <= sync_tx_quad_i;
---  TEST_LINE(4)  <= link_tx_ready_i;
+--  TEST_LINE(4)  <= '0';
 --  TEST_LINE(5)  <= debug_i(4); -- rx_los
 --  TEST_LINE(6)  <= debug_i(3); -- rx_cdr_lol 
 --  TEST_LINE(7)  <= debug_i(0); -- link_rx_ready
 --  TEST_LINE(8)  <= debug_i(1); -- link_half_done
 --  TEST_LINE(9)  <= debug_i(2); -- link_full_done
---  TEST_LINE(10) <= tx_reset_i;
+--  TEST_LINE(10) <= '0';
 --  TEST_LINE(11) <= debug_i(5); -- SFP_LOS_IN
 --  TEST_LINE(12) <= '0';
 --  TEST_LINE(13) <= '0';