--- /dev/null
+../../trb3sc/scripts/compile.pl
\ No newline at end of file
--- /dev/null
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+
+package config is
+
+
+------------------------------------------------------------------------------
+--Begin of design configuration
+------------------------------------------------------------------------------
+
+
+--set to 0 for backplane serdes, set to 1 for SFP serdes
+ constant SERDES_NUM : integer := 1;
+
+--TDC settings
+ constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5
+ constant FPGA_SIZE : string := "45KUM";
+ constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module
+ constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons
+
+ constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 10; -- size of the event buffer, 2**N
+ constant EVENT_MAX_SIZE : integer := 400; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2
+
+
+--Use sync mode, RX clock for all parts of the FPGA
+ constant USE_RXCLOCK : integer := c_NO;
+ constant USE_120_MHZ : integer := c_NO;
+
+--Address settings
+ constant INIT_ADDRESS : std_logic_vector := x"F6DC";
+ constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"91";
+
+ constant INCLUDE_UART : integer := c_NO; --300 slices
+ constant INCLUDE_SPI : integer := c_YES; --300 slices
+ constant INCLUDE_LCD : integer := c_NO; --800 slices
+ constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices
+
+ --input monitor and trigger generation logic
+ constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; --400 slices @32->2
+ constant INCLUDE_STATISTICS : integer := c_YES; --1300 slices, 1 RAM @32
+ constant TRIG_GEN_INPUT_NUM : integer := 32;
+ constant TRIG_GEN_OUTPUT_NUM : integer := 4;
+ constant MONITOR_INPUT_NUM : integer := 32;
+
+------------------------------------------------------------------------------
+--End of design configuration
+------------------------------------------------------------------------------
+
+
+ type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
+ constant LCD_DATA : data_t := (others => x"00");
+
+------------------------------------------------------------------------------
+--Select settings by configuration
+------------------------------------------------------------------------------
+ type intlist_t is array(0 to 7) of integer;
+ type hw_info_t is array(0 to 7) of unsigned(31 downto 0);
+ constant HW_INFO_BASE : unsigned(31 downto 0) := x"A7000000";
+
+
+ --declare constants, filled in body
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0);
+ constant CLOCK_FREQUENCY : integer;
+ constant MEDIA_FREQUENCY : integer;
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0);
+
+
+end;
+
+package body config is
+--compute correct configuration mode
+
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE );
+ constant CLOCK_FREQUENCY : integer := 100;
+ constant MEDIA_FREQUENCY : integer := 200;
+
+function generateIncludedFeatures return std_logic_vector is
+ variable t : std_logic_vector(63 downto 0);
+ begin
+ t := (others => '0');
+ t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1
+
+ t(7 downto 0) := std_logic_vector(to_unsigned(1,8));
+-- t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4));
+-- t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3));
+ t(15) := '1'; --TDC
+ t(17 downto 16) := "00";
+
+ t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
+ t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+ t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
+ t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+ t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+ t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
+ t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+ t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+ return t;
+ end function;
+
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;
+
+end package body;
--- /dev/null
+Familyname => 'ECP5UM',
+Devicename => 'LFE5UM-45F',
+Package => 'CABGA381',
+Speedgrade => '8',
+
+
+TOPNAME => "mdctdc",
+lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_par => "1710\@jspc29",
+lattice_path => '/d/jspc29/lattice/diamond/3.11_x64',
+synplify_path => '/d/jspc29/lattice/synplify/R-2020.09-SP1/',
+
+nodelist_file => '../nodelist_frankfurt.txt',
+pinout_file => 'dbo',
+par_options => '../par.p2t',
+
+
+#Include only necessary lpf files
+include_TDC => 0,
+include_GBE => 0,
+
+#Report settings
+firefox_open => 0,
+twr_number_of_errors => 20,
+no_ltxt2ptxt => 1, #if there is no serdes being used
--- /dev/null
+#################################################################
+# Basic Settings
+#################################################################
+
+FREQUENCY PORT CLK 200 MHz;
+FREQUENCY PORT CLK_TDC 156.25 MHz;
+BLOCK PATH TO PORT "LED*";
+BLOCK PATH TO PORT "PROGRAMN";
+
+# FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
+# FREQUENCY NET "med2int_0.clk_full" 200 MHz;
+
+FREQUENCY NET "THE_MEDIA_INTERFACE/clk_rx_full" 200 MHz;
+FREQUENCY NET "THE_MEDIA_INTERFACE/clk_rx_full" 200 MHz;
+
+MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns;
+MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns;
+
+REGION "MEDIA" "R57C34D" 13 30;
+LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ;
+
+
+
+# USE PRIMARY NET THE_TDC/calibration_pulse ;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.0.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.1.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.2.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.3.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.4.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.5.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.6.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.7.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.8.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.9.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.10.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.11.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.12.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.13.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.14.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.15.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.16.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.17.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.18.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.19.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.20.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.21.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.22.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.23.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.24.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.25.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.26.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.27.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.28.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.29.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.30.THE_CHANNEL/gated_inp 100;
+PRIORITIZE NET THE_TDC/gen_CHANNELS.31.THE_CHANNEL/gated_inp 100;
+
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.16.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.17.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.18.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.19.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.20.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.21.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.22.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.23.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.24.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.25.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.26.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.27.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.28.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.29.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.30.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.31.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.0.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.1.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.2.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.3.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.4.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.5.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.6.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.7.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.8.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.9.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.10.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.11.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.12.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.13.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.14.THE_CHANNEL/gated_inp" 0.500000 ns ;
+# MAXDELAY NET "THE_TDC/gen_CHANNELS.15.THE_CHANNEL/gated_inp" 0.500000 ns ;
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.0.THE_CHANNEL/THE_INP/InpLut" SITE "R59C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.0.THE_CHANNEL/THE_FF/FFregs" SITE "R59C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.0.THE_CHANNEL/THE_FFF/FFregs" SITE "R59C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.0.THE_CHANNEL/THE_FF2/FFregs2" SITE "R59C82D";##
+PROHIBIT SITE "R59C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.1.THE_CHANNEL/THE_INP/InpLut" SITE "R61C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.1.THE_CHANNEL/THE_FF/FFregs" SITE "R61C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.1.THE_CHANNEL/THE_FFF/FFregs" SITE "R61C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.1.THE_CHANNEL/THE_FF2/FFregs2" SITE "R61C82D";##
+PROHIBIT SITE "R61C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.2.THE_CHANNEL/THE_INP/InpLut" SITE "R63C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.2.THE_CHANNEL/THE_FF/FFregs" SITE "R63C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.2.THE_CHANNEL/THE_FFF/FFregs" SITE "R63C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.2.THE_CHANNEL/THE_FF2/FFregs2" SITE "R63C82D";##
+PROHIBIT SITE "R63C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.3.THE_CHANNEL/THE_INP/InpLut" SITE "R39C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.3.THE_CHANNEL/THE_FF/FFregs" SITE "R39C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.3.THE_CHANNEL/THE_FFF/FFregs" SITE "R39C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.3.THE_CHANNEL/THE_FF2/FFregs2" SITE "R39C82D";##
+PROHIBIT SITE "R39C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.4.THE_CHANNEL/THE_INP/InpLut" SITE "R42C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.4.THE_CHANNEL/THE_FF/FFregs" SITE "R42C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.4.THE_CHANNEL/THE_FFF/FFregs" SITE "R42C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.4.THE_CHANNEL/THE_FF2/FFregs2" SITE "R42C82D";##
+PROHIBIT SITE "R42C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.5.THE_CHANNEL/THE_INP/InpLut" SITE "R68C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.5.THE_CHANNEL/THE_FF/FFregs" SITE "R68C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.5.THE_CHANNEL/THE_FFF/FFregs" SITE "R68C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.5.THE_CHANNEL/THE_FF2/FFregs2" SITE "R68C82D";##
+PROHIBIT SITE "R68C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.6.THE_CHANNEL/THE_INP/InpLut" SITE "R65C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.6.THE_CHANNEL/THE_FF/FFregs" SITE "R65C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.6.THE_CHANNEL/THE_FFF/FFregs" SITE "R65C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.6.THE_CHANNEL/THE_FF2/FFregs2" SITE "R65C82D";##
+PROHIBIT SITE "R65C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.7.THE_CHANNEL/THE_INP/InpLut" SITE "R44C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.7.THE_CHANNEL/THE_FF/FFregs" SITE "R44C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.7.THE_CHANNEL/THE_FFF/FFregs" SITE "R44C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.7.THE_CHANNEL/THE_FF2/FFregs2" SITE "R44C82D";##
+PROHIBIT SITE "R44C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.8.THE_CHANNEL/THE_INP/InpLut" SITE "R28C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.8.THE_CHANNEL/THE_FF/FFregs" SITE "R28C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.8.THE_CHANNEL/THE_FFF/FFregs" SITE "R28C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.8.THE_CHANNEL/THE_FF2/FFregs2" SITE "R28C82D" ;
+PROHIBIT SITE "R28C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.9.THE_CHANNEL/THE_INP/InpLut" SITE "R27C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.9.THE_CHANNEL/THE_FF/FFregs" SITE "R27C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.9.THE_CHANNEL/THE_FFF/FFregs" SITE "R27C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.9.THE_CHANNEL/THE_FF2/FFregs2" SITE "R27C82D";##
+PROHIBIT SITE "R27C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.10.THE_CHANNEL/THE_INP/InpLut" SITE "R35C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.10.THE_CHANNEL/THE_FF/FFregs" SITE "R35C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.10.THE_CHANNEL/THE_FFF/FFregs" SITE "R35C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.10.THE_CHANNEL/THE_FF2/FFregs2" SITE "R35C82D";##
+PROHIBIT SITE "R35C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.11.THE_CHANNEL/THE_INP/InpLut" SITE "R25C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.11.THE_CHANNEL/THE_FF/FFregs" SITE "R25C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.11.THE_CHANNEL/THE_FFF/FFregs" SITE "R25C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.11.THE_CHANNEL/THE_FF2/FFregs2" SITE "R25C82D";##
+PROHIBIT SITE "R25C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.12.THE_CHANNEL/THE_INP/InpLut" SITE "R31C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.12.THE_CHANNEL/THE_FF/FFregs" SITE "R31C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.12.THE_CHANNEL/THE_FFF/FFregs" SITE "R31C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.12.THE_CHANNEL/THE_FF2/FFregs2" SITE "R31C82D";##
+PROHIBIT SITE "R31C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.13.THE_CHANNEL/THE_INP/InpLut" SITE "R23C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.13.THE_CHANNEL/THE_FF/FFregs" SITE "R23C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.13.THE_CHANNEL/THE_FFF/FFregs" SITE "R23C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.13.THE_CHANNEL/THE_FF2/FFregs2" SITE "R23C82D";##
+PROHIBIT SITE "R23C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.14.THE_CHANNEL/THE_INP/InpLut" SITE "R37C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.14.THE_CHANNEL/THE_FF/FFregs" SITE "R37C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.14.THE_CHANNEL/THE_FFF/FFregs" SITE "R37C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.14.THE_CHANNEL/THE_FF2/FFregs2" SITE "R37C82D";##
+PROHIBIT SITE "R37C86C";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.15.THE_CHANNEL/THE_INP/InpLut" SITE "R15C86D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.15.THE_CHANNEL/THE_FF/FFregs" SITE "R15C84D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.15.THE_CHANNEL/THE_FFF/FFregs" SITE "R15C87D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.15.THE_CHANNEL/THE_FF2/FFregs2" SITE "R15C82D";##
+PROHIBIT SITE "R15C86C";
+
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.16.THE_CHANNEL/THE_INP/InpLut" SITE "R61C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.16.THE_CHANNEL/THE_FF/FFregs" SITE "R61C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.16.THE_CHANNEL/THE_FFF/FFregs" SITE "R61C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.16.THE_CHANNEL/THE_FF2/FFregs2" SITE "R61C8D";
+# PROHIBIT SITE "R61C3B";
+# PROHIBIT SITE "R61C3C";
+# PROHIBIT SITE "R61C4B";
+# PROHIBIT SITE "R61C4C";
+# PROHIBIT SITE "R61C6B";
+# PROHIBIT SITE "R61C6C";
+# PROHIBIT SITE "R61C7B";
+# PROHIBIT SITE "R61C7C";
+PROHIBIT SITE "R61C5C";
+# PROHIBIT SITE "R61C5B";
+# PROHIBIT SITE "R61C5D";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.17.THE_CHANNEL/THE_INP/InpLut" SITE "R65C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.17.THE_CHANNEL/THE_FF/FFregs" SITE "R65C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.17.THE_CHANNEL/THE_FFF/FFregs" SITE "R65C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.17.THE_CHANNEL/THE_FF2/FFregs2" SITE "R65C8D";
+# PROHIBIT SITE "R65C3B";
+# PROHIBIT SITE "R65C3C";
+# PROHIBIT SITE "R65C4B";
+# PROHIBIT SITE "R65C4C";
+# PROHIBIT SITE "R65C6B";
+# PROHIBIT SITE "R65C6C";
+# PROHIBIT SITE "R65C7B";
+# PROHIBIT SITE "R65C7C";
+PROHIBIT SITE "R65C5C";
+# PROHIBIT SITE "R65C5B";
+# PROHIBIT SITE "R65C5D";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.18.THE_CHANNEL/THE_INP/InpLut" SITE "R41C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.18.THE_CHANNEL/THE_FF/FFregs" SITE "R41C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.18.THE_CHANNEL/THE_FFF/FFregs" SITE "R41C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.18.THE_CHANNEL/THE_FF2/FFregs2" SITE "R41C8D";
+# PROHIBIT SITE "R41C3B";
+# PROHIBIT SITE "R41C3C";
+# PROHIBIT SITE "R41C4B";
+# PROHIBIT SITE "R41C4C";
+# PROHIBIT SITE "R41C6B";
+# PROHIBIT SITE "R41C6C";
+# PROHIBIT SITE "R41C7B";
+# PROHIBIT SITE "R41C7C";
+PROHIBIT SITE "R41C5C";
+# PROHIBIT SITE "R41C5B";
+# PROHIBIT SITE "R41C5D";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.19.THE_CHANNEL/THE_INP/InpLut" SITE "R68C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.19.THE_CHANNEL/THE_FF/FFregs" SITE "R68C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.19.THE_CHANNEL/THE_FFF/FFregs" SITE "R68C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.19.THE_CHANNEL/THE_FF2/FFregs2" SITE "R68C8D";
+# PROHIBIT SITE "R68C3B";
+# PROHIBIT SITE "R68C3C";
+# PROHIBIT SITE "R68C4B";
+# PROHIBIT SITE "R68C4C";
+# PROHIBIT SITE "R68C6B";
+# PROHIBIT SITE "R68C6C";
+# PROHIBIT SITE "R68C7B";
+# PROHIBIT SITE "R68C7C";
+PROHIBIT SITE "R68C5C";
+# PROHIBIT SITE "R68C5B";
+# PROHIBIT SITE "R68C5D";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.20.THE_CHANNEL/THE_INP/InpLut" SITE "R63C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.20.THE_CHANNEL/THE_FF/FFregs" SITE "R63C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.20.THE_CHANNEL/THE_FFF/FFregs" SITE "R63C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.20.THE_CHANNEL/THE_FF2/FFregs2" SITE "R63C8D";
+# PROHIBIT SITE "R63C3B";
+# PROHIBIT SITE "R63C3C";
+# PROHIBIT SITE "R63C4B";
+# PROHIBIT SITE "R63C4C";
+# PROHIBIT SITE "R63C6B";
+# PROHIBIT SITE "R63C6C";
+# PROHIBIT SITE "R63C7B";
+# PROHIBIT SITE "R63C7C";
+PROHIBIT SITE "R63C5C";
+# PROHIBIT SITE "R63C5B";
+# PROHIBIT SITE "R63C5D";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.21.THE_CHANNEL/THE_INP/InpLut" SITE "R39C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.21.THE_CHANNEL/THE_FF/FFregs" SITE "R39C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.21.THE_CHANNEL/THE_FFF/FFregs" SITE "R39C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.21.THE_CHANNEL/THE_FF2/FFregs2" SITE "R39C8D";
+# PROHIBIT SITE "R39C3B";
+# PROHIBIT SITE "R39C3C";
+# PROHIBIT SITE "R39C4B";
+# PROHIBIT SITE "R39C4C";
+# PROHIBIT SITE "R39C6B";
+# PROHIBIT SITE "R39C6C";
+# PROHIBIT SITE "R39C7B";
+# PROHIBIT SITE "R39C7C";
+PROHIBIT SITE "R39C5C";
+# PROHIBIT SITE "R39C5B";
+# PROHIBIT SITE "R39C5D";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.22.THE_CHANNEL/THE_INP/InpLut" SITE "R37C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.22.THE_CHANNEL/THE_FF/FFregs" SITE "R37C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.22.THE_CHANNEL/THE_FFF/FFregs" SITE "R37C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.22.THE_CHANNEL/THE_FF2/FFregs2" SITE "R37C8D";
+# PROHIBIT SITE "R37C3B";
+# PROHIBIT SITE "R37C3C";
+# PROHIBIT SITE "R37C4B";
+# PROHIBIT SITE "R37C4C";
+# PROHIBIT SITE "R37C6B";
+# PROHIBIT SITE "R37C6C";
+# PROHIBIT SITE "R37C7B";
+# PROHIBIT SITE "R37C7C";
+PROHIBIT SITE "R37C5C";
+# PROHIBIT SITE "R37C5B";
+# PROHIBIT SITE "R37C5D";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.23.THE_CHANNEL/THE_INP/InpLut" SITE "R35C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.23.THE_CHANNEL/THE_FF/FFregs" SITE "R35C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.23.THE_CHANNEL/THE_FFF/FFregs" SITE "R35C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.23.THE_CHANNEL/THE_FF2/FFregs2" SITE "R35C8D";
+# PROHIBIT SITE "R35C3B";
+# PROHIBIT SITE "R35C3C";
+# PROHIBIT SITE "R35C4B";
+# PROHIBIT SITE "R35C4C";
+# PROHIBIT SITE "R35C6B";
+# PROHIBIT SITE "R35C6C";
+# PROHIBIT SITE "R35C7B";
+# PROHIBIT SITE "R35C7C";
+PROHIBIT SITE "R35C5C";
+# PROHIBIT SITE "R35C5B";
+# PROHIBIT SITE "R35C5D";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.24.THE_CHANNEL/THE_INP/InpLut" SITE "R11C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.24.THE_CHANNEL/THE_FF/FFregs" SITE "R11C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.24.THE_CHANNEL/THE_FFF/FFregs" SITE "R11C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.24.THE_CHANNEL/THE_FF2/FFregs2" SITE "R11C8D";
+# PROHIBIT SITE "R11C3B";
+# PROHIBIT SITE "R11C3C";
+# PROHIBIT SITE "R11C4B";
+# PROHIBIT SITE "R11C4C";
+# PROHIBIT SITE "R11C6B";
+# PROHIBIT SITE "R11C6C";
+# PROHIBIT SITE "R11C7B";
+# PROHIBIT SITE "R11C7C";
+PROHIBIT SITE "R11C5C";
+# PROHIBIT SITE "R11C5B";
+# PROHIBIT SITE "R11C5D";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.25.THE_CHANNEL/THE_INP/InpLut" SITE "R8C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.25.THE_CHANNEL/THE_FF/FFregs" SITE "R8C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.25.THE_CHANNEL/THE_FFF/FFregs" SITE "R8C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.25.THE_CHANNEL/THE_FF2/FFregs2" SITE "R8C8D";
+# PROHIBIT SITE "R8C3B";
+# PROHIBIT SITE "R8C3C";
+# PROHIBIT SITE "R8C4B";
+# PROHIBIT SITE "R8C4C";
+# PROHIBIT SITE "R8C6B";
+# PROHIBIT SITE "R8C6C";
+# PROHIBIT SITE "R8C7B";
+# PROHIBIT SITE "R8C7C";
+PROHIBIT SITE "R8C5C";
+# PROHIBIT SITE "R8C5B";
+# PROHIBIT SITE "R8C5D";
+
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.26.THE_CHANNEL/THE_INP/InpLut" SITE "R32C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.26.THE_CHANNEL/THE_FF/FFregs" SITE "R32C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.26.THE_CHANNEL/THE_FFF/FFregs" SITE "R32C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.26.THE_CHANNEL/THE_FF2/FFregs2" SITE "R32C8D";
+# PROHIBIT SITE "R32C3B";
+# PROHIBIT SITE "R32C3C";
+# PROHIBIT SITE "R32C4B";
+# PROHIBIT SITE "R32C4C";
+# PROHIBIT SITE "R32C6B";
+# PROHIBIT SITE "R32C6C";
+# PROHIBIT SITE "R32C7B";
+# PROHIBIT SITE "R32C7C";
+PROHIBIT SITE "R32C5C";
+# PROHIBIT SITE "R32C5B";
+# PROHIBIT SITE "R32C5D";
+
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.27.THE_CHANNEL/THE_INP/InpLut" SITE "R14C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.27.THE_CHANNEL/THE_FF/FFregs" SITE "R14C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.27.THE_CHANNEL/THE_FFF/FFregs" SITE "R14C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.27.THE_CHANNEL/THE_FF2/FFregs2" SITE "R14C8D";
+# PROHIBIT SITE "R14C3B";
+# PROHIBIT SITE "R14C3C";
+# PROHIBIT SITE "R14C4B";
+# PROHIBIT SITE "R14C4C";
+# PROHIBIT SITE "R14C6B";
+# PROHIBIT SITE "R14C6C";
+# PROHIBIT SITE "R14C7B";
+# PROHIBIT SITE "R14C7C";
+PROHIBIT SITE "R14C5C";
+# PROHIBIT SITE "R14C5B";
+# PROHIBIT SITE "R14C5D";
+
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.28.THE_CHANNEL/THE_INP/InpLut" SITE "R26C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.28.THE_CHANNEL/THE_FF/FFregs" SITE "R26C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.28.THE_CHANNEL/THE_FFF/FFregs" SITE "R26C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.28.THE_CHANNEL/THE_FF2/FFregs2" SITE "R26C8D";
+# PROHIBIT SITE "R26C3B";
+# PROHIBIT SITE "R26C3C";
+# PROHIBIT SITE "R26C4B";
+# PROHIBIT SITE "R26C4C";
+# PROHIBIT SITE "R26C6B";
+# PROHIBIT SITE "R26C6C";
+# PROHIBIT SITE "R26C7B";
+# PROHIBIT SITE "R26C7C";
+PROHIBIT SITE "R26C5C";
+# PROHIBIT SITE "R26C5B";
+# PROHIBIT SITE "R26C5D";
+
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.29.THE_CHANNEL/THE_INP/InpLut" SITE "R16C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.29.THE_CHANNEL/THE_FF/FFregs" SITE "R16C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.29.THE_CHANNEL/THE_FFF/FFregs" SITE "R16C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.29.THE_CHANNEL/THE_FF2/FFregs2" SITE "R16C8D";
+# PROHIBIT SITE "R16C3B";
+# PROHIBIT SITE "R16C3C";
+# PROHIBIT SITE "R16C4B";
+# PROHIBIT SITE "R16C4C";
+# PROHIBIT SITE "R16C6B";
+# PROHIBIT SITE "R16C6C";
+# PROHIBIT SITE "R16C7B";
+# PROHIBIT SITE "R16C7C";
+PROHIBIT SITE "R16C5C";
+# PROHIBIT SITE "R16C5B";
+# PROHIBIT SITE "R16C5D";
+
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.30.THE_CHANNEL/THE_INP/InpLut" SITE "R18C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.30.THE_CHANNEL/THE_FF/FFregs" SITE "R18C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.30.THE_CHANNEL/THE_FFF/FFregs" SITE "R18C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.30.THE_CHANNEL/THE_FF2/FFregs2" SITE "R18C8D";
+# PROHIBIT SITE "R18C3B";
+# PROHIBIT SITE "R18C3C";
+# PROHIBIT SITE "R18C4B";
+# PROHIBIT SITE "R18C4C";
+# PROHIBIT SITE "R18C6B";
+# PROHIBIT SITE "R18C6C";
+# PROHIBIT SITE "R18C7B";
+# PROHIBIT SITE "R18C7C";
+PROHIBIT SITE "R18C5C";
+# PROHIBIT SITE "R18C5B";
+# PROHIBIT SITE "R18C5D";
+
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.31.THE_CHANNEL/THE_INP/InpLut" SITE "R23C5D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.31.THE_CHANNEL/THE_FF/FFregs" SITE "R23C6D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.31.THE_CHANNEL/THE_FFF/FFregs" SITE "R23C3D" ;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.31.THE_CHANNEL/THE_FF2/FFregs2" SITE "R23C8D";
+# PROHIBIT SITE "R23C3B";
+# PROHIBIT SITE "R23C3C";
+# PROHIBIT SITE "R23C4B";
+# PROHIBIT SITE "R23C4C";
+# PROHIBIT SITE "R23C6B";
+# PROHIBIT SITE "R23C6C";
+# PROHIBIT SITE "R23C7B";
+# PROHIBIT SITE "R23C7C";
+PROHIBIT SITE "R23C5C";
+# PROHIBIT SITE "R23C5B";
+# PROHIBIT SITE "R23C5D";
+
+LOCATE UGROUP "THE_TDC/THE_REF_CHANNEL/THE_INP/InpLut" SITE "R12C86D" ;
+LOCATE UGROUP "THE_TDC/THE_REF_CHANNEL/THE_FF/FFregs" SITE "R12C84D" ;
+LOCATE UGROUP "THE_TDC/THE_REF_CHANNEL/THE_FFF/FFregs" SITE "R12C87D" ;
+LOCATE UGROUP "THE_TDC/THE_REF_CHANNEL/THE_FF2/FFregs2" SITE "R12C82D";##
+
+# REGION "TDCLEFT" "R2C16D" 68 4;
+# PROHIBIT REGION "TDCLEFT";
+# REGION "TDCRIGHT" "R2C68D" 68 4;
+# PROHIBIT REGION "TDCRIGHT";
+
+REGION "DECODERLEFT" "R9C2D" 60 10;
+REGION "DECODERRIGHT" "R7C78D" 60 10;
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.16.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.17.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.18.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.19.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.20.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.21.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.22.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.23.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.24.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.25.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.26.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.27.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.28.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.29.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.30.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.31.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERLEFT";
+
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.0.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.1.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.2.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.3.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.4.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.5.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.6.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.7.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.8.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.9.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.10.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.11.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.12.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.13.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.14.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
+LOCATE UGROUP "THE_TDC/gen_CHANNELS.15.THE_CHANNEL/THE_DECODER/Decoder" REGION "DECODERRIGHT";
--- /dev/null
+
+# implementation: "workdir"
+impl -add workdir -type fpga
+
+# device options
+set_option -technology ECP5UM
+set_option -part LFE5UM_45F
+set_option -package BG381C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -top_module "mdctdc"
+set_option -resource_sharing false
+set_option -vhdl2008 true
+
+# map options
+set_option -frequency 120
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 1
+set_option -pipe 1
+set_option -forcegsr false
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -compiler_compatible true
+set_option -multi_file_compilation_unit 1
+
+set_option -max_parallel_jobs 3
+#set_option -automatic_compile_point 1
+#set_option -continue_on_error 1
+set_option -resolve_multiple_driver 1
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+# set result format/file last
+project -result_format "edif"
+project -result_file "workdir/mdctdc.edf"
+set_option log_file "workdir/mdctdc.srf"
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
+
+####################
+
+#Packages
+add_file -vhdl -lib work "workdir/version.vhd"
+add_file -vhdl -lib work "config.vhd"
+add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+
+#Basic Infrastructure
+add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd"
+add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd"
+
+
+#Fifos
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32_oreg/fifo_36x32_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32/fifo_36x32.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_dualport_oreg/fifo_36x512_dualport_oreg.vhd"
+
+#Flash & Reload, Tools
+add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+
+#SlowControl files
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
+
+#Media interface
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd"
+
+
+#########################################
+#channel 0, backplane
+#add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd"
+#add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v"
+
+#channel 1, SFP
+#add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd"
+#add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v"
+##########################################
+
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd"
+add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v"
+
+#TrbNet Endpoint
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd"
+
+add_file -vhdl -lib work "../../clocked_tdc/code/clocked_tdc_pkg.vhd"
+add_file -vhdl -lib work "../cores/PLL_TDC/PLL_TDC.vhd"
+add_file -vhdl -lib work "../../clocked_tdc/code/TDC_FF.vhd"
+add_file -vhdl -lib work "../../clocked_tdc/code/ChannelRegs.vhd"
+add_file -vhdl -lib work "../../clocked_tdc/code/FFregs.vhd"
+add_file -vhdl -lib work "../../clocked_tdc/code/FFregs2.vhd"
+add_file -vhdl -lib work "../../clocked_tdc/code/InpLut.vhd"
+add_file -vhdl -lib work "../../clocked_tdc/code/Decoder.vhd"
+add_file -vhdl -lib work "../../clocked_tdc/code/HitBuffer.vhd"
+add_file -vhdl -lib work "../../clocked_tdc/code/ReadoutHandler.vhd"
+
+
+
+add_file -vhdl -lib work "./mdctdc.vhd"
+#add_file -fpga_constraint "./synplify.fdc"
+
+
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.version.all;
+use work.config.all;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.med_sync_define.all;
+
+entity mdctdc is
+ port(
+ CLK : in std_logic;
+ CLK_TDC : in std_logic;
+ TRG : in std_logic; --Reference Time
+
+ GPIO : inout std_logic_vector(3 downto 0); --0: Serdes out, 1: Serdes in, 2,3: trigger output 0+1
+ LVDS : in std_logic_vector(1 downto 0);
+
+ OUTP : in std_logic_vector(31 downto 0);
+ TEST : out std_logic_vector(3 downto 0);
+ INJ : out std_logic_vector(3 downto 0);
+ PTEN : out std_logic_vector(2 downto 1);
+
+ RSTN : out std_logic_vector(2 downto 1);
+ MISO : in std_logic_vector(2 downto 1);
+ MOSI : out std_logic_vector(2 downto 1);
+ SCK : out std_logic_vector(2 downto 1);
+ --Flash, Reload
+ FLASH_SCLK : out std_logic;
+ FLASH_CS : out std_logic;
+ FLASH_MOSI : out std_logic;
+ FLASH_MISO : in std_logic;
+ FLASH_HOLD : out std_logic;
+ FLASH_WP : out std_logic;
+ FLASH_SELECT : in std_logic;
+ FLASH_OVERRIDE : out std_logic;
+ PROGRAMN : out std_logic;
+
+ --I2C
+ I2C_SDA : inout std_logic;
+ I2C_SCL : inout std_logic;
+
+ --LED
+ LED : out std_logic_vector(2 downto 0)
+
+ --Other Connectors
+ );
+
+
+ attribute syn_useioff : boolean;
+ attribute syn_useioff of FLASH_CS : signal is true;
+ attribute syn_useioff of FLASH_SCLK : signal is true;
+ attribute syn_useioff of FLASH_MOSI : signal is true;
+ attribute syn_useioff of FLASH_MISO : signal is true;
+ attribute syn_useioff of OUTP : signal is false;
+
+
+end entity;
+
+architecture arch of mdctdc is
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ signal clk_sys, clk_full, clk_full_osc : std_logic;
+ signal GSR_N : std_logic;
+ signal reset_i : std_logic;
+ signal clear_i : std_logic;
+
+ --Media Interface
+ signal med2int : med2int_array_t(0 to 0);
+ signal int2med : int2med_array_t(0 to 0);
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
+ signal additional_reg : std_logic_vector ( 31 downto 0);
+
+
+ signal readout_rx : READOUT_RX;
+ signal readout_tx : readout_tx_array_t(0 to 1);
+
+ signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, bus_master_in : CTRLBUS_TX;
+ signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, bus_master_out : CTRLBUS_RX;
+
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+
+ signal sed_error_i : std_logic;
+ signal bus_master_active : std_logic;
+
+ signal timer : TIMERS;
+ signal led_off : std_logic;
+ --TDC
+ signal hit_in_i : std_logic_vector(31 downto 0);
+ signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0);
+ signal trigger_inputs_i : std_logic_vector(TRIG_GEN_INPUT_NUM-1 downto 0);
+ signal calibration_pulse: std_logic;
+
+ signal dummy_i : std_logic;
+
+begin
+
+---------------------------------------------------------------------------
+-- Clock & Reset Handling
+---------------------------------------------------------------------------
+ THE_CLOCK_RESET : entity work.clock_reset_handler
+ port map(
+ CLOCK_IN => CLK,
+ RESET_FROM_NET => med2int(0).stat_op(13),
+ SEND_RESET_IN => med2int(0).stat_op(15),
+
+ BUS_RX => bustc_rx,
+ BUS_TX => bustc_tx,
+
+ RESET_OUT => reset_i,
+ CLEAR_OUT => clear_i,
+ GSR_OUT => GSR_N,
+
+ REF_CLK_OUT => clk_full,
+ SYS_CLK_OUT => clk_sys,
+ RAW_CLK_OUT => clk_full_osc,
+
+ DEBUG_OUT => open
+ );
+
+
+---------------------------------------------------------------------------
+-- TrbNet Uplink
+---------------------------------------------------------------------------
+
+ THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync
+ generic map(
+ SERDES_NUM => 0,
+ IS_SYNC_SLAVE => c_YES
+ )
+ port map(
+ CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full,
+ CLK_INTERNAL_FULL => clk_full_osc,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ --Internal Connection
+ MEDIA_MED2INT => med2int(0),
+ MEDIA_INT2MED => int2med(0),
+
+ --Sync operation
+ RX_DLM => open,
+ RX_DLM_WORD => open,
+ TX_DLM => open,
+ TX_DLM_WORD => open,
+
+ --SFP Connection
+ SD_PRSNT_N_IN => GPIO(0),
+ SD_LOS_IN => GPIO(0),
+ SD_TXDIS_OUT => GPIO(1),
+ --Control Interface
+ BUS_RX => bussci_rx,
+ BUS_TX => bussci_tx,
+ -- Status and control port
+ STAT_DEBUG => med_stat_debug(63 downto 0),
+ CTRL_DEBUG => open
+ );
+
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
+ generic map (
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"FF",
+ REGIO_INIT_ENDPOINT_ID => x"0001",
+ REGIO_USE_1WIRE_INTERFACE => c_I2C,
+ TIMING_TRIGGER_RAW => c_YES,
+ --Configure data handler
+ DATA_INTERFACE_NUMBER => 2,
+ DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE,
+ DATA_BUFFER_WIDTH => 32,
+ DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE,
+ TRG_RELEASE_AFTER_DATA => c_YES,
+ HEADER_BUFFER_DEPTH => 9,
+ HEADER_BUFFER_FULL_THRESH => 2**9-16
+ )
+
+ port map(
+ -- Misc
+ CLK => clk_sys,
+ RESET => reset_i,
+ CLK_EN => '1',
+
+ -- Media direction port
+ MEDIA_MED2INT => med2int(0),
+ MEDIA_INT2MED => int2med(0),
+
+ --Timing trigger in
+ TRG_TIMING_TRG_RECEIVED_IN => TRG,
+
+ READOUT_RX => readout_rx,
+ READOUT_TX => readout_tx,
+
+ --Slow Control Port
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
+ BUS_RX => ctrlbus_rx,
+ BUS_TX => ctrlbus_tx,
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+
+ ONEWIRE_INOUT => open,
+ I2C_SCL => I2C_SCL,
+ I2C_SDA => I2C_SDA,
+ --Timing registers
+ TIMERS_OUT => timer
+ );
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+
+
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
+ generic map(
+ PORT_NUMBER => 3,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"a000", 3 => x"c000", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 9, 3 => 12, others => 0),
+ PORT_MASK_ENABLE => 1
+ )
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+
+ REGIO_RX => ctrlbus_rx,
+ REGIO_TX => ctrlbus_tx,
+
+ BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
+ BUS_RX(1) => bussci_rx, --SCI Serdes
+ BUS_RX(2) => busspi_rx,
+ BUS_RX(3) => bustdc_rx, --Clock switch
+ BUS_TX(0) => bustools_tx,
+ BUS_TX(1) => bussci_tx,
+ BUS_TX(2) => busspi_tx,
+ BUS_TX(3) => bustdc_tx,
+
+ STAT_DEBUG => open
+ );
+
+---------------------------------------------------------------------------
+-- Control Tools
+---------------------------------------------------------------------------
+ THE_TOOLS : entity work.trb3sc_tools
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+
+ --Flash & Reload
+ FLASH_CS => FLASH_CS,
+ FLASH_CLK => FLASH_SCLK,
+ FLASH_IN => FLASH_MISO,
+ FLASH_OUT => FLASH_MOSI,
+ PROGRAMN => PROGRAMN,
+ REBOOT_IN => common_ctrl_reg(15),
+ --SPI
+-- SPI_CS_OUT(1 downto 0) => RSTN,
+-- SPI_MOSI_OUT(1 downto 0) => MOSI,
+-- SPI_MISO_IN(1 downto 0) => MISO,
+-- SPI_CLK_OUT(1 downto 0) => SCK,
+ --Header
+ HEADER_IO => open,
+ ADDITIONAL_REG => additional_reg,
+
+ --LCD
+ LCD_DATA_IN => (others => '0'),
+ --ADC
+ ADC_CS => open,
+ ADC_MOSI => open,
+ ADC_MISO => open,
+ ADC_CLK => open,
+ --Trigger & Monitor
+ MONITOR_INPUTS => monitor_inputs_i,
+ TRIG_GEN_INPUTS => trigger_inputs_i,
+ TRIG_GEN_OUTPUTS(1 downto 0) => GPIO(3 downto 2),
+ --SED
+ SED_ERROR_OUT => sed_error_i,
+ --Slowcontrol
+ BUS_RX => bustools_rx,
+ BUS_TX => bustools_tx,
+ --Control master for default settings
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+ DEBUG_OUT => open
+ );
+
+ FLASH_HOLD <= '1';
+ FLASH_WP <= '1';
+
+ led_off <= additional_reg(0);
+ FLASH_OVERRIDE <= not additional_reg(1);
+
+---------------------------------------------------------------------------
+-- I/O
+---------------------------------------------------------------------------
+ monitor_inputs_i <= OUTP(MONITOR_INPUT_NUM-1 downto 0);
+ trigger_inputs_i <= OUTP(TRIG_GEN_INPUT_NUM-1 downto 0);
+ hit_in_i <= OUTP;
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+ LED(0) <= (med2int(0).stat_op(10) or med2int(0).stat_op(11)) and not led_off;
+ LED(1) <= med2int(0).stat_op(9) and not led_off;
+ LED(2) <= (LVDS(1) or LVDS(0) or dummy_i or FLASH_SELECT) and not led_off;
+
+
+--------------------------------------------------------------------------
+-- Controls
+---------------------------------------------------------------------------
+ PTEN <= "11";
+ INJ <= additional_reg(19 downto 16); --"0000";
+ TEST <= additional_reg(27 downto 24) or (calibration_pulse & calibration_pulse & calibration_pulse & calibration_pulse); --"0000";
+
+
+-------------------------------------------------------------------------------
+-- TDC
+-------------------------------------------------------------------------------
+-- THE_TDC : entity work.TDC_FF
+--
+-- port map(
+-- CLK_FAST => CLK_TDC,
+-- CLK_SYS => clk_sys,
+-- RESET_IN => reset_i,
+-- SIGNAL_IN => hit_in_i(31 downto 0),
+-- TRIGGER_IN => TRG,
+-- CALIBRATION_OUT => calibration_pulse,
+--
+-- BUS_RX => bustdc_rx,
+-- BUS_TX => bustdc_tx,
+--
+-- READOUT_RX => readout_rx,
+-- READOUT_TX => readout_tx(0 to 1),
+--
+-- DUMMY => dummy_i
+--
+-- );
+
+-------------------------------------------------------------------------------
+-- THE automatic SPI
+-------------------------------------------------------------------------------
+-- THE_SPI : entity work.pasttrec_spi
+-- port map(
+--
+-- );
+
+-- RSTN : out std_logic_vector(1 downto 0);
+-- MISO : in std_logic_vector(1 downto 0);
+-- MOSI : out std_logic_vector(1 downto 0);
+-- SCK : out std_logic_vector(1 downto 0);
+
+
+
+-------------------------------------------------------------------------------
+-- No trigger/data endpoint included
+-------------------------------------------------------------------------------
+readout_tx(0).data_finished <= '1';
+readout_tx(0).data_write <= '0';
+readout_tx(0).busy_release <= '1';
+readout_tx(1).data_finished <= '1';
+readout_tx(1).data_write <= '0';
+readout_tx(1).busy_release <= '1';
+end architecture;
+
+
+
--- /dev/null
+-w
+#-y
+-l 5
+#-m nodelist.txt # Controlled by the compile.pl script.
+#-n 1 # Controlled by the compile.pl script.
+-s 10
+-t 2
+-c 2
+-e 2
+-i 10
+#-exp parPlcInLimit=0
+#-exp parPlcInNeighborSize=1
+#General PAR Command Line Options
+# -w With this option, any files generated will overwrite existing files
+# (e.g., any .par, .pad files).
+# -y Adds the Delay Summary Report in the .par file and creates the delay
+# file (in .dly format) at the end of the par run.
+#
+#PAR Placement Command Line Options
+# -l Specifies the effort level of the design from 1 (simplest designs)
+# to 5 (most complex designs).
+# -m Multi-tasking option. Controlled by the compile.pl script.
+# -n Sets the number of iterations performed at the effort level
+# specified by the -l option. Controlled by the compile.pl script.
+# -s Save the number of best results for this run.
+# -t Start placement at the specified cost table. Default is 1.
+#
+#PAR Routing Command Line Options
+# -c Run number of cost-based cleanup passes of the router.
+# -e Run number of delay-based cleanup passes of the router on
+# completely-routed designs only.
+# -i Run a maximum number of passes, stopping earlier only if the routing
+# goes to 100 percent completion and all constraints are met.
+#
+#PAR Explorer Command Line Options
+# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is
+# compatible with all Lattice FPGA device families; however, most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families.
+# parCDR Enable the congestion-driven router (CDR) algorithm.
+# Congestion-driven options like parCDR and parCDP can improve
+# performance given a design with multiple congestion “hotspots.” The
+# Layer > Congestion option of the Design Planner Floorplan View can
+# help visualize routing congestion. Large congested areas may prevent
+# the options from finding a successful solution.
+# CDR is compatible with all Lattice FPGA device families however most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families.
+# paruseNBR NBR Router or Negotiation-based routing option. Supports all
+# FPGA device families except LatticeXP and MachXO.
+# When turned on, an alternate routing engine from the traditional
+# Rip-up-based routing selection (RBR) is used. This involves an
+# iterative routing algorithm that routes connections to achieve
+# minimum delay cost. It does so by computing the demand on each
+# routing resource and applying cost values per node. It will
+# complete when an optimal solution is arrived at or the number of
+# iterations is reached.
+# parPathBased Path-based placement option. Path-based timing driven
+# placement will yield better performance and more
+# predictable results in many cases.
+# parHold Additional hold time correction option. This option
+# forces the router to automatically insert extra wires to compensate for the
+# hold time violation.
+# parHoldLimit This option allows you to set a limit on the number of
+# hold time violations to be processed by the auto hold time correction option
+# parHold.
+# parPlcInLimit Cannot find in the online help
+# parPlcInNeighborSize Cannot find in the online help
+-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.2" title="mdctdc" device="LFE5UM-45F-8BG381C" default_implementation="mdctdc">
+ <Options/>
+ <Implementation title="mdctdc" dir="mdctdc" description="Automatically generated implemenatation" synthesis="synplify" default_strategy="Strategy1">
+ <Options def_top="mdctdc" top="mdctdc"/>
+ <Source name="../workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" type="VHDL" type_short="VHDL">
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+ </Source>
+ <Source name="../workdir/version.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
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+ </Source>
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+ </Source>
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+ </Source>
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+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../dirich/cores/pll_240_100/pll_240_100.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../dirich/code/clock_reset_handler.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../vhdlbasics/ecp5/sedcheck.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
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+ </Source>
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+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
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+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
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+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
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+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
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+ <Options lib="work"/>
+ </Source>
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+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/slv_register.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trb3sc/code/trb3sc_tools.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
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+ <Options lib="work"/>
+ </Source>
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+ <Options lib="work"/>
+ </Source>
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+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/uart_rec.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/uart_trans.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trbnet/optical_link/f_divider.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trb3sc/code/load_settings.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trb3sc/code/spi_master_generic.vhd" type="VHDL" type_short="VHDL">
+ <Options lib="work"/>
+ </Source>
+ <Source name="../../../trb3/base/code/input_to_trigger_logic_record.vhd" type="VHDL" type_short="VHDL">
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+ </Source>
+ <Source name="../../../trb3/base/code/input_statistics.vhd" type="VHDL" type_short="VHDL">
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+ </Source>
+ <Source name="../../../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
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+ <Options lib="work"/>
+ </Source>
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+ <Options lib="work"/>
+ </Source>
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+ <Options lib="work"/>
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+ <Options/>
+ </Source>
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+ </Source>
+ <Source name="../../../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
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+ <Source name="untitled.lpf" type="Logic Preference" type_short="LPF" excluded="TRUE">
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+ <Source name="../workdir/mdctdc.lpf" type="Logic Preference" type_short="LPF">
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+ </Implementation>
+ <Strategy name="Strategy1" file="auto_strat.sty"/>
+</BaliProject>
jspc29 / mdcupgrade.git / commitdiff