few more minor changes

diff --git a/daqstartup.tex b/daqstartup.tex
index 71d4f930ca7b7be5263ca8acba8c08608b965983..0bd11a2efb19b08a61c6495c1e2352817b68d5d0 100755 (executable)
--- a/daqstartup.tex
+++ b/daqstartup.tex
@@ -130,9 +130,9 @@ The most common operation is to load some settings to registers on the FPGA. In
 
 The first part of the file lists the register addresses the data has to be written to. As you can see, in this case to different sets of registers do exist, marked with the type number. Depending on the type there might be a different number of registers.
 
-The second part lists the values for each endpoint individually: The first entry is the network address of the endpoint, the second one is the register set to use as listed in the first table. Then an appropriate number of values (max. 32bits each as defined by TrbNet) follows.
+The second part lists the values for each endpoint individually: The first entry is the network address of the endpoint, the second one is the register set to use as listed in the first table. Then an appropriate number of values (32bits each as defined by TrbNet) follows.
 
-Both tables is preceded by a marker (either ``!Register'' or ``!Value``) using ''!`` as an escape character to mark the start of the tables for the parser.
+Both tables are preceded by a marker (either ``!Register'' or ``!Value``)to mark the start of the tables for the parser.
 
 \subsection{Trbcmd Scripts}
 \label{daqtrbcmd}

diff --git a/trb3/FlashSettings.tex b/trb3/FlashSettings.tex
new file mode 100644 (file)
index 0000000..98d18f7
--- /dev/null
+++ b/trb3/FlashSettings.tex
@@ -0,0 +1,7 @@
+\section{Settings Stored in Flash}
+
+Most registers settings that need to be done during the start-up of a system can also be stored in the on-board Flash memory and  loaded automatically with each reload or reset of the FPGA. This allows a mostly automatic restart of the system without the need to load many settings, which might take a while in a large system.
+
+
+This features is only available for register addresses above 0x1000 and for register accesses that don't have any special timing requirements. See \verb!daqtools/tools/flashsettings.pl! for details. 
+

diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex
index 6b5cba0eebf10f476daa7fc4d11176060e7fb9c6..b3315cb96439f26231fd9b998bf8a85401b11bfe 100644 (file)
--- a/trb3/Trb3GeneralRemarks.tex
+++ b/trb3/Trb3GeneralRemarks.tex
@@ -195,7 +195,6 @@ The initial address set with \signal{Regio\_Init\_Address} can be chosen in the
 \begin{itemize*}
  \item 0xF300 for the central FPGA
  \item 0xF305 for the peripheral FPGA
- \item 0xF30n for a design for FPGA n only
  \item 0xF3C0 a design with CTS
  \item 0xF3CC slave TRB3sc
  \item 0xF3CD TRB3sc with hub AddOn

diff --git a/trb3/Trb3scBasics.tex b/trb3/Trb3scBasics.tex
index dd1073a35d9715ac535443f9315afa07e5dc2afc..448a0b44fff6166f4188c0dc3995b0d14c3ee5c1 100644 (file)
--- a/trb3/Trb3scBasics.tex
+++ b/trb3/Trb3scBasics.tex
@@ -59,8 +59,8 @@ HDR\_IO is available for any general purpose I/O. All lines are LVCMOS25. By def
   4 & SPI MISO\\
   5 & SPI CLK\\
   6 & SPI CE\\
-  7 & (LCD DC)\\
-  8 & (LCD Reset)\\
+  7 & I2C SDA\\
+  8 & I2C SCL\\
   9 & \\
   10 & \\
   11 & 3.3V\\

diff --git a/trb3/main.tex b/trb3/main.tex
index e1e9d7cfca7dc1ed0217b376bbc2141df89aa6f0..458656989710fc900bb931637a85731a8b509c7b 100644 (file)
--- a/trb3/main.tex
+++ b/trb3/main.tex
@@ -219,6 +219,8 @@
   \input{AdditionalModules}
   \clearpage
   \input{TriggerModule}      
+  \clearpage
+  \input{FlashSettings}      
 
   \clearpage
   \section{GbE Data Read-out}