Add sources/remove last remaining nxyter lines

diff --git a/mupix/trb3_periph.prj b/mupix/trb3_periph.prj
index 65669a647aa21689859975fe5399f5c483be7ac9..f011bfe73f3edd1ae8173d2f2123a4de686f9e63 100644 (file)
--- a/mupix/trb3_periph.prj
+++ b/mupix/trb3_periph.prj
@@ -140,4 +140,19 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.v
 add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
 
 
-
+#MuPix Files
+add_file -vhdl -lib "work" "trb3_periph.vhd"
+
+add_file -vhdl -lib "work" "sources/mupix_components.vhd"
+add_file -vhdl -lib "work" "sources/BlockMemory.vhd"
+add_file -vhdl -lib "work" "sources/EventBuffer.vhd"
+add_file -vhdl -lib "work" "sources/graycounter.vhd"
+add_file -vhdl -lib "work" "sources/Histogram.vhd"
+add_file -vhdl -lib "work" "sources/HitbusHistogram.vhd"
+add_file -vhdl -lib "work" "sources/injection_generator.vhd"
+add_file -vhdl -lib "work" "sources/MuPix3_board.vhd"
+add_file -vhdl -lib "work" "sources/MuPix3_interface.vhd"
+add_file -vhdl -lib "work" "sources/MuPix3_PixCtr.vhd"
+add_file -vhdl -lib "work" "sources/spi_if.vhd"
+
+add_file -vhdl -lib "work" "cores/fifo_32_data.vhd"

diff --git a/mupix/trb3_periph.vhd b/mupix/trb3_periph.vhd
index f5487c22d6939942974e489a5cc72cca3a32e3c9..2728a801268a5d2b8ffbd43ab2f152b0db81224f 100644 (file)
--- a/mupix/trb3_periph.vhd
+++ b/mupix/trb3_periph.vhd
@@ -13,7 +13,7 @@ use work.trb_net_std.all;
 use work.trb_net_components.all;
 use work.trb3_components.all;
 use work.version.all;
-use work.nxyter_components.all;
+use work.mupix_components.all;
 
 library ecp3;
 use ecp3.components.all;
@@ -113,9 +113,6 @@ entity trb3_periph is
   attribute syn_useioff of FPGA5_COMM       : signal is true;
   attribute syn_useioff of TEST_LINE        : signal is true;
   --attribute syn_useioff of INP           : signal is false;
-  attribute syn_useioff of NX1_TIMESTAMP_IN : signal is true;
-  attribute syn_useioff of NX2_TIMESTAMP_IN : signal is true;
-  --attribute syn_useioff of NX1_ADC_NX_IN   : signal is true;
   --attribute syn_useioff of DAC_SDO       : signal is true;
   --attribute syn_useioff of DAC_SDI       : signal is true;
   --attribute syn_useioff of DAC_SCK       : signal is true;
@@ -684,28 +681,5 @@ begin
       );
 
 
-  -----------------------------------------------------------------------------
-  -- MuPix common Clocks
-  -----------------------------------------------------------------------------
-  pll_nx_clk256_1 : entity work.pll_nx_clk256
-    port map (
-      CLK   => clk_100_i,
-      CLKOP => nx_clk256,
-      LOCK  => pll_lock_clk256
-      );
-
-  NX1_CLK256A_OUT <= nx_clk256;
-  NX2_CLK256A_OUT <= nx_clk256;
-
-  -- ADC Receiver Clock
-  pll_adc_clk192_1 : pll_adc_clk192
-    port map (
-      CLK   => CLK_PCLK_LEFT,
-      CLKOP => clk_adc_dat,
-      LOCK  => clk_adc_dat_lock
-      );
-
- 
-
 
 end architecture;