a working system although this should be the way (according to docs).
Situatiuon: trb is running on oscillator clocks (!!) soda is running on rx_full_clk.
This gives a working trbnet (with errors) but I'm amazed that it works at all.
MED_PACKET_NUM_OUT : out t_HUB_NUM; -- std_logic_vector(4*c_NUM_WIDTH-1 downto 0) := (others => '0');
MED_DATAREADY_OUT : out std_logic_vector(3 downto 0) := (others => '0');
MED_READ_IN : in std_logic_vector(3 downto 0);
- CLK_RX_HALF_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
- CLK_RX_FULL_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
- CLK_TX_HALF_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
- CLK_TX_FULL_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
+ RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
+ RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
+ TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
+ TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
--Sync operation
RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
signal clk_200_txdata : std_logic;
signal clk_200_rxdn : std_logic_vector(3 downto 0);
signal clk_200_i : std_logic_vector(3 downto 0);
-signal clk_rx_full : std_logic_vector(3 downto 0);
-signal clk_rx_half : std_logic_vector(3 downto 0);
-signal clk_tx_full : std_logic_vector(3 downto 0);
-signal clk_tx_half : std_logic_vector(3 downto 0);
+signal rx_full_clk : std_logic_vector(3 downto 0);
+signal rx_half_clk : std_logic_vector(3 downto 0);
+signal tx_full_clk : std_logic_vector(3 downto 0);
+signal tx_half_clk : std_logic_vector(3 downto 0);
signal tx_data : t_HUB_BYTE; --std_logic_vector(4*8-1 downto 0);
signal tx_k : std_logic_vector(3 downto 0);
rst(i) <= (CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i));
rst_n(i) <= not(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i));
- CLK_RX_HALF_OUT(i) <= clk_rx_half(i);
- CLK_RX_FULL_OUT(i) <= clk_rx_full(i);
- CLK_TX_HALF_OUT(i) <= clk_tx_half(i);
- CLK_TX_FULL_OUT(i) <= clk_tx_full(i);
+ RX_HALF_CLK_OUT(i) <= rx_half_clk(i);
+ RX_FULL_CLK_OUT(i) <= rx_full_clk(i);
+ TX_HALF_CLK_OUT(i) <= tx_half_clk(i);
+ TX_FULL_CLK_OUT(i) <= tx_full_clk(i);
-- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate -- NO WAY IN HELL !! this downlink is a master
--- clk_200_i(i) <= clk_rx_full(i);
+-- clk_200_i(i) <= rx_full_clk(i);
-- end generate;
-- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
- clk_200_i(i) <= clk_200_txdata;
- clk_200_rxdn(i) <= clk_rx_full(i); -- These clocks are the rx_full of the DOWNLINKs !!!
+-- clk_200_i(i) <= clk_200_txdata;
+-- clk_200_rxdn(i) <= rx_full_clk(i); -- These clocks are the rx_full of the DOWNLINKs !!!
-- end generate;
end generate;
hdinn_ch0 => SD_RXD_N_IN(0),
hdoutp_ch0 => SD_TXD_P_OUT(0),
hdoutn_ch0 => SD_TXD_N_OUT(0),
- rxiclk_ch0 => clk_200_i(0), --clk_200_txdata,
+ rxiclk_ch0 => clk_200_txdata, --clk_200_i(0),
sci_sel_ch0 => sci_ch_i(0),
txiclk_ch0 => clk_200_txdata,
- rx_full_clk_ch0 => clk_rx_full(0),
- rx_half_clk_ch0 => clk_rx_half(0),
- tx_full_clk_ch0 => clk_tx_full(0),
- tx_half_clk_ch0 => clk_tx_half(0),
+ rx_full_clk_ch0 => rx_full_clk(0),
+ rx_half_clk_ch0 => rx_half_clk(0),
+ tx_full_clk_ch0 => tx_full_clk(0),
+ tx_half_clk_ch0 => tx_half_clk(0),
fpga_rxrefclk_ch0 => clk_200_osc,
txdata_ch0 => tx_data(0),
tx_k_ch0 => tx_k(0),
hdinn_ch1 => SD_RXD_N_IN(1),
hdoutp_ch1 => SD_TXD_P_OUT(1),
hdoutn_ch1 => SD_TXD_N_OUT(1),
- rxiclk_ch1 => clk_200_i(1), --clk_200_txdata,
+ rxiclk_ch1 => clk_200_txdata, --clk_200_i(1),
sci_sel_ch1 => sci_ch_i(1),
txiclk_ch1 => clk_200_txdata,
- rx_full_clk_ch1 => clk_rx_full(1),
- rx_half_clk_ch1 => clk_rx_half(1),
- tx_full_clk_ch1 => clk_tx_full(1),
- tx_half_clk_ch1 => clk_tx_half(1),
+ rx_full_clk_ch1 => rx_full_clk(1),
+ rx_half_clk_ch1 => rx_half_clk(1),
+ tx_full_clk_ch1 => tx_full_clk(1),
+ tx_half_clk_ch1 => tx_half_clk(1),
fpga_rxrefclk_ch1 => clk_200_osc,
txdata_ch1 => tx_data(1),
tx_k_ch1 => tx_k(1),
hdinn_ch2 => SD_RXD_N_IN(2),
hdoutp_ch2 => SD_TXD_P_OUT(2),
hdoutn_ch2 => SD_TXD_N_OUT(2),
- rxiclk_ch2 => clk_200_i(2), --clk_200_txdata,
+ rxiclk_ch2 => clk_200_txdata, --clk_200_i(2),
sci_sel_ch2 => sci_ch_i(2),
txiclk_ch2 => clk_200_txdata,
- rx_full_clk_ch2 => clk_rx_full(2),
- rx_half_clk_ch2 => clk_rx_half(2),
- tx_full_clk_ch2 => clk_tx_full(2),
- tx_half_clk_ch2 => clk_tx_half(2),
+ rx_full_clk_ch2 => rx_full_clk(2),
+ rx_half_clk_ch2 => rx_half_clk(2),
+ tx_full_clk_ch2 => tx_full_clk(2),
+ tx_half_clk_ch2 => tx_half_clk(2),
fpga_rxrefclk_ch2 => clk_200_osc,
txdata_ch2 => tx_data(2),
tx_k_ch2 => tx_k(2),
hdinn_ch3 => SD_RXD_N_IN(3),
hdoutp_ch3 => SD_TXD_P_OUT(3),
hdoutn_ch3 => SD_TXD_N_OUT(3),
- rxiclk_ch3 => clk_200_i(3), --clk_200_txdata,
+ rxiclk_ch3 => clk_200_txdata, --clk_200_i(3),
sci_sel_ch3 => sci_ch_i(3),
txiclk_ch3 => clk_200_txdata,
- rx_full_clk_ch3 => clk_rx_full(3),
- rx_half_clk_ch3 => clk_rx_half(3),
- tx_full_clk_ch3 => clk_tx_full(3),
- tx_half_clk_ch3 => clk_tx_half(3),
+ rx_full_clk_ch3 => rx_full_clk(3),
+ rx_half_clk_ch3 => rx_half_clk(3),
+ tx_full_clk_ch3 => tx_full_clk(3),
+ tx_half_clk_ch3 => tx_half_clk(3),
fpga_rxrefclk_ch3 => clk_200_osc,
txdata_ch3 => tx_data(3),
tx_k_ch3 => tx_k(3),
sci_rd => sci_read_i,
sci_wrn => sci_write_i,
- fpga_txrefclk => clk_200_osc, --clk_200_i(0),
+ fpga_txrefclk => clk_200_txdata, --clk_200_osc, --clk_200_i(0),
tx_serdes_rst_c => '0', --tx_serdes_rst(0), -- resets tx_pll PL 1906
tx_pll_lol_qd_s => tx_pll_lol_quad,
tx_sync_qd_c => '0', -- unused; signal to synchronise channels/serdesses for multi-channel protocols
THE_RX_FSM : rx_reset_fsm
port map(
RST_N => rst_n(i),
- RX_REFCLK => clk_200_osc, -- want de rx_refclk is clk_200_osc !!! en moet er altijd zijn
+ RX_REFCLK => rx_full_clk(i), --clk_200_osc, -- want de rx_refclk is clk_200_osc !!! en moet er altijd zijn
TX_PLL_LOL_QD_S => tx_pll_lol(i),
RX_SERDES_RST_CH_C => rx_serdes_rst(i),
RX_CDR_LOL_CH_S => rx_cdr_lol(i),
THE_TX_FSM : tx_reset_fsm
port map(
RST_N => rst_n(i),
- TX_REFCLK => clk_200_osc,
+ TX_REFCLK => clk_200_txdata, --clk_200_osc,
TX_PLL_LOL_QD_S => tx_pll_lol(i),
RST_QD_C => rst_qd(i),
TX_PCS_RST_CH_C => tx_pcs_rst(i),
wa_position_rx(i) <= wa_position(i) when (IS_SYNC_SLAVE = c_YES) else x"0";
- PROC_ALLOW : process(clk_200_i(i))
+ PROC_ALLOW : process(clk_200_txdata) --clk_200_i(i))
begin
- if rising_edge(clk_200_i(i)) then -- clk_200_txdata ??
+ if rising_edge(clk_200_txdata) then -- clk_200_txdata ??
if rx_fsm_state(i) = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(i)(start_timer'left) = '1') then
rx_allow(i) <= '1';
tx_allow(i) <= '1';
tx_allow_q(i) <= tx_allow(i) when rising_edge(SYSCLK);
- PROC_START_TIMER : process(clk_200_i(i)) --clk_200_txdata??
+ PROC_START_TIMER : process(clk_200_txdata) --clk_200_i(i))
begin
- if rising_edge(clk_200_i(i)) then
+ if rising_edge(clk_200_txdata) then
if got_link_ready_i(i) = '1' then
watchdog_timer(i) <= (others => '0');
if start_timer(i)(start_timer'left) = '0' then
-------------------------------------------------
THE_TX : soda_tx_control
port map(
- CLK_200 => clk_200_i(i), --clk_200_txdata??
+ CLK_200 => tx_full_clk(i), --clk_200_i(i),
CLK_100 => SYSCLK,
RESET_IN => rst(i), --CLEAR, PL!
-------------------------------------------------
THE_RX_CONTROL : rx_control
port map(
- CLK_200 => clk_200_i(i), --PL!
+ CLK_200 => rx_full_clk(i), --clk_200_i(i), --PL!
CLK_100 => SYSCLK,
RESET_IN => rst(i), --CLEAR, PL!
generic( SERDES_NUM : integer range 0 to 3 := 0;
IS_SYNC_SLAVE : integer := c_NO); --select slave mode
port(
- CLK : in std_logic; -- _internal_ 200 MHz reference clock
+ OSCCLK : in std_logic; -- _internal_ 200 MHz reference clock
SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
MED_DATAREADY_OUT : out std_logic := '0';
MED_READ_IN : in std_logic;
- CLK_RX_HALF_OUT : out std_logic := '0'; --received 100 MHz
- CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz
- CLK_TX_HALF_OUT : out std_logic := '0'; --received 100 MHz
- CLK_TX_FULL_OUT : out std_logic := '0'; --received 200 MHz
+ RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
+ RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
+ TX_HALF_CLK_OUT : out std_logic := '0'; --pll 100 MHz
+ TX_FULL_CLK_OUT : out std_logic := '0'; --pll 200 MHz
--Sync operation
RX_DLM : out std_logic := '0';
end component;
-signal clk_200_i : std_logic;
-signal clk_200_internal : std_logic;
-signal clk_rx_full : std_logic;
-signal clk_rx_half : std_logic;
-signal clk_tx_full : std_logic;
-signal clk_tx_half : std_logic;
+--signal clk_200_i : std_logic;
+--signal clk_200_internal : std_logic;
+signal clk_200_osc : std_logic;
+signal rx_full_clk_ch0 : std_logic;
+signal rx_half_clk_ch0 : std_logic;
+signal tx_full_clk_ch0 : std_logic;
+signal tx_half_clk_ch0 : std_logic;
signal tx_data : std_logic_vector(7 downto 0);
signal tx_k : std_logic;
begin
-clk_200_internal <= CLK;
+clk_200_osc <= OSCCLK;
-CLK_RX_HALF_OUT <= clk_rx_half;
-CLK_RX_FULL_OUT <= clk_rx_full;
-CLK_TX_HALF_OUT <= clk_tx_half;
-CLK_TX_FULL_OUT <= clk_tx_full;
+RX_HALF_CLK_OUT <= rx_half_clk_ch0;
+RX_FULL_CLK_OUT <= rx_full_clk_ch0;
+TX_HALF_CLK_OUT <= tx_half_clk_ch0;
+TX_FULL_CLK_OUT <= tx_full_clk_ch0;
SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
rst <= (CLEAR or internal_make_link_reset_out);
--gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
--- clk_200_i <= clk_rx_full;
+-- clk_200_i <= rx_full_clk_ch0;
--end generate;
--gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
- clk_200_i <= clk_200_internal;
+-- clk_200_i <= clk_200_internal;
--end generate;
hdinn_ch0 => SD_RXD_N_IN,
hdoutp_ch0 => SD_TXD_P_OUT,
hdoutn_ch0 => SD_TXD_N_OUT,
- rxiclk_ch0 => clk_200_i, -- read fifo is no longer present! PL!
- txiclk_ch0 => clk_200_i,
- rx_full_clk_ch0 => clk_rx_full,
- rx_half_clk_ch0 => clk_rx_half,
- tx_full_clk_ch0 => clk_tx_full,
- tx_half_clk_ch0 => clk_tx_half,
- fpga_rxrefclk_ch0 => clk_200_internal, -- REF CLK MUST ALWAYS BE PRESENT
+ rxiclk_ch0 => tx_full_clk_ch0, --clk_200_i, -- read fifo is no longer present! PL!
+ txiclk_ch0 => tx_full_clk_ch0, --clk_200_i,
+ rx_full_clk_ch0 => rx_full_clk_ch0,
+ rx_half_clk_ch0 => rx_half_clk_ch0,
+ tx_full_clk_ch0 => tx_full_clk_ch0,
+ tx_half_clk_ch0 => tx_half_clk_ch0,
+ fpga_rxrefclk_ch0 => clk_200_osc, --clk_200_internal, -- REF CLK MUST ALWAYS BE PRESENT
txdata_ch0 => tx_data,
tx_k_ch0 => tx_k,
tx_force_disp_ch0 => '0',
SCI_RD => sci_read_i,
SCI_WRN => sci_write_i,
- fpga_txrefclk => clk_200_internal, -- REF CLK MUST ALWAYS BE PRESENT
+ fpga_txrefclk => clk_200_osc, --clk_200_internal, -- REF CLK MUST ALWAYS BE PRESENT
tx_serdes_rst_c => tx_serdes_rst,
tx_pll_lol_qd_s => tx_pll_lol,
rst_qd_c => rst_qd,
THE_RX_FSM : rx_reset_fsm
port map(
RST_N => rst_n,
- RX_REFCLK => clk_200_i,
+ RX_REFCLK => rx_full_clk_ch0, --clk_200_i,
TX_PLL_LOL_QD_S => tx_pll_lol,
RX_SERDES_RST_CH_C => rx_serdes_rst,
RX_CDR_LOL_CH_S => rx_cdr_lol,
THE_TX_FSM : tx_reset_fsm
port map(
RST_N => rst_n,
- TX_REFCLK => clk_200_internal,
+ TX_REFCLK => clk_200_osc, --clk_200_internal,
TX_PLL_LOL_QD_S => tx_pll_lol,
RST_QD_C => rst_qd,
TX_PCS_RST_CH_C => tx_pcs_rst,
--Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable
PROC_ALLOW : process begin
- wait until rising_edge(clk_200_i);
+ wait until rising_edge(clk_200_osc); --clk_200_i);
if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then
rx_allow <= '1';
else
-- If you are a SLAVE, you can then start transmitting right away. -- if you are a MASTER, you wait for the start_timer MSB to go high.
-- This gives a slave on the other side time to start-up
-- if the rx-link is NOT ready, the watchdog_timer starts. It should be longer than start_timer and will cause a hanging link to reset
-PROC_START_TIMER : process(clk_200_i)
+PROC_START_TIMER : process(clk_200_osc) --clk_200_i)
begin
- if rising_edge(clk_200_i) then
+ if rising_edge(clk_200_osc) then
if got_link_ready_i = '1' then
-- watchdog_timer <= (others => '0');
if start_timer(start_timer'left) = '0' then
-------------------------------------------------
THE_TX : soda_tx_control
port map(
- CLK_200 => clk_200_i,
+ CLK_200 => clk_200_osc, --clk_200_i,
CLK_100 => SYSCLK,
RESET_IN => rst, --CLEAR, PL!
-------------------------------------------------
THE_RX_CONTROL : rx_control
port map(
- CLK_200 => clk_rx_full, --clk_200_i, PL!
+ CLK_200 => rx_full_clk_ch0, --clk_200_i, PL!
CLK_100 => SYSCLK,
RESET_IN => rst, --CLEAR, PL!
generic( SERDES_NUM : integer range 0 to 3 := 0;
IS_SYNC_SLAVE : integer := c_YES); --select slave mode
port(
- CLK : in std_logic; -- 200 MHz reference clock
+ OSCCLK : in std_logic; -- 200 MHz reference clock
SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
MED_DATAREADY_OUT : out std_logic := '0';
MED_READ_IN : in std_logic;
- CLK_RX_HALF_OUT : out std_logic := '0'; --received 100 MHz
- CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz
- CLK_TX_HALF_OUT : out std_logic := '0'; --received 100 MHz
- CLK_TX_FULL_OUT : out std_logic := '0'; --received 200 MHz
+ RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
+ RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
+ TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
+ TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
--Sync operation
RX_DLM : out std_logic := '0';
end component;
-signal clk_200_i : std_logic;
-signal clk_200_internal : std_logic;
-signal clk_rx_full : std_logic;
-signal clk_rx_half : std_logic;
-signal clk_tx_full : std_logic;
-signal clk_tx_half : std_logic;
+--signal clk_200_i : std_logic;
+--signal clk_200_internal : std_logic;
+signal clk_200_osc : std_logic;
+signal rx_full_clk_ch3 : std_logic;
+signal rx_half_clk_ch3 : std_logic;
+signal tx_full_clk_ch3 : std_logic;
+signal tx_half_clk_ch3 : std_logic;
signal tx_data : std_logic_vector(7 downto 0);
signal tx_k : std_logic;
begin
-clk_200_internal <= CLK;
+clk_200_osc <= OSCCLK;
-CLK_RX_HALF_OUT <= clk_rx_half;
-CLK_RX_FULL_OUT <= clk_rx_full;
-CLK_TX_HALF_OUT <= clk_tx_half;
-CLK_TX_FULL_OUT <= clk_tx_full;
+RX_HALF_CLK_OUT <= rx_half_clk_ch3;
+RX_FULL_CLK_OUT <= rx_full_clk_ch3;
+TX_HALF_CLK_OUT <= tx_half_clk_ch3;
+TX_FULL_CLK_OUT <= tx_full_clk_ch3;
SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
LINK_READY_OUT <= got_link_ready_i;
-\r
+
--rst_n <= not CLEAR; PL!
rst_n <= not(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
--gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
- clk_200_i <= clk_rx_full;
+-- clk_200_i <= rx_full_clk_ch3;
--end generate;
--gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
hdinn_ch3 => SD_RXD_N_IN,
hdoutp_ch3 => SD_TXD_P_OUT,
hdoutn_ch3 => SD_TXD_N_OUT,
--- rxiclk_ch3 => clk_200_i, -- no more RX-fifo
- txiclk_ch3 => clk_200_i,
- rx_full_clk_ch3 => clk_rx_full,
- rx_half_clk_ch3 => clk_rx_half,
- tx_full_clk_ch3 => clk_tx_full,
- tx_half_clk_ch3 => clk_tx_half,
- fpga_rxrefclk_ch3 => clk_200_internal,
+ txiclk_ch3 => rx_full_clk_ch3, --clk_200_i,
+ rx_full_clk_ch3 => rx_full_clk_ch3,
+ rx_half_clk_ch3 => rx_half_clk_ch3,
+ tx_full_clk_ch3 => tx_full_clk_ch3,
+ tx_half_clk_ch3 => tx_half_clk_ch3,
+ fpga_rxrefclk_ch3 => clk_200_osc, --clk_200_internal,
txdata_ch3 => tx_data,
tx_k_ch3 => tx_k,
tx_force_disp_ch3 => '0',
SCI_RD => sci_read_i,
SCI_WRN => sci_write_i,
- fpga_txrefclk => clk_200_i,
+ fpga_txrefclk => rx_full_clk_ch3, --clk_200_osc, --clk_200_i,
tx_serdes_rst_c => tx_serdes_rst,
tx_pll_lol_qd_s => tx_pll_lol,
rst_qd_c => rst_qd,
THE_RX_FSM : rx_reset_fsm
port map(
RST_N => rst_n,
- RX_REFCLK => clk_200_internal, -- allways running PL!
+ RX_REFCLK => clk_200_osc, --clk_200_internal, -- allways running PL!
TX_PLL_LOL_QD_S => tx_pll_lol,
RX_SERDES_RST_CH_C => rx_serdes_rst,
RX_CDR_LOL_CH_S => rx_cdr_lol,
THE_TX_FSM : tx_reset_fsm
port map(
RST_N => rst_n,
- TX_REFCLK => clk_200_internal, -- allways running PL! 18-06 was clk_200_i
+ TX_REFCLK => rx_full_clk_ch3, --clk_200_osc, --clk_200_internal, -- allways running PL! 18-06 was clk_200_i
TX_PLL_LOL_QD_S => tx_pll_lol,
RST_QD_C => rst_qd,
TX_PCS_RST_CH_C => tx_pcs_rst,
--Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable
PROC_ALLOW : process begin
- wait until rising_edge(clk_200_i);
+ wait until rising_edge(rx_full_clk_ch3); --clk_200_osc); --clk_200_i);
if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then
rx_allow <= '1';
else
tx_allow_q <= tx_allow when rising_edge(SYSCLK);
-PROC_START_TIMER : process(clk_200_i)
+PROC_START_TIMER : process(rx_full_clk_ch3) --clk_200_osc) --clk_200_i)
begin
- if rising_edge(clk_200_i) then
+ if rising_edge(clk_200_osc) then
if got_link_ready_i = '1' then
watchdog_timer <= (others => '0');
if start_timer(start_timer'left) = '0' then
-------------------------------------------------
THE_TX : soda_tx_control
port map(
- CLK_200 => clk_200_i,
+ CLK_200 => rx_full_clk_ch3, --clk_200_osc, --clk_200_i,
CLK_100 => SYSCLK,
RESET_IN => rst, --CLEAR, PL!
-------------------------------------------------
THE_RX_CONTROL : rx_control
port map(
- CLK_200 => clk_rx_full, --clk_200_i, PL!
+ CLK_200 => rx_full_clk_ch3, --clk_200_i, PL!
CLK_100 => SYSCLK,
RESET_IN => rst, --CLEAR, PL!
port(
SYSCLK : in std_logic; -- fabric clock
SODACLK : in std_logic; -- recovered clock
- TX_SODACLK : in t_HUB_BIT; -- transmit clock
+-- SODA_OUT_CLK : in t_HUB_BIT; -- transmit clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
CLK_EN : in std_logic;
SERDES_NUM : integer range 0 to 3 := 0;
IS_SYNC_SLAVE : integer := c_NO); --select slave mode
port(
- CLK : in std_logic; -- _internal_ 200 MHz reference clock
+ OSCCLK : in std_logic; -- _internal_ 200 MHz reference clock
SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
MED_DATAREADY_OUT : out std_logic := '0';
MED_READ_IN : in std_logic;
- CLK_RX_HALF_OUT : out std_logic := '0'; --received 100 MHz
- CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz
- CLK_TX_HALF_OUT : out std_logic := '0'; --received 100 MHz
- CLK_TX_FULL_OUT : out std_logic := '0'; --received 200 MHz
+ RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
+ RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
+ TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
+ TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
--Sync operation
RX_DLM : out std_logic := '0';
MED_PACKET_NUM_OUT : out t_HUB_NUM; -- std_logic_vector(4*c_NUM_WIDTH-1 downto 0) := (others => '0');
MED_DATAREADY_OUT : out std_logic_vector(3 downto 0) := (others => '0');
MED_READ_IN : in std_logic_vector(3 downto 0);
- CLK_RX_HALF_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
- CLK_RX_FULL_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
- CLK_TX_HALF_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
- CLK_TX_FULL_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
+ RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
+ RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
+ TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
+ TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
--Sync operation
RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
IS_SYNC_SLAVE : integer := c_YES --select slave mode
);
port(
- CLK : in std_logic; -- 200 MHz reference clock
+ OSCCLK : in std_logic; -- 200 MHz reference clock
SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
MED_DATAREADY_OUT : out std_logic := '0';
MED_READ_IN : in std_logic;
- CLK_RX_HALF_OUT : out std_logic := '0'; --received 100 MHz
- CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz
-
+ RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
+ RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
+ TX_HALF_CLK_OUT : out std_logic := '0'; --pll 100 MHz
+ TX_FULL_CLK_OUT : out std_logic := '0'; --pll 200 MHz
--Sync operation
RX_DLM : out std_logic := '0';
RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
port(
SYSCLK : in std_logic; -- fabric clock
SODACLK : in std_logic; -- recovered clock
- TX_SODACLK : in t_HUB_BIT; -- tx-full clock
+-- TX_SODACLK : in t_HUB_BIT; -- tx-full clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
CLK_EN : in std_logic;
channel :for i in c_HUB_CHILDREN-1 downto 0 generate
- X_clk_domain : process(TX_SODACLK(i))
- begin
- if rising_edge(TX_SODACLK(i)) then
- if RESET='1' then
- TXsoda_cmd_valid_S(i) <= '0';
- TXstart_of_superburst_S(i) <= '0';
- TXsoda_cmd_word_S(i) <= (others => '0');
- TXsuper_burst_nr_S(i) <= (others => '0');
- else
- TXsoda_cmd_valid_S(i) <= soda_cmd_valid_S;
- TXstart_of_superburst_S(i) <= start_of_superburst_S;
- TXsoda_cmd_word_S(i) <= '0' & soda_cmd_word_S;
- TXsuper_burst_nr_S(i) <= '0' & super_burst_nr_S;
- end if;
- end if;
- end process;
+ --X_clk_domain : process(TX_SODACLK(i))
+ --begin
+ --if rising_edge(TX_SODACLK(i)) then
+ --if RESET='1' then
+ --TXsoda_cmd_valid_S(i) <= '0';
+ --TXstart_of_superburst_S(i) <= '0';
+ --TXsoda_cmd_word_S(i) <= (others => '0');
+ --TXsuper_burst_nr_S(i) <= (others => '0');
+ --else
+ --TXsoda_cmd_valid_S(i) <= soda_cmd_valid_S;
+ --TXstart_of_superburst_S(i) <= start_of_superburst_S;
+ --TXsoda_cmd_word_S(i) <= '0' & soda_cmd_word_S;
+ --TXsuper_burst_nr_S(i) <= '0' & super_burst_nr_S;
+ --end if;
+ --end if;
+ --end process;
\r
\r
\r
packet_builder : soda_packet_builder
port map(
- SODACLK => TX_SODACLK(i),
+ SODACLK => SODACLK,
RESET => RESET,
--Internal Connection
SODA_CMD_STROBE_IN => TXsoda_cmd_valid_S(i),
hub_reply_handler : soda_reply_handler
port map(
- SODACLK => TX_SODACLK(i),
+ SODACLK => SODACLK,
RESET => RESET,
CLEAR => '0',
CLK_EN => '1',
hub_calibration_timer : soda_calibration_timer
port map(
- SODACLK => TX_SODACLK(i),
+ SODACLK => SODACLK,
RESET => RESET,
CLEAR => '0',
CLK_EN => '1',
--Clock / Reset
-- signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
- signal clk_soda_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+-- signal clk_soda_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
-- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
signal clear_i : std_logic;
attribute syn_keep of GSR_N : signal is true;
attribute syn_preserve of GSR_N : signal is true;
signal clk_sys_internal : std_logic;
- signal clk_raw_internal : std_logic;
- signal clk_tdc : std_logic;
+-- signal clk_raw_internal : std_logic;
+ signal clk_200_osc : std_logic;
+ signal rx_full_clk : std_logic;
+ signal rx_half_clk : std_logic;
+ signal tx_full_clk : std_logic;
+ signal tx_half_clk : std_logic;
+-- signal clk_tdc : std_logic;
signal time_counter, time_counter2 : unsigned(31 downto 0);
--Media Interface
signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
--SODA
-signal soda_rx_clock_half : std_logic;
-signal soda_rx_clock_full : std_logic;
+--signal soda_rx_clock_half : std_logic;
+--signal soda_rx_clock_full : std_logic;
signal tx_dlm_i : std_logic;
signal rx_dlm_i : std_logic;
signal tx_dlm_word : std_logic_vector(7 downto 0);
signal soda_counter_i : unsigned(3 downto 0);
attribute syn_keep of soda_counter_i : signal is true;
-- fix signal names for constraining
- attribute syn_preserve of clk_soda_i : signal is true;
- attribute syn_keep of clk_soda_i : signal is true;
+-- attribute syn_preserve of clk_soda_i : signal is true;
+-- attribute syn_keep of clk_soda_i : signal is true;
-- attribute syn_preserve of soda_rx_clock_full : signal is true;
-- attribute syn_keep of soda_rx_clock_full : signal is true;
-- attribute syn_preserve of soda_rx_clock_half : signal is true;
-- attribute syn_keep of soda_rx_clock_half : signal is true;
attribute syn_preserve of clk_sys_internal : signal is true;
attribute syn_keep of clk_sys_internal : signal is true;
- attribute syn_preserve of clk_raw_internal : signal is true;
- attribute syn_keep of clk_raw_internal : signal is true;
+ attribute syn_preserve of clk_200_osc : signal is true;
+ attribute syn_keep of clk_200_osc : signal is true;
attribute syn_preserve of tx_dlm_i : signal is true;
attribute syn_keep of tx_dlm_i : signal is true;
attribute syn_preserve of rx_dlm_i : signal is true;
port map(
CLEAR_IN => '0', -- reset input (high active, async)
CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => clk_raw_internal, -- raw master clock, NOT from PLL/DLL!
+ CLK_IN => clk_200_osc, --clk_raw_internal, -- raw master clock, NOT from PLL/DLL!
SYSCLK_IN => clk_sys_internal, -- PLL/DLL remastered clock
PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
RESET_IN => '0', --general_reset_i, -- '0', -- general reset signal (SYSCLK) --peter schakel
port map(
CLK => CLK_GPLL_RIGHT,
CLKOP => clk_sys_internal,
- CLKOK => clk_raw_internal,
+ CLKOK => clk_200_osc, --clk_raw_internal,
LOCK => pll_lock
);
end generate;
-gen_125 : if USE_125_MHZ = c_YES generate
- clk_sys_internal <= CLK_GPLL_LEFT;
- clk_raw_internal <= CLK_GPLL_LEFT;
-end generate;
+--gen_125 : if USE_125_MHZ = c_YES generate
+-- clk_sys_internal <= CLK_GPLL_LEFT;
+-- clk_raw_internal <= CLK_GPLL_LEFT;
+--end generate;
-gen_sync_clocks : if SYNC_MODE = c_YES generate
+--gen_sync_clocks : if SYNC_MODE = c_YES generate
-- clk_sys_i <= clk_sys_internal;
- clk_soda_i <= soda_rx_clock_full;
+-- clk_soda_i <= soda_rx_clock_full;
-- clk_200_i <= soda_rx_clock_full;
-end generate;
+--end generate;
-gen_local_clocks : if SYNC_MODE = c_NO generate
+--gen_local_clocks : if SYNC_MODE = c_NO generate
-- clk_sys_i <= clk_sys_internal;
- clk_soda_i <= clk_raw_internal;
+-- clk_soda_i <= clk_raw_internal;
-- clk_200_i <= clk_raw_internal;
-end generate;
+--end generate;
---------------------------------------------------------------------------
IS_SYNC_SLAVE => c_YES
)
port map(
- CLK => clk_raw_internal, --clk_200_i,
+ OSCCLK => clk_200_osc, --clk_raw_internal, --clk_200_i,
SYSCLK => clk_sys_internal, --clk_sys_i,
RESET => reset_i,
CLEAR => clear_i,
MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
MED_DATAREADY_OUT => med_dataready_in(0),
MED_READ_IN => med_read_out(0),
- CLK_RX_HALF_OUT => soda_rx_clock_half,
- CLK_RX_FULL_OUT => soda_rx_clock_full,
+ RX_HALF_CLK_OUT => rx_half_clk, --soda_rx_clock_half,
+ RX_FULL_CLK_OUT => rx_full_clk, --soda_rx_clock_full,
+ TX_HALF_CLK_OUT => tx_half_clk,
+ TX_FULL_CLK_OUT => tx_full_clk,
RX_DLM => rx_dlm_i,
RX_DLM_WORD => rx_dlm_word,
A_SODA_CLIENT : soda_client
port map(
SYSCLK => clk_sys_internal, --clk_sys_i,
- SODACLK => clk_soda_i,
+ SODACLK => rx_full_clk, --soda_rx_clock_full, --clk_soda_i,
RESET => reset_i,
CLEAR => clear_i,
CLK_EN => '1',
end if;
end process;
- process(clk_soda_i)
+ process(rx_full_clk) --soda_rx_clock_full) --clk_soda_i)
begin
- if rising_edge(clk_soda_i) then
+ if rising_edge(rx_full_clk) then
soda_counter_i <= soda_counter_i+1;
end if;
end process;
TEST_LINE(3) <= soda_counter_i(2);
TEST_LINE(4) <= '0';
TEST_LINE(5) <= '0';
- TEST_LINE(6) <= soda_rx_clock_half;
+ TEST_LINE(6) <= rx_half_clk;
TEST_LINE(7) <= '0';
TEST_LINE(8) <= '0';
--Clock / Reset
-- signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
- signal clk_soda_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+-- signal clk_soda_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
-- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
signal clear_i : std_logic;
attribute syn_keep of GSR_N : signal is true;
attribute syn_preserve of GSR_N : signal is true;
signal clk_sys_internal : std_logic;
- signal clk_raw_internal : std_logic;
- signal clk_tdc : std_logic;
+-- signal clk_raw_internal : std_logic;
+ signal clk_200_osc : std_logic;
+
+ signal rxup_half_clk : std_logic;
+ signal rxup_full_clk : std_logic;
+ signal txup_half_clk : std_logic;
+ signal txup_full_clk : std_logic;
+
+ signal rxdn_half_clk : t_HUB_BIT;
+ signal rxdn_full_clk : t_HUB_BIT;
+ signal txdn_half_clk : t_HUB_BIT;
+ signal txdn_full_clk : t_HUB_BIT;
+
+-- signal clk_tdc : std_logic;
signal time_counter, time_counter2 : unsigned(31 downto 0);
--Media Interface
signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0');
--SODA
--- signal soda_rxup_clock_half : std_logic;
- signal soda_rxup_clock_full : std_logic;
--- signal soda_rxdn_clock_half : t_HUB_BIT;
- signal soda_rxdn_clock_full : t_HUB_BIT;
- signal soda_txdn_clock_full : t_HUB_BIT;
signal make_reset : std_logic;
--SODA uplink
signal soda_counter_i : unsigned(3 downto 0);
--- attribute syn_useioff : boolean;
--- --no IO-FF for LEDs relaxes timing constraints
--- attribute syn_useioff of LED_GREEN : signal is false;
--- attribute syn_useioff of LED_ORANGE : signal is false;
--- attribute syn_useioff of LED_RED : signal is false;
--- attribute syn_useioff of LED_YELLOW : signal is false;
--- attribute syn_useioff of TEMPSENS : signal is false;
--- attribute syn_useioff of PROGRAMN : signal is false;
--- attribute syn_useioff of CODE_LINE : signal is false;
--- attribute syn_useioff of LED_LINKOK : signal is false;
--- attribute syn_useioff of LED_TX : signal is false;
--- attribute syn_useioff of LED_RX : signal is false;
--- attribute syn_useioff of SFP_MOD0 : signal is false;
--- attribute syn_useioff of SFP_TXDIS : signal is false;
--- attribute syn_useioff of SFP_LOS : signal is false;
--- attribute syn_useioff of TEST_LINE : signal is false; --H!
-
--- --important signals _with_ IO-FF
--- attribute syn_useioff of FLASH_CLK : signal is true;
--- attribute syn_useioff of FLASH_CS : signal is true;
--- attribute syn_useioff of FLASH_DIN : signal is true;
--- attribute syn_useioff of FLASH_DOUT : signal is true;
--- attribute syn_useioff of FPGA5_COMM : signal is true;
attribute syn_keep of soda_counter_i : signal is true;
-- fix signal names for constraining
attribute syn_preserve of clk_sys_internal : signal is true;
attribute syn_keep of clk_sys_internal : signal is true;
- attribute syn_preserve of clk_raw_internal : signal is true;
- attribute syn_keep of clk_raw_internal : signal is true;
- attribute syn_preserve of clk_soda_i : signal is true;
- attribute syn_keep of clk_soda_i : signal is true;
+-- attribute syn_preserve of clk_raw_internal : signal is true;
+-- attribute syn_keep of clk_raw_internal : signal is true;
+-- attribute syn_preserve of clk_soda_i : signal is true;
+-- attribute syn_keep of clk_soda_i : signal is true;
attribute syn_preserve of txup_dlm_i : signal is true;
attribute syn_keep of txup_dlm_i : signal is true;
attribute syn_preserve of rxup_dlm_i : signal is true;
port map(
CLEAR_IN => '0', -- reset input (high active, async)
CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => clk_raw_internal, -- raw master clock, NOT from PLL/DLL!
+ CLK_IN => clk_200_osc, -- raw master clock, NOT from PLL/DLL!
SYSCLK_IN => clk_sys_internal, -- PLL/DLL remastered clock
PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
RESET_IN => '0', --general_reset_i, -- '0', -- general reset signal (SYSCLK) --peter schakel
DEBUG_OUT => open
);
- process(clk_sys_internal)
- begin
- if rising_edge(clk_sys_internal) then
- general_reset_i <= not SFP_LOS(1);
- end if;
- end process;
+-- process(clk_sys_internal)
+-- begin
+-- if rising_edge(clk_sys_internal) then
+-- general_reset_i <= not SFP_LOS(1);
+-- end if;
+-- end process;
---------------------------------------------------------------------------
-- Clock Handling
port map(
CLK => CLK_GPLL_RIGHT,
CLKOP => clk_sys_internal,
- CLKOK => clk_raw_internal,
+ CLKOK => clk_200_osc,
LOCK => pll_lock
);
--end generate;
--end generate;
--gen_sync_clocks : if SYNC_MODE = c_YES generate
- clk_soda_i <= soda_rxup_clock_full;
+-- clk_soda_i <= rxup_full_clk;
--end generate;
--gen_local_clocks : if SYNC_MODE = c_NO generate
IS_SYNC_SLAVE => c_YES
)
port map(
- CLK => clk_raw_internal, --clk_200_i,
+ OSCCLK => clk_200_osc, --clk_200_i,
SYSCLK => clk_sys_internal, --clk_sys_i,
RESET => reset_i,
CLEAR => clear_i,
MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
MED_DATAREADY_OUT => med_dataready_in(0),
MED_READ_IN => med_read_out(0),
- CLK_RX_HALF_OUT => open, --soda_rxup_clock_half,
- CLK_RX_FULL_OUT => soda_rxup_clock_full,
+ RX_HALF_CLK_OUT => rxup_half_clk,
+ RX_FULL_CLK_OUT => rxup_full_clk,
+ TX_HALF_CLK_OUT => txup_half_clk,
+ TX_FULL_CLK_OUT => txup_full_clk,
RX_DLM => rxup_dlm_i,
RX_DLM_WORD => rxup_dlm_word,
A_SODA_HUB : soda_hub
port map(
SYSCLK => clk_sys_internal, --clk_sys_i,
- SODACLK => clk_soda_i,
- TX_SODACLK => soda_txdn_clock_full, -- This is 4 clocks !!
+ SODACLK => rxup_full_clk, --clk_soda_i,
+-- SODA_OUT_CLK => txdn_full_clk, -- This is 4 clocks !!
RESET => reset_i,
CLEAR => clear_i,
CLK_EN => '1',
IS_SYNC_SLAVE => c_NO
)
port map(
- OSC_CLK => clk_raw_internal,
- TX_DATACLK => clk_soda_i, --clk_raw_internal, --clk_200_i,
+ OSC_CLK => clk_200_osc,
+ TX_DATACLK => rxup_full_clk, --clk_soda_i, --clk_raw_internal, --clk_200_i,
SYSCLK => clk_sys_internal, --clk_sys_i,
RESET => downlink_reset,
CLEAR => downlink_clear,
MED_READ_IN(2) => med_read_out(2),
MED_READ_IN(3) => med_read_out(4),
- CLK_RX_HALF_OUT(0) => open,
- CLK_RX_HALF_OUT(1) => open,
- CLK_RX_HALF_OUT(2) => open,
- CLK_RX_HALF_OUT(3) => open,
+ RX_HALF_CLK_OUT(0) => rxdn_half_clk(0),
+ RX_HALF_CLK_OUT(1) => rxdn_half_clk(1),
+ RX_HALF_CLK_OUT(2) => rxdn_half_clk(2),
+ RX_HALF_CLK_OUT(3) => rxdn_half_clk(3),
- CLK_RX_FULL_OUT(0) => soda_rxdn_clock_full(0), -- needed for sync replies i.e. calibration
- CLK_RX_FULL_OUT(1) => soda_rxdn_clock_full(1), -- needed for sync replies i.e. calibration
- CLK_RX_FULL_OUT(2) => soda_rxdn_clock_full(2), -- needed for sync replies i.e. calibration
- CLK_RX_FULL_OUT(3) => soda_rxdn_clock_full(3), -- needed for sync replies i.e. calibration
+ RX_FULL_CLK_OUT(0) => rxdn_full_clk(0), -- needed for sync replies i.e. calibration
+ RX_FULL_CLK_OUT(1) => rxdn_full_clk(1), -- needed for sync replies i.e. calibration
+ RX_FULL_CLK_OUT(2) => rxdn_full_clk(2), -- needed for sync replies i.e. calibration
+ RX_FULL_CLK_OUT(3) => rxdn_full_clk(3), -- needed for sync replies i.e. calibration
- CLK_TX_HALF_OUT(0) => open,
- CLK_TX_HALF_OUT(1) => open,
- CLK_TX_HALF_OUT(2) => open,
- CLK_TX_HALF_OUT(3) => open,
+ TX_HALF_CLK_OUT(0) => txdn_half_clk(0),
+ TX_HALF_CLK_OUT(1) => txdn_half_clk(1),
+ TX_HALF_CLK_OUT(2) => txdn_half_clk(2),
+ TX_HALF_CLK_OUT(3) => txdn_half_clk(3),
- CLK_TX_FULL_OUT(0) => soda_txdn_clock_full(0),
- CLK_TX_FULL_OUT(1) => soda_txdn_clock_full(1),
- CLK_TX_FULL_OUT(2) => soda_txdn_clock_full(2),
- CLK_TX_FULL_OUT(3) => soda_txdn_clock_full(3),
+ TX_FULL_CLK_OUT(0) => txdn_full_clk(0),
+ TX_FULL_CLK_OUT(1) => txdn_full_clk(1),
+ TX_FULL_CLK_OUT(2) => txdn_full_clk(2),
+ TX_FULL_CLK_OUT(3) => txdn_full_clk(3),
RX_DLM(0) => rxdn_dlm_i(0),
RX_DLM(1) => rxdn_dlm_i(1),
end if;
end process;
- process(clk_soda_i)
+ process(rxup_full_clk) --clk_soda_i)
begin
- if rising_edge(clk_soda_i) then
+ if rising_edge(rxup_full_clk) then
soda_counter_i <= soda_counter_i+1;
end if;
end process;
--SODA
signal SOB_S : std_logic := '0';
-- fix signal names for constraining
- attribute syn_preserve of CLK_GPLL_LEFT : signal is true;
- attribute syn_keep of CLK_GPLL_LEFT : signal is true;
- attribute syn_preserve of CLK_GPLL_RIGHT : signal is true;
- attribute syn_keep of CLK_GPLL_RIGHT : signal is true;
- attribute syn_preserve of CLK_PCLK_LEFT : signal is true;
- attribute syn_keep of CLK_PCLK_LEFT : signal is true;
- attribute syn_preserve of CLK_PCLK_RIGHT : signal is true;
- attribute syn_keep of CLK_PCLK_RIGHT : signal is true;
-
attribute syn_preserve of soda_rx_clock_full : signal is true;
attribute syn_keep of soda_rx_clock_full : signal is true;
attribute syn_preserve of soda_rx_clock_half : signal is true;
IS_SYNC_SLAVE => c_NO
)
port map(
- CLK => clk_raw_internal,
+ OSCCLK => clk_raw_internal,
SYSCLK => clk_sys_internal,
RESET => reset_i,
CLEAR => clear_i,
MED_PACKET_NUM_OUT => med_packet_num_in(5 downto 3),
MED_DATAREADY_OUT => med_dataready_in(1),
MED_READ_IN => med_read_out(1),
- CLK_RX_HALF_OUT => soda_rx_clock_half,
- CLK_RX_FULL_OUT => soda_rx_clock_full,
- CLK_TX_HALF_OUT => soda_tx_clock_half,
- CLK_TX_FULL_OUT => soda_tx_clock_full,
+ RX_HALF_CLK_OUT => soda_rx_clock_half,
+ RX_FULL_CLK_OUT => soda_rx_clock_full,
+ TX_HALF_CLK_OUT => soda_tx_clock_half,
+ TX_FULL_CLK_OUT => soda_tx_clock_full,
RX_DLM => rx_dlm_i,
RX_DLM_WORD => rx_dlm_word,
-- The Soda Central
---------------------------------------------------------------------------
-THE_SOB_SOURCE : soda_start_of_burst_faker\r
- generic map(\r
+THE_SOB_SOURCE : soda_start_of_burst_faker
+ generic map(
CLOCK_PERIOD => cSYS_CLOCK_PERIOD, -- clock-period in ns
BURST_PERIOD => cBURST_PERIOD -- burst-period in ns
)
SODA_ACK_OUT => soda_ack,
LEDS_OUT => soda_leds
);
-\r
-\r
+
+
raw : soda_clockscaler
port map(
CLK => clk_raw_internal,
CLOCK_ENABLE_OUT => open,
CLOCK_OUT => open
);
-\r
+
tx : soda_clockscaler
port map(
CLK => soda_tx_clock_full,
RESET => reset_i,
CLOCK_ENABLE_OUT => open,
- CLOCK_OUT => open\r
+ CLOCK_OUT => open
);
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_client_probe.rvl" Date="2014-06-24">
+<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_client_probe.rvl" Date="2014-07-07">
<IP Version="1_5_062609"/>
<Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_client"/>
- <Core InsertDataset="0" Insert="1" Reveal_sig="2041647785" Name="trb3_periph_sodaclient_LA0" ID="0">
+ <Core InsertDataset="0" Insert="1" Reveal_sig="2043606920" Name="trb3_periph_sodaclient_LA0" ID="0">
<Setting>
- <Clock SampleClk="clk_soda_i" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
+ <Clock SampleClk="tx_full_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="128"/>
<Capture Mode="0" MinSamplesPerTrig="8"/>
<Event CntEnable="0" MaxEventCnt="8"/>
</Setting>
<Dataset Name="Base">
<Trace>
- <Sig Type="SIG" Name="the_sync_link/rx_cdr_lol"/>
<Bus Name="the_sync_link/rx_data">
<Sig Type="SIG" Name="the_sync_link/rx_data:0"/>
<Sig Type="SIG" Name="the_sync_link/rx_data:1"/>
<Sig Type="SIG" Name="the_sync_link/rx_data:6"/>
<Sig Type="SIG" Name="the_sync_link/rx_data:7"/>
</Bus>
+ <Sig Type="SIG" Name="the_sync_link/rx_k"/>
<Sig Type="SIG" Name="the_sync_link/rx_dlm"/>
<Bus Name="the_sync_link/rx_dlm_word">
<Sig Type="SIG" Name="the_sync_link/rx_dlm_word:0"/>
<Sig Type="SIG" Name="the_sync_link/rx_dlm_word:6"/>
<Sig Type="SIG" Name="the_sync_link/rx_dlm_word:7"/>
</Bus>
- <Sig Type="SIG" Name="the_sync_link/rx_error"/>
- <Bus Name="the_sync_link/rx_fsm_state">
- <Sig Type="SIG" Name="the_sync_link/rx_fsm_state:0"/>
- <Sig Type="SIG" Name="the_sync_link/rx_fsm_state:1"/>
- <Sig Type="SIG" Name="the_sync_link/rx_fsm_state:2"/>
- <Sig Type="SIG" Name="the_sync_link/rx_fsm_state:3"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/rx_k"/>
<Sig Type="SIG" Name="the_sync_link/rx_los_low"/>
<Sig Type="SIG" Name="the_sync_link/rx_pcs_rst"/>
<Sig Type="SIG" Name="the_sync_link/rx_serdes_rst"/>
- <Bus Name="the_sync_link/the_rx_fsm/state_out">
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/state_out:0"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/state_out:1"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/state_out:2"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/state_out:3"/>
- </Bus>
- <Bus Name="the_sync_link/the_rx_fsm/cs">
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/cs:0"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/cs:1"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/cs:2"/>
- </Bus>
- <Bus Name="the_sync_link/the_rx_fsm/ns">
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/ns:0"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/ns:1"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/ns:2"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/sd_los_in"/>
- <Sig Type="SIG" Name="the_sync_link/sd_txdis_out"/>
- <Sig Type="SIG" Name="the_sync_link/tx_allow"/>
<Sig Type="SIG" Name="the_sync_link/tx_allow_q"/>
+ <Sig Type="SIG" Name="the_sync_link/tx_k"/>
<Bus Name="the_sync_link/tx_data">
<Sig Type="SIG" Name="the_sync_link/tx_data:0"/>
<Sig Type="SIG" Name="the_sync_link/tx_data:1"/>
<Sig Type="SIG" Name="the_sync_link/tx_dlm_word:6"/>
<Sig Type="SIG" Name="the_sync_link/tx_dlm_word:7"/>
</Bus>
- <Bus Name="the_sync_link/tx_fsm_state">
- <Sig Type="SIG" Name="the_sync_link/tx_fsm_state:0"/>
- <Sig Type="SIG" Name="the_sync_link/tx_fsm_state:1"/>
- <Sig Type="SIG" Name="the_sync_link/tx_fsm_state:2"/>
- <Sig Type="SIG" Name="the_sync_link/tx_fsm_state:3"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/tx_k"/>
- <Sig Type="SIG" Name="the_sync_link/tx_pcs_rst"/>
- <Sig Type="SIG" Name="the_sync_link/tx_pll_lol"/>
- <Sig Type="SIG" Name="the_sync_link/tx_serdes_rst"/>
- <Bus Name="the_sync_link/wa_position">
- <Sig Type="SIG" Name="the_sync_link/wa_position:0"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:1"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:2"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:3"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:4"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:5"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:6"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:7"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:8"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:9"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:10"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:11"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:12"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:13"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:14"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:15"/>
- </Bus>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/soda_dlm_preview_s"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/tx_dlm_preview_out"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/tx_dlm_out"/>
- <Bus Name="a_soda_client/reply_packet_builder/tx_dlm_word_out">
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/tx_dlm_word_out:0"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/tx_dlm_word_out:1"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/tx_dlm_word_out:2"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/tx_dlm_word_out:3"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/tx_dlm_word_out:4"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/tx_dlm_word_out:5"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/tx_dlm_word_out:6"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/tx_dlm_word_out:7"/>
- </Bus>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/start_of_superburst"/>
- <Bus Name="a_soda_client/reply_packet_builder/super_burst_nr_in">
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:0"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:1"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:2"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:3"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:4"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:5"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:6"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:7"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:8"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:9"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:10"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:11"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:12"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:13"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:14"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:15"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:16"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:17"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:18"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:19"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:20"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:21"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:22"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:23"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:24"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:25"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:26"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:27"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:28"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:29"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/super_burst_nr_in:30"/>
- </Bus>
- <Bus Name="a_soda_client/reply_packet_builder/packet_state_s">
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/packet_state_s:0"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/packet_state_s:1"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/packet_state_s:2"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/packet_state_s:3"/>
- <Sig Type="SIG" Name="a_soda_client/reply_packet_builder/packet_state_s:4"/>
- </Bus>
+ <Sig Type="SIG" Name="the_sync_link/watchdog_trigger"/>
</Trace>
<Trigger>
- <TU Serialbits="0" Type="0" ID="1" Sig="the_sync_link/watchdog_trigger,"/>
- <TU Serialbits="0" Type="0" ID="2" Sig="a_soda_client/start_of_superburst_s,"/>
- <TU Serialbits="0" Type="0" ID="3" Sig="the_sync_link/rx_cdr_lol,"/>
- <TU Serialbits="0" Type="0" ID="4" Sig="the_sync_link/rx_los_low,"/>
- <TU Serialbits="0" Type="0" ID="5" Sig="(BUS)the_sync_link/rx_fsm_state[3:0],"/>
- <TU Serialbits="0" Type="0" ID="6" Sig="the_sync_link/the_serdes/rx_cv_err_ch3,"/>
+ <TU Serialbits="0" Type="0" ID="1" Sig="led_green,"/>
+ <TU Serialbits="0" Type="0" ID="2" Sig=""/>
+ <TU Serialbits="0" Type="0" ID="3" Sig="the_sync_link/watchdog_trigger,"/>
<TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="3" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="4" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="5" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="6" Resource="0"/>
</Trigger>
</Dataset>
</Core>
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_hub_probe.rvl" Date="2014-07-02">
+<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_hub_probe.rvl" Date="2014-07-08">
<IP Version="1_5_062609"/>
<Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_hub"/>
- <Core InsertDataset="0" Insert="1" Reveal_sig="2042945940" Name="trb3_periph_sodahub_LA0" ID="0">
+ <Core InsertDataset="0" Insert="1" Reveal_sig="2043713826" Name="trb3_periph_sodahub_LA0" ID="0">
<Setting>
- <Clock SampleClk="clk_raw_internal" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
- <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="256"/>
+ <Clock SampleClk="rxup_full_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
+ <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="128"/>
<Capture Mode="0" MinSamplesPerTrig="8"/>
<Event CntEnable="0" MaxEventCnt="8"/>
<TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_soda_hub_LA0_net"/>
<Sig Type="SIG" Name="a_soda_hub/expected_reply_s:3:6"/>
<Sig Type="SIG" Name="a_soda_hub/expected_reply_s:3:7"/>
</Bus>
+ <Sig Type="SIG" Name="clear_i"/>
</Trace>
<Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="a_soda_hub/recv_start_calibration_s,"/>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140623.bit</File>
- <FileTime>06/23/14 18:00:44</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140707.bit</File>
+ <FileTime>07/07/14 13:26:49</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140623.bit</File>
- <FileTime>06/23/14 18:00:44</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140707.bit</File>
+ <FileTime>07/07/14 11:46:30</FileTime>
<JedecChecksum>N/A</JedecChecksum>
<Operation>Fast Program</Operation>
<Option>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodahub_20140702.bit</File>
- <FileTime>07/03/14 15:55:49</FileTime>
- <JedecChecksum>N/A</JedecChecksum>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodahub_20140708.bit</File>
+ <FileTime>07/08/14 08:30:03</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140624.bit</File>
- <FileTime>06/24/14 17:16:05</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140707.bit</File>
+ <FileTime>07/07/14 15:37:02</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140701.bit</File>
- <FileTime>07/01/14 09:40:14</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140707.bit</File>
+ <FileTime>07/07/14 11:46:30</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140701.bit</File>
- <FileTime>07/01/14 09:40:14</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140707.bit</File>
+ <FileTime>07/07/14 11:46:30</FileTime>
+ <JedecChecksum>N/A</JedecChecksum>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
jspc29 / soda.git / commitdiff