MEDIA_MED2INT : in med2int_array_t(0 to 0);
MEDIA_INT2MED : out int2med_array_t(0 to 0);
+ MY_ADDRESS_IN : in std_logic_vector(15 downto 0);
+
--Event information coming from CTS for CRI
CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
CTS_CODE_IN : in std_logic_vector (7 downto 0);
signal cri_reply_packet_num_in : std_logic_vector( 2 downto 0);
signal cri_reply_read_out : std_logic;
+ --API data Transmitter to CRI
+ signal cri_apl_data_in : std_logic_vector(15 downto 0);
+ signal cri_apl_packet_num_in : std_logic_vector( 2 downto 0);
+ signal cri_apl_dataready_in : std_logic;
+ signal cri_apl_read_out : std_logic;
+ signal cri_apl_send_in : std_logic;
+
+ --API data Receiver from CRI
+ signal cri_apl_data_out : std_logic_vector(15 downto 0);
+ signal cri_apl_packet_num_out : std_logic_vector( 2 downto 0);
+ signal cri_apl_typ_out : std_logic_vector( 2 downto 0);
+ signal cri_apl_dataready_out : std_logic;
+ signal cri_apl_read_in : std_logic;
+
+ --API data controller
+ signal cri_apl_run_out : std_logic;
+ signal cri_packet_num_cnt : unsigned( 1 downto 0) := 0;
+ signal cri_data_send_cnt : unsigned(15 downto 0) := 0;
+ signal cri_send : std_logic;
+
+ signal cri_event_cnt : unsigned(15 downto 0) := 0;
+
--DEBUG SIGNALS:
signal debug_resp_control : std_logic_vector(63 downto 0);
signal readout_finished_cnt, readout_start_cnt : unsigned(15 downto 0);
PS_DATA_IN => (others => '0'),
PS_WR_EN_IN => '0',
PS_ACTIVATE_IN => '0',
- PS_RESPONSE_READY_OUT => open, -- TODO: make use of it
+ PS_RESPONSE_READY_OUT => resp_ready, -- TODO: make use of it
PS_BUSY_OUT => open,--busy(3), -- TODO: make use of it
PS_SELECTED_IN => '1',
PS_SRC_MAC_ADDRESS_IN => (others => '0'),
DATA_HIST_OUT => open,--DATA_HIST_OUT
BUS_DBG_RX => BUS_DBG_RX,
- BUS_DBG_TX => BUS_DBG_TX
+ BUS_DBG_TX => BUS_DBG_TX,
+
+ --debuging for TrbNet Transfer
+ dbg_event_cnt => cri_event_cnt
);
- THE_CRI_TRANSPORT_CONTROL_CONTROLER : process begin
+ THE_CRI_READOUT_CONTROL : process begin
wait until rising_edge(CLK);
if RESET = '1' then
--tc_rd_en <= '0';
+ cri_packet_num_cnt <= 0;
+ cri_data_send_cnt <= 0;
+ cri_event_cnt <= 0;
else
- -- if resp_ready = '1' then --maybe not good in timing; then maybe event_bytes != loaded_bytes for ever
- -- tc_rd_en <= '1';
- -- else
- -- tc_rd_en <= '0'; --includes also busy state
- -- end if;
+-- if resp_ready = '1' then --maybe not good in timing; then maybe event_bytes != loaded_bytes for ever
+-- tc_rd_en <= '1';
+-- else
+-- tc_rd_en <= '0'; --includes also busy state
+-- end if;
if (debug_resp_control(35 downto 32) <= x"2") then
tc_rd_en <= '0';
tc_rd_en <= '1';
end if;
+ ---
+
+ --fifo 8to 16 with almost empty and full
+
+
+ if (cri_data_send_cnt < x"20" ) then
+ cri_send <= '1';
+ else
+ cri_send <= '0';
+ if (cri_apl_run_out = '0') then -- data transfer has finished and the reply is in
+ cri_data_send_cnt <= 0;
+ cri_event_cnt <= cri_event_cnt + 1;
+ end if;
+ end if;
+
+ -- Write only if buffer in api is not full
+ if cri_apl_read_out = '0' and cri_send = '1' then --TODO: add fifo dataready for real dataflow
+ cri_apl_dataready_in <= '1';
+ cri_apl_data_in <= x"1234";
+ cri_apl_packet_num_in <= '0' & std_logic_vector(cri_packet_num_cnt);
+ cri_packet_num_cnt <= cri_packet_num_cnt + 1;
+ cri_apl_send_in <= '1';
+ cri_data_send_cnt <= cri_data_send_cnt + 1;
+ else
+ cri_apl_send_in <= '0';
+ end if;
+
+
end if;
end process;
---------------------------------------------------------------------
-- active API for Data Channel
---------------------------------------------------------------------
--- TRG_CHANNEL_API: trb_net16_api_base
--- generic map (
--- API_TYPE => c_API_ACTIVE,
--- FIFO_TO_INT_DEPTH => 6,
--- FIFO_TO_APL_DEPTH => 6,
--- FORCE_REPLY => 1,
--- SBUF_VERSION => 6,
--- USE_VENDOR_CORES => c_YES,
--- SECURE_MODE_TO_APL => c_YES,
--- SECURE_MODE_TO_INT => c_YES,
--- APL_WRITE_ALL_WORDS=> c_NO
--- )
--- port map (
--- -- Misc
--- CLK => CLK,
--- RESET => reset_i,
--- CLK_EN => '1',
--- -- APL Transmitter port
--- APL_DATA_IN => (others => '0'),
--- APL_PACKET_NUM_IN => "000",
--- APL_DATAREADY_IN => '0', -- almostfullflag ; daten in fifo von 8 auf 16 bit packen
--- APL_READ_OUT => open,
--- APL_SHORT_TRANSFER_IN => '0',
--- APL_DTYPE_IN => CTS_TRG_TYPE_IN,
--- APL_ERROR_PATTERN_IN => trg_apl_error_pattern_in(31 downto 0),
--- APL_SEND_IN => CTS_TRG_SEND_IN,
--- APL_TARGET_ADDRESS_IN => (others => '0'),
--- -- Receiver port
--- APL_DATA_OUT => trg_apl_data_out(15 downto 0),
--- APL_PACKET_NUM_OUT=> trg_apl_packet_num_out(2 downto 0),
--- APL_TYP_OUT => trg_apl_typ_out(2 downto 0),
--- APL_DATAREADY_OUT => trg_apl_dataready_out,
--- APL_READ_IN => trg_apl_read_in,
--- -- APL Control port
--- APL_RUN_OUT => trg_apl_run_out,
--- APL_MY_ADDRESS_IN => my_address,
--- APL_SEQNR_OUT => open,
--- APL_LENGTH_IN => (others => '0'),
---
---
--- -- Internal direction port
--- INT_MASTER_DATAREADY_OUT => cri_init_dataready_out,
--- INT_MASTER_DATA_OUT => cri_init_data_out,
--- INT_MASTER_PACKET_NUM_OUT=> cri_init_packet_num_out,
--- INT_MASTER_READ_IN => cri_init_read_in,
--- INT_MASTER_DATAREADY_IN => '0',
--- INT_MASTER_DATA_IN => (others => '0'),
--- INT_MASTER_PACKET_NUM_IN => "000",
--- INT_MASTER_READ_OUT => open,
--- INT_SLAVE_DATAREADY_OUT => open,
--- INT_SLAVE_DATA_OUT => open,
--- INT_SLAVE_PACKET_NUM_OUT => open,
--- INT_SLAVE_READ_IN => '1',
--- INT_SLAVE_DATAREADY_IN => cri_reply_dataready_in,
--- INT_SLAVE_DATA_IN => cri_reply_data_in,
--- INT_SLAVE_PACKET_NUM_IN => cri_reply_packet_num_in,
--- INT_SLAVE_READ_OUT => cri_reply_read_out,
--- -- Status and control port
--- CTRL_SEQNR_RESET => '0',--common_ctrl(10), --TO BE IMPLEMENTED
--- STAT_FIFO_TO_INT => open,
--- STAT_FIFO_TO_APL => open
--- );
+ TRG_CHANNEL_API: trb_net16_api_base
+ generic map (
+ API_TYPE => c_API_ACTIVE,
+ FIFO_TO_INT_DEPTH => 6,
+ FIFO_TO_APL_DEPTH => 6,
+ FORCE_REPLY => 1,
+ SBUF_VERSION => 0,
+ USE_VENDOR_CORES => c_YES,
+ SECURE_MODE_TO_APL => c_YES,
+ SECURE_MODE_TO_INT => c_YES,
+ APL_WRITE_ALL_WORDS=> c_YES
+ )
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => reset_i,
+ CLK_EN => '1',
+ -- APL Transmitter port
+ APL_DATA_IN => cri_apl_data_in,
+ APL_PACKET_NUM_IN => cri_apl_packet_num_in,
+ APL_DATAREADY_IN => cri_apl_dataready_in, -- almostfullflag ; daten in fifo von 8 auf 16 bit packen
+ APL_READ_OUT => cri_apl_read_out,
+ APL_SHORT_TRANSFER_IN => '0',
+ APL_DTYPE_IN => (others => '0'),
+ APL_ERROR_PATTERN_IN => (others => '0'),
+ APL_SEND_IN => cri_apl_send_in, -- 1 till end of Datastream
+ APL_TARGET_ADDRESS_IN => (others => '1'),
+ -- Receiver port
+ APL_DATA_OUT => cri_apl_data_out,
+ APL_PACKET_NUM_OUT => cri_apl_packet_num_out,
+ APL_TYP_OUT => cri_apl_typ_out,
+ APL_DATAREADY_OUT => cri_apl_dataready_out,
+ APL_READ_IN => cri_apl_read_in,
+ -- APL Control port
+ APL_RUN_OUT => cri_apl_run_out,
+ APL_MY_ADDRESS_IN => MY_ADDRESS_IN,
+ APL_SEQNR_OUT => open,
+ APL_LENGTH_IN => (others => '0'),
+ APL_FIFO_COUNT_OUT => open,
+
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT => cri_init_dataready_out,
+ INT_MASTER_DATA_OUT => cri_init_data_out,
+ INT_MASTER_PACKET_NUM_OUT=> cri_init_packet_num_out,
+ INT_MASTER_READ_IN => cri_init_read_in,
+ INT_MASTER_DATAREADY_IN => '0',
+ INT_MASTER_DATA_IN => (others => '0'),
+ INT_MASTER_PACKET_NUM_IN => "000",
+ INT_MASTER_READ_OUT => open,
+ INT_SLAVE_DATAREADY_OUT => open,
+ INT_SLAVE_DATA_OUT => open,
+ INT_SLAVE_PACKET_NUM_OUT => open,
+ INT_SLAVE_READ_IN => '1',
+ INT_SLAVE_DATAREADY_IN => cri_reply_dataready_in,
+ INT_SLAVE_DATA_IN => cri_reply_data_in,
+ INT_SLAVE_PACKET_NUM_IN => cri_reply_packet_num_in,
+ INT_SLAVE_READ_OUT => cri_reply_read_out,
+ -- Status and control port
+ CTRL_SEQNR_RESET => '0',--common_ctrl(10), --TO BE IMPLEMENTED
+ STAT_FIFO_TO_INT => open,
+ STAT_FIFO_TO_APL => open
+ );
--iobuf on streaming api, towards CRI, data channel
--- THE_IOBUF_1 : trb_net16_iobuf
--- generic map(
--- IBUF_DEPTH => 6,
--- USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(1),
--- USE_CHECKSUM => cfg_USE_CHECKSUM(1),
--- INIT_CAN_SEND_DATA => c_YES,
--- INIT_CAN_RECEIVE_DATA => c_YES,
--- REPLY_CAN_SEND_DATA => c_YES,
--- REPLY_CAN_RECEIVE_DATA => c_NO
--- )
--- port map(
--- -- Misc
--- CLK => CLK,
--- RESET => reset_i_mux_io,
--- CLK_EN => CLK_EN,
--- -- Media direction port
--- MED_INIT_DATAREADY_OUT => io_dataready_out(2),
--- MED_INIT_DATA_OUT => io_data_out(47 downto 32),
--- MED_INIT_PACKET_NUM_OUT => io_packet_num_out(8 downto 6),
--- MED_INIT_READ_IN => io_read_in(2),
---
--- MED_REPLY_DATAREADY_OUT => io_dataready_out(3),
--- MED_REPLY_DATA_OUT => io_data_out(63 downto 48),
--- MED_REPLY_PACKET_NUM_OUT => io_packet_num_out(11 downto 9),
--- MED_REPLY_READ_IN => io_read_in(3),
---
--- MED_DATAREADY_IN => io_dataready_in(1),
--- MED_DATA_IN => io_data_in(31 downto 16),
--- MED_PACKET_NUM_IN => io_packet_num_in(5 downto 3),
--- MED_READ_OUT => io_read_out(1),
--- MED_ERROR_IN => io_error_in,
---
--- -- Internal direction port
---
--- INT_INIT_DATAREADY_OUT => open,
--- INT_INIT_DATA_OUT => open,
--- INT_INIT_PACKET_NUM_OUT => open,
--- INT_INIT_READ_IN => '1',
---
--- INT_INIT_DATAREADY_IN => cri_init_dataready_out,
--- INT_INIT_DATA_IN => cri_init_data_out, -- gbe like data to CRI
--- INT_INIT_PACKET_NUM_IN => cri_init_packet_num_out,
--- INT_INIT_READ_OUT => cri_init_read_in,
---
--- INT_REPLY_DATAREADY_OUT => cri_reply_dataready_in,
--- INT_REPLY_DATA_OUT => cri_reply_data_in, -- answer from CRI
--- INT_REPLY_PACKET_NUM_OUT => cri_reply_packet_num_in,
--- INT_REPLY_READ_IN => cri_reply_read_out,
---
--- INT_REPLY_DATAREADY_IN => '0',
--- INT_REPLY_DATA_IN => (others => '0'),
--- INT_REPLY_PACKET_NUM_IN => (others => '0'),
--- INT_REPLY_READ_OUT => open,
---
--- -- Status and control port
--- STAT_GEN => open,
--- STAT_IBUF_BUFFER => open,
--- CTRL_GEN => (others => '0'),
--- STAT_INIT_OBUF_DEBUG => open,
--- STAT_REPLY_OBUF_DEBUG => open,
--- TIMER_TICKS_IN => TIMER_TICKS_IN
--- );
+ THE_IOBUF_1 : trb_net16_iobuf
+ generic map(
+ IBUF_DEPTH => 6,
+ USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(1),
+ USE_CHECKSUM => cfg_USE_CHECKSUM(1),
+ INIT_CAN_SEND_DATA => c_YES,
+ INIT_CAN_RECEIVE_DATA => c_NO,
+ REPLY_CAN_SEND_DATA => c_NO,
+ REPLY_CAN_RECEIVE_DATA => c_YES
+ )
+ port map(
+ -- Misc
+ CLK => CLK,
+ RESET => reset_i_mux_io,
+ CLK_EN => CLK_EN,
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT => io_dataready_out(2),
+ MED_INIT_DATA_OUT => io_data_out(47 downto 32),
+ MED_INIT_PACKET_NUM_OUT => io_packet_num_out(8 downto 6),
+ MED_INIT_READ_IN => io_read_in(2),
+
+ MED_REPLY_DATAREADY_OUT => io_dataready_out(3),
+ MED_REPLY_DATA_OUT => io_data_out(63 downto 48),
+ MED_REPLY_PACKET_NUM_OUT => io_packet_num_out(11 downto 9),
+ MED_REPLY_READ_IN => io_read_in(3),
+
+ MED_DATAREADY_IN => io_dataready_in(1),
+ MED_DATA_IN => io_data_in(31 downto 16),
+ MED_PACKET_NUM_IN => io_packet_num_in(5 downto 3),
+ MED_READ_OUT => io_read_out(1),
+ MED_ERROR_IN => io_error_in,
+
+ -- Internal direction port
+
+ INT_INIT_DATAREADY_OUT => open,
+ INT_INIT_DATA_OUT => open,
+ INT_INIT_PACKET_NUM_OUT => open,
+ INT_INIT_READ_IN => '1',
+
+ INT_INIT_DATAREADY_IN => cri_init_dataready_out,
+ INT_INIT_DATA_IN => cri_init_data_out, -- gbe like data to CRI
+ INT_INIT_PACKET_NUM_IN => cri_init_packet_num_out,
+ INT_INIT_READ_OUT => cri_init_read_in,
+
+ INT_REPLY_DATAREADY_OUT => cri_reply_dataready_in,
+ INT_REPLY_DATA_OUT => cri_reply_data_in, -- answer from CRI
+ INT_REPLY_PACKET_NUM_OUT => cri_reply_packet_num_in,
+ INT_REPLY_READ_IN => cri_reply_read_out,
+
+ INT_REPLY_DATAREADY_IN => '0',
+ INT_REPLY_DATA_IN => (others => '0'),
+ INT_REPLY_PACKET_NUM_IN => (others => '0'),
+ INT_REPLY_READ_OUT => open,
+
+ -- Status and control port
+ STAT_GEN => open,
+ STAT_IBUF_BUFFER => open,
+ CTRL_GEN => (others => '0'),
+ STAT_INIT_OBUF_DEBUG => open,
+ STAT_REPLY_OBUF_DEBUG => open,
+ TIMER_TICKS_IN => TIMER_TICKS_IN
+ );
end generate trbnet_gen;
jspc29 / dirich.git / commitdiff