ModuleName=pll_in100_out25
SourceFormat=Schematic/VHDL
ParameterFileVersion=1.0
-Date=08/16/2010
-Time=18:01:31
+Date=08/19/2010
+Time=13:30:57
[Parameters]
Verilog=0
Order=None
IO=0
Type=ehxpllb
-mode=normal
+mode=advanced
IFrq=100
OFrq=25.000000
KFrq=
SecD=2
fb_mode=CLKOP
PhaseDuty=Static
-DelayControl=AUTO_NO_DELAY
-External=AUTO
+DelayControl=GPLL_NO_DELAY
+External=DISABLED
PCDR=0
ClkOPBp=0
EnCLKOS=0
-- VHDL netlist generated by SCUBA ispLever_v8.1_PROD_Build (20)
-- Module Version: 5.2
---/d/sugar/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -n pll_in100_out25 -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 100 -phase_cntl STATIC -fclkop 25 -fclkop_tol 0.0 -delay_cntl AUTO_NO_DELAY -fb_mode CLOCKTREE -extcap AUTO -noclkos -noclkok -norst -e
+--/d/sugar/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -n pll_in100_out25 -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 100 -phase_cntl STATIC -mdiv 4 -ndiv 1 -vdiv 48 -delay_cntl GPLL_NO_DELAY -fb_mode CLOCKTREE -extcap DISABLED -noclkos -noclkok -norst -e
--- Mon Aug 16 18:01:32 2010
+-- Thu Aug 19 13:30:58 2010
library IEEE;
use IEEE.std_logic_1164.all;
attribute CLKFB_DIV : string;
attribute CLKI_DIV : string;
attribute FIN : string;
- attribute PLLCAP of PLLDInst_0 : label is "AUTO";
- attribute PLLTYPE of PLLDInst_0 : label is "AUTO";
+ attribute PLLCAP of PLLDInst_0 : label is "DISABLED";
+ attribute PLLTYPE of PLLDInst_0 : label is "GPLL";
attribute CLKOK_BYPASS of PLLDInst_0 : label is "DISABLED";
attribute FREQUENCY_PIN_CLKOK of PLLDInst_0 : label is "50.000000";
attribute CLKOK_DIV of PLLDInst_0 : label is "2";
PLLDInst_0: EPLLD
-- synopsys translate_off
- generic map (PLLCAP=> "AUTO", CLKOK_BYPASS=> "DISABLED",
+ generic map (PLLCAP=> "DISABLED", CLKOK_BYPASS=> "DISABLED",
CLKOK_DIV=> 2, CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
PHASE_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", CLKOP_DIV=> 48,
CLKFB_DIV=> 1, CLKI_DIV=> 4)
ModuleName=serdes_fot_full_quad_ctc
SourceFormat=Schematic/VHDL
ParameterFileVersion=1.0
-Date=08/18/2010
-Time=23:30:13
+Date=08/19/2010
+Time=21:29:46
[Parameters]
Verilog=0
RxTermCh1=50
RxTermCh2=50
RxTermCh3=50
-RxCoupCh0=DC
-RxCoupCh1=DC
-RxCoupCh2=DC
-RxCoupCh3=DC
+RxCoupCh0=AC
+RxCoupCh1=AC
+RxCoupCh2=AC
+RxCoupCh3=AC
Loss=0
CDRLoss=0
TxTerm=50
CH1_RTERM_RX "50"
CH2_RTERM_RX "50"
CH3_RTERM_RX "50"
-CH0_RX_DCC "DC"
-CH1_RX_DCC "DC"
-CH2_RX_DCC "DC"
-CH3_RX_DCC "DC"
+CH0_RX_DCC "AC"
+CH1_RX_DCC "AC"
+CH2_RX_DCC "AC"
+CH3_RX_DCC "AC"
LOS_THRESHOLD "0"
PLL_TERM "50"
PLL_DCC "DC"
signal request_cnt_i : unsigned(7 downto 0);
signal reset_rx_control : std_logic;
signal send_reset_words_ext : std_logic;
-
+ signal ffs_plol_low_stable : std_logic;
+ signal ffs_plol_counter : std_logic_vector(18 downto 0);
+ signal tx_lane_reset_q : std_logic;
+ signal tx_lane_reset : std_logic;
begin
-----------------------------------------------------------------------
D_OUT(8) => link_ok_q
);
+ TX_TO_CLK_SYNC: signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 1
+ )
+ port map(
+ RESET => '0',
+ D_IN(0) => tx_lane_reset,
+ CLK0 => CLK_25,
+ CLK1 => CLK,
+ D_OUT(0) => tx_lane_reset_q
+ );
+
SYNC_INPUT_TO_CLK : signal_sync
generic map(
DEPTH => 2,
end if;
end process;
+-----------------------------------------------------------------------
+--TX Reset
+-----------------------------------------------------------------------
+
+ tx_lane_reset <= ffs_plol or quad_rst_qtx or not ffs_plol_low_stable ;
+
+ process(CLK_25)
+ begin
+ if rising_edge(CLK_25) then
+ if ffs_plol = '0' then
+ ffs_plol_low_stable <= '0';
+ ffs_plol_counter <= (others => '0');
+ elsif ffs_plol_counter(18 downto 17) /= "11" then
+ ffs_plol_low_stable <= ffs_plol_counter(18);
+ ffs_plol_counter <= ffs_plol_counter + 1;
+ end if;
+ end if;
+ end process;
+
-----------------------------------------------------------------------
--Debugging
-----------------------------------------------------------------------
signal rx_counter : std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
signal sfp_los : std_logic_vector(3 downto 0);
-signal led_counter : std_logic_vector(15 downto 0);
+signal led_counter : std_logic_vector(14 downto 0);
signal rx_led : std_logic_vector(3 downto 0);
signal tx_led : std_logic_vector(3 downto 0);
signal reset_rx_control : std_logic_vector(3 downto 0);
signal enable_correction_i : std_logic_vector(3 downto 0);
+signal ffs_plol_low_stable : std_logic;
+signal ffs_plol_counter : std_logic_vector(18 downto 0);
+signal tx_lane_reset_q : std_logic_vector(3 downto 0);
+signal tx_lane_reset : std_logic;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
ff_disp_err_ch0 => link_error(0)(0),
ff_cv_ch0 => link_error(0)(1),
ffc_rrst_ch0 => '0',
- ffc_lane_tx_rst_ch0 => lane_rst(0),
+ ffc_lane_tx_rst_ch0 => lane_rst(0),--tx_lane_reset, --
ffc_lane_rx_rst_ch0 => lane_rst(0),
ffc_txpwdnb_ch0 => '1',
ffc_rxpwdnb_ch0 => '1',
);
end generate;
+
+
+-----------------------------------------------------------------------
+--TX Reset
+-----------------------------------------------------------------------
+
+ tx_lane_reset <= ffs_plol or quad_rst_qtx(0) or not ffs_plol_low_stable ;
+
+ process(CLK_25)
+ begin
+ ffs_plol_low_stable <= '0';
+ if rising_edge(CLK_25) then
+ if ffs_plol = '0' then
+ ffs_plol_low_stable <= '0';
+ ffs_plol_counter <= (others => '0');
+ elsif ffs_plol_counter(18 downto 17) /= "11" then
+ ffs_plol_low_stable <= ffs_plol_counter(18);
+ ffs_plol_counter <= ffs_plol_counter + 1;
+ end if;
+ end if;
+ end process;
+
gen_logic : for i in 0 to 3 generate
-----------------------------------------------------------------------
TXCLK_IN => CLK_25,
RXCLK_IN => CLK_25,
SYSCLK_IN => CLK,
- RESET_IN => RESET,
+ RESET_IN => lane_rst(i),
TX_DATA_IN => MED_DATA_IN(i*16+15 downto i*16),
TX_WRITE_IN => MED_DATAREADY_IN(i),
RX_K_IN => rx_k(i),
RX_CV_IN => link_error(i)(1),
RX_DISP_ERR_IN => link_error(i)(0),
- RX_ALLOW_IN => rx_allow_qtx(i),
+ RX_ALLOW_IN => rx_allow(i),
-- media interface
SYSCLK_IN => CLK,
MED_DATA_OUT => buf_med_data_out(i*16+15 downto i*16),
SFP_LOS_IN => sfp_los(i),
SD_LINK_OK_IN => link_ok_q(i),
SD_LOS_IN => link_error_q(i)(2),
- SD_TXCLK_BAD_IN => ffs_plol,
+ SD_TXCLK_BAD_IN => ffs_plol, --
SD_RXCLK_BAD_IN => link_error_q(i)(7),
SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
SD_ALIGNMENT_IN => "10",
RX_TO_CLK_SYNC: signal_sync
generic map(
DEPTH => 2,
- WIDTH => 9
+ WIDTH => 10
)
port map(
RESET => '0',
D_IN(7 downto 0) => link_error(i),
D_IN(8) => link_ok(i),
+ D_IN(9) => tx_lane_reset,
CLK0 => CLK_25,
CLK1 => CLK,
D_OUT(7 downto 0) => link_error_q(i),
- D_OUT(8) => link_ok_q(i)
+ D_OUT(8) => link_ok_q(i),
+ D_OUT(9) => tx_lane_reset_q(i)
);
SYNC_INPUT_TO_CLK : signal_sync
+
-----------------------------------------------------------------------
--STAT & Debug
-----------------------------------------------------------------------
STAT_OP(i*16+7 downto i*16+0) <= FSM_STAT_OP(i*16+7 downto i*16+0);
- STAT_OP(i*16+8) <= start_retransmit_i(i);
+ --STAT_OP(i*16+8) <= start_retransmit_i(i);--signal is registered!
STAT_OP(i*16+9) <= FSM_STAT_OP(i*16+9);
STAT_OP(i*16+10) <= rx_led(i);
STAT_OP(i*16+11) <= tx_led(i);
- STAT_OP(i*16+12) <= request_retransmit_i(i) when CTRL_OP(i*16+8) = '1' else (link_error(i)(1) and not send_reset_words(i) and tx_allow(i));
+ --STAT_OP(i*16+12) <= --signal is registered!
STAT_OP(i*16+13) <= make_trbnet_reset(i);
STAT_OP(i*16+14) <= FSM_STAT_OP(i*16+14);
STAT_OP(i*16+15) <= send_reset_words(i);
process(CLK)
begin
if rising_edge(CLK) then
+ STAT_OP(i*16+8) <= start_retransmit_i(i);
+ if CTRL_OP(i*16+8) = '1' then
+ STAT_OP(i*16+12) <= request_retransmit_i(i);
+ else
+ STAT_OP(i*16+12) <= (link_error(i)(1) and not send_reset_words(i) and tx_allow(i));
+ end if;
+
STAT_DEBUG(i*64+16) <= request_retransmit_i(i);
STAT_DEBUG(i*64+17) <= start_retransmit_i(i);
STAT_DEBUG(i*64+25 downto i*64+18) <= rx_data(i*8+7 downto i*8);
-----------------------------------------------------------------------
--LED Signals
-----------------------------------------------------------------------
- THE_TX_RX_LED_PROC: process( clk_25 )
+ THE_TX_LED_PROC: process( clk_25 )
begin
if( rising_edge(CLK_25) ) then
last_tx_k(i) <= tx_k(i);
- if ( buf_med_dataready_out(i) = '1' ) then
- rx_led(i) <= '1';
- elsif( led_counter = 0 ) then
- rx_led(i) <= '0';
- end if;
if( tx_k(i) = '0' and last_tx_k(i) = '0') then
tx_led(i) <= '1';
elsif led_counter = 0 then
end if;
end process;
+ THE_RX_LED_PROC: process( clk_25 )
+ begin
+ if( rising_edge(CLK_25) ) then
+ if ( buf_med_dataready_out(i) = '1' ) then
+ rx_led(i) <= '1';
+ elsif( led_counter = 0 ) then
+ rx_led(i) <= '0';
+ end if;
+ end if;
+ end process;
end generate;
- PROC_LED_COUNTER: process(CLK)
+ PROC_LED_COUNTER: process(CLK_25)
begin
- if( rising_edge(CLK) ) then
+ if( rising_edge(CLK_25) ) then
led_counter <= led_counter + 1;
end if;
end process PROC_LED_COUNTER;
----------------------------------------------------------------------\r
\r
comma_valid_x <= comma_locked and (comma_idle or comma_error or comma_stx)\r
- and not buf_cv(1) and not buf_cv(0) and not buf_disperr(0) and not buf_disperr(1);\r
+ and not buf_cv(1) and not buf_cv(0) ; --and not buf_disperr(0) and not buf_disperr(1);\r
\r
data_valid_x <= comma_locked and not buf_k(1) and not buf_k(0)\r
- and not buf_cv(1) and not buf_cv(0) and not buf_disperr(0) and not buf_disperr(1);\r
+ and not buf_cv(1) and not buf_cv(0) ; --and not buf_disperr(0) and not buf_disperr(1);\r
\r
fifo_wr_x <= comma_toggle and data_valid_x and not fifo_inhibit;\r
\r
if( rising_edge(CLK_IN) ) then\r
if ( (RESET_IN = '1') or (comma_stx = '1') or ENABLE_CORRECTION_IN = '0') then\r
fifo_inhibit <= '0';\r
- elsif( (comma_locked = '1') and (comma_toggle = '1') and (comma_valid_x = '0') and (data_valid_x = '0') ) then\r
+ elsif( (comma_locked = '1') and (comma_toggle = '1') and (comma_valid_x = '0') and (data_valid_x = '0') and c_reset_x = '0' ) then\r
fifo_inhibit <= '1';\r
end if;\r
end if;\r
\r
library work;\r
use work.trb_net_std.all;\r
---use work.trb_net_components.all;\r
+use work.trb_net_components.all;\r
\r
entity trb_net16_rx_control is\r
port(\r
\r
signal rx_gone_wrong_x : std_logic;\r
signal rx_gone_wrong : std_logic;\r
+signal rx_allow_qrx : std_logic;\r
+signal enable_correction_qrx: std_logic;\r
\r
signal comma_locked : std_logic;\r
\r
RX_K_IN => RX_K_IN,\r
RX_CV_IN => RX_CV_IN,\r
RX_DISP_ERR_IN => RX_DISP_ERR_IN,\r
- RX_ALLOW_IN => RX_ALLOW_IN,\r
+ RX_ALLOW_IN => rx_allow_qrx,\r
-- FIFO interface\r
FIFO_DATA_OUT => fifo_wr_data,\r
FIFO_WR_OUT => fifo_wr_en,\r
-- reset handling\r
SEND_RESET_WORDS_OUT => send_reset_words,\r
MAKE_TRBNET_RESET_OUT => make_trbnet_reset,\r
- ENABLE_CORRECTION_IN => ENABLE_CORRECTION_IN,\r
+ ENABLE_CORRECTION_IN => enable_correction_qrx,\r
-- Debugging\r
DEBUG_OUT => debug_rch\r
);\r
STATE_B_OUT => rx_gone_wrong\r
);\r
\r
+-- clock domain transfer for RX problems\r
+THE_RX_ALLOW_SYNC: signal_sync\r
+generic map(\r
+ DEPTH => 2,\r
+ WIDTH => 2\r
+)\r
+port map(\r
+ RESET => '0',\r
+ D_IN(0) => RX_ALLOW_IN,\r
+ D_IN(1) => ENABLE_CORRECTION_IN,\r
+ CLK0 => CLK_IN,\r
+ CLK1 => CLK_IN,\r
+ D_OUT(0) => rx_allow_qrx,\r
+ D_OUT(1) => enable_correction_qrx\r
+);\r
+\r
+-- THE_RX_ALLOW_SYNC: signal_sync\r
+-- generic map(\r
+-- DEPTH => 2,\r
+-- WIDTH => 1\r
+-- )\r
+-- port map(\r
+-- RESET => '0',\r
+-- D_IN(0) => RX_ALLOW_IN,\r
+-- CLK0 => SYSCLK_IN,\r
+-- CLK1 => SYSCLK_IN,\r
+-- D_OUT(0) => rx_allow_qrx\r
+-- );\r
+\r
+\r
+\r
----------------------------------------------------------------------\r
-- the RX FIFO itself\r
----------------------------------------------------------------------\r
\r
signal debug : std_logic_vector(15 downto 0);\r
\r
+\r
+attribute syn_keep : boolean;\r
+attribute syn_preserve : boolean;\r
+attribute NOMERGE : string;\r
+attribute NOCLIP : string;\r
+\r
+attribute syn_keep of bsm : signal is true;\r
+attribute syn_preserve of bsm : signal is true;\r
+attribute NOMERGE of bsm : signal is "ON";\r
+attribute NOCLIP of bsm : signal is "ON";\r
+attribute syn_keep of bsm_x : signal is true;\r
+attribute syn_preserve of bsm_x : signal is true;\r
+attribute NOMERGE of bsm_x : signal is "ON";\r
+attribute NOCLIP of bsm_x : signal is "ON";\r
+\r
begin\r
\r
----------------------------------------------------------------------\r
signal start_retransmit_i : std_logic;
signal request_retransmit_i : std_logic;
+ signal buf_tx_read_out : std_logic;
signal tx_data_25_i : std_logic_vector(15 downto 0);
signal tx_allow_qtx : std_logic;
signal send_link_reset_qtx : std_logic;
AlmostFull => ct_fifo_afull
);
-TX_READ_OUT <= TX_ALLOW_IN and not ct_fifo_afull ;
-ct_fifo_write<= TX_ALLOW_IN and not ct_fifo_afull and TX_WRITE_IN;
+ THE_RD_PROC : process(SYSCLK_IN)
+ begin
+ if rising_edge(SYSCLK_IN) then
+ buf_tx_read_out <= TX_ALLOW_IN and not ct_fifo_afull ;
+ end if;
+ end process;
+
+TX_READ_OUT <= buf_tx_read_out;
+
+ct_fifo_write<= buf_tx_read_out and TX_WRITE_IN;
ct_fifo_read <= tx_allow_qtx and not ram_afull;
----------------------------------------------------------------------
--RAM empty
- ram_empty <= not or_all(std_logic_vector(ram_write_addr) xor std_logic_vector(ram_read_addr));
- ram_afull <= '1' when ram_fill_level > 5 else '0';
+ ram_empty <= not or_all(std_logic_vector(ram_write_addr) xor std_logic_vector(ram_read_addr)) and not RESET_IN;
+ ram_afull <= '1' when ram_fill_level > 4 else '0';
if current_state = SEND_START_H or
current_state = SEND_IDLE_H or
current_state = SEND_DATA_H or
- current_state = SEND_REQUEST_H then
- if send_link_reset_qtx = '1' then
+ current_state = SEND_REQUEST_H or
+ current_state = SLEEP then
+ if RESET_IN = '1' then
+ current_state <= SEND_IDLE_L;
+ elsif send_link_reset_qtx = '1' then
current_state <= SEND_RESET;
elsif make_request_i = '1' then
current_state <= SEND_REQUEST_L;
#####################################################################
# Test connector
#####################################################################
- LOCATE COMP "TEST_LINE_0" SITE "F7";
- LOCATE COMP "TEST_LINE_1" SITE "D8";
- LOCATE COMP "TEST_LINE_2" SITE "J13";
- LOCATE COMP "TEST_LINE_3" SITE "G11";
- LOCATE COMP "TEST_LINE_4" SITE "H13";
- LOCATE COMP "TEST_LINE_5" SITE "H12";
- LOCATE COMP "TEST_LINE_6" SITE "E8";
- LOCATE COMP "TEST_LINE_7" SITE "D9";
- LOCATE COMP "TEST_LINE_8" SITE "D12";
- LOCATE COMP "TEST_LINE_9" SITE "E13";
- LOCATE COMP "TEST_LINE_10" SITE "J12";
- LOCATE COMP "TEST_LINE_11" SITE "H10";
- LOCATE COMP "TEST_LINE_12" SITE "E12";
- LOCATE COMP "TEST_LINE_13" SITE "D11";
- LOCATE COMP "TEST_LINE_14" SITE "H11";
- LOCATE COMP "TEST_LINE_15" SITE "F11";
-
- DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
- IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVTTL33 PULLMODE=DOWN ;
+# LOCATE COMP "TEST_LINE_0" SITE "F7";
+# LOCATE COMP "TEST_LINE_1" SITE "D8";
+# LOCATE COMP "TEST_LINE_2" SITE "J13";
+# LOCATE COMP "TEST_LINE_3" SITE "G11";
+# LOCATE COMP "TEST_LINE_4" SITE "H13";
+# LOCATE COMP "TEST_LINE_5" SITE "H12";
+# LOCATE COMP "TEST_LINE_6" SITE "E8";
+# LOCATE COMP "TEST_LINE_7" SITE "D9";
+# LOCATE COMP "TEST_LINE_8" SITE "D12";
+# LOCATE COMP "TEST_LINE_9" SITE "E13";
+# LOCATE COMP "TEST_LINE_10" SITE "J12";
+# LOCATE COMP "TEST_LINE_11" SITE "H10";
+# LOCATE COMP "TEST_LINE_12" SITE "E12";
+# LOCATE COMP "TEST_LINE_13" SITE "D11";
+# LOCATE COMP "TEST_LINE_14" SITE "H11";
+# LOCATE COMP "TEST_LINE_15" SITE "F11";
+#
+# DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+# IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVTTL33 PULLMODE=DOWN ;
#####################################################################
proc_retransmit_counters : process(CLK)
begin
if rising_edge(CLK) then
- if MED_STAT_OP(i*16+12) = '1' then
+ if HC_COMMON_CTRL_REGS(5) = '1' then
+ sent_retransmit_requests(i) <= (others => '0');
+ elsif MED_STAT_OP(i*16+12) = '1' then
sent_retransmit_requests(i) <= sent_retransmit_requests(i) + to_unsigned(1,1);
end if;
- if MED_STAT_OP(i*16+8) = '1' then
+ if HC_COMMON_CTRL_REGS(5) = '1' then
+ received_retransmit_requests(i) <= (others => '0');
+ elsif MED_STAT_OP(i*16+8) = '1' then
received_retransmit_requests(i) <= received_retransmit_requests(i) + to_unsigned(1,1);
end if;
end if;
jspc29 / trbnet.git / commitdiff