cleanup, changes to get toggling WS in reset, bug in tx_ctrl still not fixed

diff --git a/media_interfaces/ecp3_sfp/serdes_sync_all_125M_RS.txt b/media_interfaces/ecp3_sfp/serdes_sync_all_125M_RS.txt
index e1b59256e323398c104535190bcfde96e0bcc6a9..29b841d3085e3a727f3f9a3e01baa6259d01d527 100644 (file)
--- a/media_interfaces/ecp3_sfp/serdes_sync_all_125M_RS.txt
+++ b/media_interfaces/ecp3_sfp/serdes_sync_all_125M_RS.txt
@@ -12,10 +12,10 @@ CH0_MODE                "RXTX"
 CH1_MODE                "RXTX"
 CH2_MODE                "RXTX"
 CH3_MODE                "RXTX"
-CH0_CDR_SRC       "REFCLK_CORE"
-CH1_CDR_SRC       "REFCLK_CORE"
-CH2_CDR_SRC       "REFCLK_CORE"
-CH3_CDR_SRC       "REFCLK_CORE"
+CH0_CDR_SRC             "REFCLK_CORE"
+CH1_CDR_SRC             "REFCLK_CORE"
+CH2_CDR_SRC             "REFCLK_CORE"
+CH3_CDR_SRC             "REFCLK_CORE"
 PLL_SRC                 "REFCLK_CORE"
 TX_DATARATE_RANGE       "MED"
 CH0_RX_DATARATE_RANGE   "MED"
@@ -36,30 +36,30 @@ CH0_TX_DATA_WIDTH       "8"
 CH1_TX_DATA_WIDTH       "8"
 CH2_TX_DATA_WIDTH       "8"
 CH3_TX_DATA_WIDTH       "8"
-CH0_RX_DATA_WIDTH        "8"
-CH1_RX_DATA_WIDTH        "8"
-CH2_RX_DATA_WIDTH        "8"
-CH3_RX_DATA_WIDTH        "8"
-CH0_TX_FIFO       "DISABLED"
-CH1_TX_FIFO       "DISABLED"
-CH2_TX_FIFO       "DISABLED"
-CH3_TX_FIFO       "DISABLED"
-CH0_RX_FIFO        "DISABLED"
-CH1_RX_FIFO        "DISABLED"
-CH2_RX_FIFO        "DISABLED"
-CH3_RX_FIFO        "DISABLED"
-CH0_TDRV      "0"
-CH1_TDRV      "0"
-CH2_TDRV      "0"
-CH3_TDRV      "0"
+CH0_RX_DATA_WIDTH       "8"
+CH1_RX_DATA_WIDTH       "8"
+CH2_RX_DATA_WIDTH       "8"
+CH3_RX_DATA_WIDTH       "8"
+CH0_TX_FIFO             "DISABLED"
+CH1_TX_FIFO             "DISABLED"
+CH2_TX_FIFO             "DISABLED"
+CH3_TX_FIFO             "DISABLED"
+CH0_RX_FIFO             "DISABLED"
+CH1_RX_FIFO             "DISABLED"
+CH2_RX_FIFO             "DISABLED"
+CH3_RX_FIFO             "DISABLED"
+CH0_TDRV                "0"
+CH1_TDRV                "0"
+CH2_TDRV                "0"
+CH3_TDRV                "0"
 #CH0_TX_FICLK_RATE      125.0
 #CH1_TX_FICLK_RATE      125.0
 #CH2_TX_FICLK_RATE      125.0
 #CH3_TX_FICLK_RATE      125.0
-#CH0_RXREFCLK_RATE        "125.0"
-#CH1_RXREFCLK_RATE        "125.0"
-#CH2_RXREFCLK_RATE        "125.0"
-#CH3_RXREFCLK_RATE        "125.0"
+#CH0_RXREFCLK_RATE      "125.0"
+#CH1_RXREFCLK_RATE      "125.0"
+#CH2_RXREFCLK_RATE      "125.0"
+#CH3_RXREFCLK_RATE      "125.0"
 #CH0_RX_FICLK_RATE      125.0
 #CH1_RX_FICLK_RATE      125.0
 #CH2_RX_FICLK_RATE      125.0
@@ -84,10 +84,10 @@ CH0_RX_DCC              "AC"
 CH1_RX_DCC              "AC"
 CH2_RX_DCC              "AC"
 CH3_RX_DCC              "AC"
-CH0_LOS_THRESHOLD_LO       "2"
-CH1_LOS_THRESHOLD_LO       "2"
-CH2_LOS_THRESHOLD_LO       "2"
-CH3_LOS_THRESHOLD_LO       "2"
+CH0_LOS_THRESHOLD_LO    "2"
+CH1_LOS_THRESHOLD_LO    "2"
+CH2_LOS_THRESHOLD_LO    "2"
+CH3_LOS_THRESHOLD_LO    "2"
 PLL_TERM                "50"
 PLL_DCC                 "AC"
 PLL_LOL_SET             "0"

diff --git a/media_interfaces/ecp3_sfp/serdes_sync_all_125M_RS.vhd b/media_interfaces/ecp3_sfp/serdes_sync_all_125M_RS.vhd
index b1b599feab7094f4bb56b837daf0f1a9fd71d6e1..faad7914bdf383009e97e32d4a19685339031ce8 100644 (file)
--- a/media_interfaces/ecp3_sfp/serdes_sync_all_125M_RS.vhd
+++ b/media_interfaces/ecp3_sfp/serdes_sync_all_125M_RS.vhd
@@ -1538,6 +1538,7 @@ entity serdes_sync_all_125M_RS is
     hdinp_ch0, hdinn_ch0    :   in std_logic;
     hdoutp_ch0, hdoutn_ch0   :   out std_logic;
     sci_sel_ch0    :   in std_logic;
+    ebrd_clk_ch0    :   in std_logic;
     txiclk_ch0    :   in std_logic;
     rx_full_clk_ch0   :   out std_logic;
     rx_half_clk_ch0   :   out std_logic;
@@ -1568,6 +1569,7 @@ entity serdes_sync_all_125M_RS is
     hdinp_ch1, hdinn_ch1    :   in std_logic;
     hdoutp_ch1, hdoutn_ch1   :   out std_logic;
     sci_sel_ch1    :   in std_logic;
+    ebrd_clk_ch1    :   in std_logic;
     txiclk_ch1    :   in std_logic;
     rx_full_clk_ch1   :   out std_logic;
     rx_half_clk_ch1   :   out std_logic;
@@ -1598,6 +1600,7 @@ entity serdes_sync_all_125M_RS is
     hdinp_ch2, hdinn_ch2    :   in std_logic;
     hdoutp_ch2, hdoutn_ch2   :   out std_logic;
     sci_sel_ch2    :   in std_logic;
+    ebrd_clk_ch2    :   in std_logic;
     txiclk_ch2    :   in std_logic;
     rx_full_clk_ch2   :   out std_logic;
     rx_half_clk_ch2   :   out std_logic;
@@ -1628,6 +1631,7 @@ entity serdes_sync_all_125M_RS is
     hdinp_ch3, hdinn_ch3    :   in std_logic;
     hdoutp_ch3, hdoutn_ch3   :   out std_logic;
     sci_sel_ch3    :   in std_logic;
+    ebrd_clk_ch3    :   in std_logic;
     txiclk_ch3    :   in std_logic;
     rx_full_clk_ch3   :   out std_logic;
     rx_half_clk_ch3   :   out std_logic;
@@ -2308,7 +2312,7 @@ port map  (
   SCIENCH0 => fpsc_vhi,
   FF_RXI_CLK_0 => fpsc_vlo,
   FF_TXI_CLK_0 => txiclk_ch0,
-  FF_EBRD_CLK_0 => fpsc_vlo,
+  FF_EBRD_CLK_0 => ebrd_clk_ch0, --fpsc_vlo,
   FF_RX_F_CLK_0 => rx_full_clk_ch0,
   FF_RX_H_CLK_0 => rx_half_clk_ch0,
   FF_TX_F_CLK_0 => tx_full_clk_ch0_sig,
@@ -2414,7 +2418,7 @@ port map  (
   SCIENCH1 => fpsc_vhi,
   FF_RXI_CLK_1 => fpsc_vlo,
   FF_TXI_CLK_1 => txiclk_ch1,
-  FF_EBRD_CLK_1 => fpsc_vlo,
+  FF_EBRD_CLK_1 => ebrd_clk_ch1, --fpsc_vlo,
   FF_RX_F_CLK_1 => rx_full_clk_ch1,
   FF_RX_H_CLK_1 => rx_half_clk_ch1,
   FF_TX_F_CLK_1 => tx_full_clk_ch1_sig,
@@ -2520,7 +2524,7 @@ port map  (
   SCIENCH2 => fpsc_vhi,
   FF_RXI_CLK_2 => fpsc_vlo,
   FF_TXI_CLK_2 => txiclk_ch2,
-  FF_EBRD_CLK_2 => fpsc_vlo,
+  FF_EBRD_CLK_2 => ebrd_clk_ch2, --fpsc_vlo,
   FF_RX_F_CLK_2 => rx_full_clk_ch2,
   FF_RX_H_CLK_2 => rx_half_clk_ch2,
   FF_TX_F_CLK_2 => tx_full_clk_ch2_sig,
@@ -2626,7 +2630,7 @@ port map  (
   SCIENCH3 => fpsc_vhi,
   FF_RXI_CLK_3 => fpsc_vlo,
   FF_TXI_CLK_3 => txiclk_ch3,
-  FF_EBRD_CLK_3 => fpsc_vlo,
+  FF_EBRD_CLK_3 => ebrd_clk_ch3, --fpsc_vlo,
   FF_RX_F_CLK_3 => rx_full_clk_ch3,
   FF_RX_H_CLK_3 => rx_half_clk_ch3,
   FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,

diff --git a/media_interfaces/ecp3_sfp/serdes_sync_all_200M_RS.txt b/media_interfaces/ecp3_sfp/serdes_sync_all_200M_RS.txt
index f7731349f21029311607e18615b8f39313fb51a9..bed2d748100f400b5b00aa405af8e7028ed88f3a 100644 (file)
--- a/media_interfaces/ecp3_sfp/serdes_sync_all_200M_RS.txt
+++ b/media_interfaces/ecp3_sfp/serdes_sync_all_200M_RS.txt
@@ -12,10 +12,10 @@ CH0_MODE                "RXTX"
 CH1_MODE                "RXTX"
 CH2_MODE                "RXTX"
 CH3_MODE                "RXTX"
-CH0_CDR_SRC       "REFCLK_CORE"
-CH1_CDR_SRC       "REFCLK_CORE"
-CH2_CDR_SRC       "REFCLK_CORE"
-CH3_CDR_SRC       "REFCLK_CORE"
+CH0_CDR_SRC             "REFCLK_CORE"
+CH1_CDR_SRC             "REFCLK_CORE"
+CH2_CDR_SRC             "REFCLK_CORE"
+CH3_CDR_SRC             "REFCLK_CORE"
 PLL_SRC                 "REFCLK_CORE"
 TX_DATARATE_RANGE       "MEDHIGH"
 CH0_RX_DATARATE_RANGE   "MEDHIGH"
@@ -36,30 +36,30 @@ CH0_TX_DATA_WIDTH       "8"
 CH1_TX_DATA_WIDTH       "8"
 CH2_TX_DATA_WIDTH       "8"
 CH3_TX_DATA_WIDTH       "8"
-CH0_RX_DATA_WIDTH        "8"
-CH1_RX_DATA_WIDTH        "8"
-CH2_RX_DATA_WIDTH        "8"
-CH3_RX_DATA_WIDTH        "8"
-CH0_TX_FIFO       "DISABLED"
-CH1_TX_FIFO       "DISABLED"
-CH2_TX_FIFO       "DISABLED"
-CH3_TX_FIFO       "DISABLED"
-CH0_RX_FIFO        "DISABLED"
-CH1_RX_FIFO        "DISABLED"
-CH2_RX_FIFO        "DISABLED"
-CH3_RX_FIFO        "DISABLED"
-CH0_TDRV      "0"
-CH1_TDRV      "0"
-CH2_TDRV      "0"
-CH3_TDRV      "0"
+CH0_RX_DATA_WIDTH       "8"
+CH1_RX_DATA_WIDTH       "8"
+CH2_RX_DATA_WIDTH       "8"
+CH3_RX_DATA_WIDTH       "8"
+CH0_TX_FIFO             "DISABLED"
+CH1_TX_FIFO             "DISABLED"
+CH2_TX_FIFO             "DISABLED"
+CH3_TX_FIFO             "DISABLED"
+CH0_RX_FIFO             "DISABLED"
+CH1_RX_FIFO             "DISABLED"
+CH2_RX_FIFO             "DISABLED"
+CH3_RX_FIFO             "DISABLED"
+CH0_TDRV                "0"
+CH1_TDRV                "0"
+CH2_TDRV                "0"
+CH3_TDRV                "0"
 #CH0_TX_FICLK_RATE      200
 #CH1_TX_FICLK_RATE      200
 #CH2_TX_FICLK_RATE      200
 #CH3_TX_FICLK_RATE      200
-#CH0_RXREFCLK_RATE        "200"
-#CH1_RXREFCLK_RATE        "200"
-#CH2_RXREFCLK_RATE        "200"
-#CH3_RXREFCLK_RATE        "200"
+#CH0_RXREFCLK_RATE      "200"
+#CH1_RXREFCLK_RATE      "200"
+#CH2_RXREFCLK_RATE      "200"
+#CH3_RXREFCLK_RATE      "200"
 #CH0_RX_FICLK_RATE      200
 #CH1_RX_FICLK_RATE      200
 #CH2_RX_FICLK_RATE      200
@@ -84,10 +84,10 @@ CH0_RX_DCC              "AC"
 CH1_RX_DCC              "AC"
 CH2_RX_DCC              "AC"
 CH3_RX_DCC              "AC"
-CH0_LOS_THRESHOLD_LO       "2"
-CH1_LOS_THRESHOLD_LO       "2"
-CH2_LOS_THRESHOLD_LO       "2"
-CH3_LOS_THRESHOLD_LO       "2"
+CH0_LOS_THRESHOLD_LO    "2"
+CH1_LOS_THRESHOLD_LO    "2"
+CH2_LOS_THRESHOLD_LO    "2"
+CH3_LOS_THRESHOLD_LO    "2"
 PLL_TERM                "50"
 PLL_DCC                 "AC"
 PLL_LOL_SET             "0"

diff --git a/media_interfaces/ecp3_sfp/serdes_sync_all_200M_RS.vhd b/media_interfaces/ecp3_sfp/serdes_sync_all_200M_RS.vhd
index 4cfb549a744d524f3c78f810fe8bbb4dfad54cae..2779fa87599983c43d6730d26a2e0dbda618fe60 100644 (file)
--- a/media_interfaces/ecp3_sfp/serdes_sync_all_200M_RS.vhd
+++ b/media_interfaces/ecp3_sfp/serdes_sync_all_200M_RS.vhd
@@ -1538,6 +1538,7 @@ entity serdes_sync_all_200M_RS is
     hdinp_ch0, hdinn_ch0    :   in std_logic;
     hdoutp_ch0, hdoutn_ch0   :   out std_logic;
     sci_sel_ch0    :   in std_logic;
+    ebrd_clk_ch0    :   in std_logic;
     txiclk_ch0    :   in std_logic;
     rx_full_clk_ch0   :   out std_logic;
     rx_half_clk_ch0   :   out std_logic;
@@ -1568,6 +1569,7 @@ entity serdes_sync_all_200M_RS is
     hdinp_ch1, hdinn_ch1    :   in std_logic;
     hdoutp_ch1, hdoutn_ch1   :   out std_logic;
     sci_sel_ch1    :   in std_logic;
+    ebrd_clk_ch1    :   in std_logic;
     txiclk_ch1    :   in std_logic;
     rx_full_clk_ch1   :   out std_logic;
     rx_half_clk_ch1   :   out std_logic;
@@ -1598,6 +1600,7 @@ entity serdes_sync_all_200M_RS is
     hdinp_ch2, hdinn_ch2    :   in std_logic;
     hdoutp_ch2, hdoutn_ch2   :   out std_logic;
     sci_sel_ch2    :   in std_logic;
+    ebrd_clk_ch2    :   in std_logic;
     txiclk_ch2    :   in std_logic;
     rx_full_clk_ch2   :   out std_logic;
     rx_half_clk_ch2   :   out std_logic;
@@ -1628,6 +1631,7 @@ entity serdes_sync_all_200M_RS is
     hdinp_ch3, hdinn_ch3    :   in std_logic;
     hdoutp_ch3, hdoutn_ch3   :   out std_logic;
     sci_sel_ch3    :   in std_logic;
+    ebrd_clk_ch3    :   in std_logic;
     txiclk_ch3    :   in std_logic;
     rx_full_clk_ch3   :   out std_logic;
     rx_half_clk_ch3   :   out std_logic;
@@ -2308,7 +2312,7 @@ port map  (
   SCIENCH0 => fpsc_vhi,
   FF_RXI_CLK_0 => fpsc_vlo,
   FF_TXI_CLK_0 => txiclk_ch0,
-  FF_EBRD_CLK_0 => fpsc_vlo,
+  FF_EBRD_CLK_0 => ebrd_clk_ch0, --fpsc_vlo,
   FF_RX_F_CLK_0 => rx_full_clk_ch0,
   FF_RX_H_CLK_0 => rx_half_clk_ch0,
   FF_TX_F_CLK_0 => tx_full_clk_ch0_sig,
@@ -2414,7 +2418,7 @@ port map  (
   SCIENCH1 => fpsc_vhi,
   FF_RXI_CLK_1 => fpsc_vlo,
   FF_TXI_CLK_1 => txiclk_ch1,
-  FF_EBRD_CLK_1 => fpsc_vlo,
+  FF_EBRD_CLK_1 => ebrd_clk_ch1, --fpsc_vlo,
   FF_RX_F_CLK_1 => rx_full_clk_ch1,
   FF_RX_H_CLK_1 => rx_half_clk_ch1,
   FF_TX_F_CLK_1 => tx_full_clk_ch1_sig,
@@ -2520,7 +2524,7 @@ port map  (
   SCIENCH2 => fpsc_vhi,
   FF_RXI_CLK_2 => fpsc_vlo,
   FF_TXI_CLK_2 => txiclk_ch2,
-  FF_EBRD_CLK_2 => fpsc_vlo,
+  FF_EBRD_CLK_2 => ebrd_clk_ch2, --fpsc_vlo,
   FF_RX_F_CLK_2 => rx_full_clk_ch2,
   FF_RX_H_CLK_2 => rx_half_clk_ch2,
   FF_TX_F_CLK_2 => tx_full_clk_ch2_sig,
@@ -2626,7 +2630,7 @@ port map  (
   SCIENCH3 => fpsc_vhi,
   FF_RXI_CLK_3 => fpsc_vlo,
   FF_TXI_CLK_3 => txiclk_ch3,
-  FF_EBRD_CLK_3 => fpsc_vlo,
+  FF_EBRD_CLK_3 => ebrd_clk_ch3, --fpsc_vlo,
   FF_RX_F_CLK_3 => rx_full_clk_ch3,
   FF_RX_H_CLK_3 => rx_half_clk_ch3,
   FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,

diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
index 2ded66af4d38d46fc367ecbaf7d26c69b946e575..bf27340acf6b5bd59fc50977d5810cd8b4961876 100644 (file)
--- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
@@ -304,6 +304,7 @@ gen_SERDES: if LINK_SPEED = 125 generate
       hdinn_ch0            => hdinn(0),
       hdoutp_ch0           => hdoutp(0),
       hdoutn_ch0           => hdoutn(0),
+      ebrd_clk_ch0         => clk_tx_full(0), -- HACK
       txiclk_ch0           => clk_tx_full(0), -- drives TX FIFO bridge
       rx_full_clk_ch0      => clk_rx_full(0), -- recovered RX clock
       rx_half_clk_ch0      => clk_rx_half(0),
@@ -335,6 +336,7 @@ gen_SERDES: if LINK_SPEED = 125 generate
       hdinn_ch1            => hdinn(1),
       hdoutp_ch1           => hdoutp(1),
       hdoutn_ch1           => hdoutn(1),
+      ebrd_clk_ch1         => clk_tx_full(1), -- HACK
       txiclk_ch1           => clk_tx_full(1),
       rx_full_clk_ch1      => clk_rx_full(1),
       rx_half_clk_ch1      => clk_rx_half(1),
@@ -366,6 +368,7 @@ gen_SERDES: if LINK_SPEED = 125 generate
       hdinn_ch2            => hdinn(2),
       hdoutp_ch2           => hdoutp(2),
       hdoutn_ch2           => hdoutn(2),
+      ebrd_clk_ch2         => clk_tx_full(2), -- HACK
       txiclk_ch2           => clk_tx_full(2),
       rx_full_clk_ch2      => clk_rx_full(2),
       rx_half_clk_ch2      => clk_rx_half(2),
@@ -397,6 +400,7 @@ gen_SERDES: if LINK_SPEED = 125 generate
       hdinn_ch3            => hdinn(3),
       hdoutp_ch3           => hdoutp(3),
       hdoutn_ch3           => hdoutn(3),
+      ebrd_clk_ch3         => clk_tx_full(3), -- HACK
       txiclk_ch3           => clk_tx_full(3),
       rx_full_clk_ch3      => clk_rx_full(3),
       rx_half_clk_ch3      => clk_rx_half(3),
@@ -451,6 +455,7 @@ gen_SERDES: if LINK_SPEED = 200 generate
       hdinn_ch0            => hdinn(0),
       hdoutp_ch0           => hdoutp(0),
       hdoutn_ch0           => hdoutn(0),
+      ebrd_clk_ch0         => clk_tx_full(0), -- HACK
       txiclk_ch0           => clk_tx_full(0), -- drives TX FIFO bridge
       rx_full_clk_ch0      => clk_rx_full(0), -- recovered RX clock
       rx_half_clk_ch0      => clk_rx_half(0),
@@ -482,6 +487,7 @@ gen_SERDES: if LINK_SPEED = 200 generate
       hdinn_ch1            => hdinn(1),
       hdoutp_ch1           => hdoutp(1),
       hdoutn_ch1           => hdoutn(1),
+      ebrd_clk_ch1         => clk_tx_full(1), -- HACK
       txiclk_ch1           => clk_tx_full(1),
       rx_full_clk_ch1      => clk_rx_full(1),
       rx_half_clk_ch1      => clk_rx_half(1),
@@ -513,6 +519,7 @@ gen_SERDES: if LINK_SPEED = 200 generate
       hdinn_ch2            => hdinn(2),
       hdoutp_ch2           => hdoutp(2),
       hdoutn_ch2           => hdoutn(2),
+      ebrd_clk_ch2         => clk_tx_full(2), -- HACK
       txiclk_ch2           => clk_tx_full(2),
       rx_full_clk_ch2      => clk_rx_full(2),
       rx_half_clk_ch2      => clk_rx_half(2),
@@ -544,6 +551,7 @@ gen_SERDES: if LINK_SPEED = 200 generate
       hdinn_ch3            => hdinn(3),
       hdoutp_ch3           => hdoutp(3),
       hdoutn_ch3           => hdoutn(3),
+      ebrd_clk_ch3         => clk_tx_full(3), -- HACK
       txiclk_ch3           => clk_tx_full(3),
       rx_full_clk_ch3      => clk_rx_full(3),
       rx_half_clk_ch3      => clk_rx_half(3),

diff --git a/media_interfaces/sync/rx_control_RS.vhd b/media_interfaces/sync/rx_control_RS.vhd
index 7580347b4e9881b2afab13456e0cea02b2cb4b3b..4e1ff2cdef78234ccc4d8799ea1c1debf8f68379 100644 (file)
--- a/media_interfaces/sync/rx_control_RS.vhd
+++ b/media_interfaces/sync/rx_control_RS.vhd
@@ -191,12 +191,13 @@ begin
         link_rx_null_i        <= '1';\r
         if( (reg_rx_k_in = '1') and (reg_rx_data_in = K_IDLE) and (link_rx_ready_qrx = '1') ) then\r
           rx_state            <= WAIT_1;\r
-          sync_k_i            <= '1';\r
+          sync_k_i            <= not sync_k_i; --'1'; -- HACK for toggling during reset\r
         end if;\r
 \r
       when WAIT_1 =>\r
         -- and skip the data byte\r
         rx_state <= FIRST;\r
+        sync_k_i <= '0'; -- HACK for toggling during reset\r
 \r
       when FIRST =>\r
         rx_state_bits         <= x"2";\r

diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd
index 29defa79529647c6e7703fbfdfc1c45c2fc8e459..ef561ceb480bde776c3fd8d1a70ae677b71c142c 100644 (file)
--- a/media_interfaces/sync/tx_control_RS.vhd
+++ b/media_interfaces/sync/tx_control_RS.vhd
@@ -323,7 +323,7 @@ begin
           elsif( link_tx_null_qtx = '1' ) then\r
             current_state     <= SEND_NULL_L;\r
           elsif( send_dlm_i = '1' ) then\r
-            current_state     <= SEND_DLM_L;\r
+            current_state     <= SEND_DLM_L; -- BUG!!! may interrupt reset sequence!!!\r
           elsif( send_rst_i = '1' ) then\r
             current_state     <= SEND_RST_L;\r
           elsif( ram_empty = '0' ) then\r

diff --git a/special/statistics.vhd b/special/statistics.vhd
index cc533f4614b07e8dce6c20fd3a587ecb89444959..24f88a019570bde530466300d1df8df57cf2b40d 100644 (file)
--- a/special/statistics.vhd
+++ b/special/statistics.vhd
@@ -4,19 +4,23 @@ use ieee.numeric_std.all;
 
 entity statistics is
 port( 
-  AUXCLK          : in  std_logic;
-  RESET           : in  std_logic;
-  DELAY_VALUE_IN  : in  std_logic_vector(9 downto 0);
-  DELAY_VALID_IN  : in  std_logic;
-  FSM_START_IN    : in  std_logic;
-  FSM_CLR_DONE_IN : in  std_logic;
-  FSM_ACTIVE_OUT  :  out std_logic;
-  FSM_CE_OUT      : out std_logic;
-  FSM_RST_OUT     : out std_logic;
-  FSM_DONE_OUT    : out  std_logic;
-  RD_CLK          : in  std_logic;
-  RD_ADDRESS_IN   : in  std_logic_vector(9 downto 0);
-  RD_DATA_OUT     : out  std_logic_vector(17 downto 0)
+  AUXCLK           : in  std_logic;
+  RESET            : in  std_logic;
+  DELAY_CLK        : in  std_logic;
+  DELAY_START_IN   : in  std_logic;
+  DELAY_STOP_IN    : in  std_logic;
+  DELAY_COARSE_OUT : out std_logic_vector(31 downto 0);
+  DELAY_VALUE_IN   : in  std_logic_vector(9 downto 0);
+  DELAY_VALID_IN   : in  std_logic;
+  FSM_START_IN     : in  std_logic;
+  FSM_CLR_DONE_IN  : in  std_logic;
+  FSM_ACTIVE_OUT   :  out std_logic;
+  FSM_CE_OUT       : out std_logic;
+  FSM_RST_OUT      : out std_logic;
+  FSM_DONE_OUT     : out  std_logic;
+  RD_CLK           : in  std_logic;
+  RD_ADDRESS_IN    : in  std_logic_vector(9 downto 0);
+  RD_DATA_OUT      : out  std_logic_vector(17 downto 0)
 );
 end;
 
@@ -55,6 +59,9 @@ architecture behavioural of statistics is
   signal mean_sum_x       : unsigned(31 downto 0);
   signal mean_sum_q       : unsigned(31 downto 0);
 
+  signal coarse_counter : unsigned(31 downto 0);
+  signal coarse_delay   : std_logic_vector(31 downto 0);
+  
   component statmem is
   port(
     DATAINA   : in  std_logic_vector(17 downto 0); 
@@ -81,6 +88,25 @@ attribute HGROUP of behavioural: architecture is "statistics";
 
 begin
 
+---------------------------------------------------------------------------
+-- coarse delay measurement, based on TX clock
+---------------------------------------------------------------------------
+THE_COARSE_COUNTER_PROC: process( DELAY_CLK )
+begin
+  if( rising_edge(DELAY_CLK) ) then
+    if( DELAY_START_IN = '1' ) then
+      coarse_counter <= (others => '0');
+    else
+      coarse_counter <= coarse_counter + 1;
+    end if;
+    if( DELAY_STOP_IN = '1' ) then
+      coarse_delay <= std_logic_vector(coarse_counter);
+    end if;
+  end if;
+end process THE_COARSE_COUNTER_PROC;
+
+DELAY_COARSE_OUT <= coarse_delay;
+
 -----------------------------------------------------------
 -- statemachine: clocked process
 -----------------------------------------------------------