--- /dev/null
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.numeric_std.all;
+
+library work;
+
+
+
+entity fifo_19x16_obuf is
+port(
+ Data : in std_logic_vector(18 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ AmFullThresh : in std_logic_vector(3 downto 0);
+ Q : out std_logic_vector(18 downto 0);
+ WCNT : out std_logic_vector(4 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostFull : out std_logic
+);
+end entity;
+
+
+
+
+
+architecture fifo_19x16_obuf_arch of fifo_19x16_obuf is
+
+
+
+component xilinx_19x16_obuf IS
+port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(18 downto 0);
+ prog_full_thresh: IN std_logic_VECTOR(3 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ data_count: OUT std_logic_VECTOR(3 downto 0);
+ dout: OUT std_logic_VECTOR(18 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ prog_full: OUT std_logic
+);
+END component;
+
+
+
+begin
+
+
+the_FIFO: xilinx_19x16_obuf
+port map(
+ clk => Clock,
+ din => Data,
+ prog_full_thresh => AmFullThresh,
+ rd_en => RdEn,
+ rst => Reset,
+ wr_en => WrEn,
+ data_count => WCNT(3 downto 0),
+ dout => Q,
+ empty => Empty,
+ full => Full,
+ prog_full => AlmostFull
+);
+
+WCNT(4) <= '0';
+
+end architecture;
\ No newline at end of file
--- /dev/null
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used --
+-- solely for design, simulation, implementation and creation of --
+-- design files limited to Xilinx devices or technologies. Use --
+-- with non-Xilinx devices or technologies is expressly prohibited --
+-- and immediately terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
+-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
+-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
+-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
+-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
+-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
+-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
+-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
+-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
+-- FOR A PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support --
+-- appliances, devices, or systems. Use in such applications are --
+-- expressly prohibited. --
+-- --
+-- (c) Copyright 1995-2007 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file xilinx_19x16_obuf.vhd when simulating
+-- the core, xilinx_19x16_obuf. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY xilinx_19x16_obuf IS
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(18 downto 0);
+ prog_full_thresh: IN std_logic_VECTOR(3 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ data_count: OUT std_logic_VECTOR(3 downto 0);
+ dout: OUT std_logic_VECTOR(18 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ prog_full: OUT std_logic);
+END xilinx_19x16_obuf;
+
+ARCHITECTURE xilinx_19x16_obuf_a OF xilinx_19x16_obuf IS
+-- synthesis translate_off
+component wrapped_xilinx_19x16_obuf
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(18 downto 0);
+ prog_full_thresh: IN std_logic_VECTOR(3 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ data_count: OUT std_logic_VECTOR(3 downto 0);
+ dout: OUT std_logic_VECTOR(18 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ prog_full: OUT std_logic);
+end component;
+
+-- Configuration specification
+ for all : wrapped_xilinx_19x16_obuf use entity XilinxCoreLib.fifo_generator_v4_2(behavioral)
+ generic map(
+ c_has_int_clk => 0,
+ c_rd_freq => 1,
+ c_wr_response_latency => 1,
+ c_has_srst => 0,
+ c_has_rd_data_count => 0,
+ c_din_width => 19,
+ c_has_wr_data_count => 0,
+ c_full_flags_rst_val => 1,
+ c_implementation_type => 0,
+ c_family => "virtex4",
+ c_use_embedded_reg => 1,
+ c_has_wr_rst => 0,
+ c_wr_freq => 1,
+ c_use_dout_rst => 0,
+ c_underflow_low => 0,
+ c_has_meminit_file => 0,
+ c_has_overflow => 0,
+ c_preload_latency => 2,
+ c_dout_width => 19,
+ c_rd_depth => 16,
+ c_default_value => "BlankString",
+ c_mif_file_name => "BlankString",
+ c_has_underflow => 0,
+ c_has_rd_rst => 0,
+ c_has_almost_full => 0,
+ c_has_rst => 1,
+ c_data_count_width => 4,
+ c_has_wr_ack => 0,
+ c_use_ecc => 0,
+ c_wr_ack_low => 0,
+ c_common_clock => 1,
+ c_rd_pntr_width => 4,
+ c_use_fwft_data_count => 0,
+ c_has_almost_empty => 0,
+ c_rd_data_count_width => 4,
+ c_enable_rlocs => 0,
+ c_wr_pntr_width => 4,
+ c_overflow_low => 0,
+ c_prog_empty_type => 0,
+ c_optimization_mode => 0,
+ c_wr_data_count_width => 4,
+ c_preload_regs => 1,
+ c_dout_rst_val => "0",
+ c_has_data_count => 1,
+ c_prog_full_thresh_negate_val => 13,
+ c_wr_depth => 16,
+ c_prog_empty_thresh_negate_val => 3,
+ c_prog_empty_thresh_assert_val => 2,
+ c_has_valid => 0,
+ c_init_wr_pntr_val => 0,
+ c_prog_full_thresh_assert_val => 14,
+ c_use_fifo16_flags => 0,
+ c_has_backup => 0,
+ c_valid_low => 0,
+ c_prim_fifo_type => "512x36",
+ c_count_type => 0,
+ c_prog_full_type => 3,
+ c_memory_type => 1);
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_xilinx_19x16_obuf
+ port map (
+ clk => clk,
+ din => din,
+ prog_full_thresh => prog_full_thresh,
+ rd_en => rd_en,
+ rst => rst,
+ wr_en => wr_en,
+ data_count => data_count,
+ dout => dout,
+ empty => empty,
+ full => full,
+ prog_full => prog_full);
+-- synthesis translate_on
+
+END xilinx_19x16_obuf_a;
+
--- /dev/null
+##############################################################
+#
+# Xilinx Core Generator version J.40
+# Date: Tue Oct 19 14:19:54 2010
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = True
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc4vlx40
+SET devicefamily = virtex4
+SET flowvendor = Foundation_iSE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = ff1148
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -10
+SET verilogsim = True
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 4.2
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=xilinx_19x16_obuf
+CSET data_count=true
+CSET data_count_width=4
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=2
+CSET empty_threshold_negate_value=3
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET fifo_implementation=Common_Clock_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=14
+CSET full_threshold_negate_value=13
+CSET input_data_width=19
+CSET input_depth=16
+CSET output_data_width=19
+CSET output_depth=16
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=Standard_FIFO
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=Single_Programmable_Full_Threshold_Input_Port
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=4
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=false
+CSET use_embedded_registers=true
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=4
+# END Parameters
+GENERATE
+# CRC: e6f9f439
+
jspc29 / trbnet.git / commitdiff