add hub status register 0x80++ to data bus at 4180++

diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd
index e93ea4a4a0f592c722d7798d61ee7bd7fbdfbfcc..90d256ac3ba4c86838f4b73d0a0242bc94868d1f 100644 (file)
--- a/trb_net16_hub_base.vhd
+++ b/trb_net16_hub_base.vhd
@@ -243,7 +243,6 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is
   signal reset_i_mux_io : std_logic_vector((MII_NUMBER*2**(c_MUX_WIDTH-1))-1 downto 0);
   signal reset_i_tmp : std_logic;
 
-
   signal combined_resync : std_logic;
   signal IDRAM_DATA_IN, IDRAM_DATA_OUT : std_logic_vector(15 downto 0);
   signal IDRAM_WR_IN : std_logic;
@@ -323,7 +322,14 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is
   signal busaddr_datatx   : std_logic_vector(31 downto 0);
   signal busaddr_rack     : std_logic;
   signal busaddr_wack     : std_logic;
-  
+
+  signal busstat_addr     : std_logic_vector(15 downto 0);
+  signal busstat_read     : std_logic;
+  signal busstat_write    : std_logic;
+  signal busstat_datarx   : std_logic_vector(31 downto 0);
+  signal busstat_datatx   : std_logic_vector(31 downto 0);
+  signal busstat_rack     : std_logic;
+ 
   signal stat_globaltime_read      : std_logic;
   signal stat_globaltime_write     : std_logic;
   signal last_stat_globaltime_read : std_logic;
@@ -375,6 +381,7 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is
   signal tmp_buf_to_hub_REPLY_DATA_ctrl : std_logic_vector(15 downto 0);
   signal CONF_addresses : std_logic_vector(31 downto 0);
   signal CONF_generic   : std_logic_vector(7 downto 0);
+  signal i2c_status     : std_logic_vector(31 downto 0);
 
   attribute syn_preserve : boolean;
   attribute syn_keep : boolean;
@@ -414,14 +421,15 @@ begin
   proc_SYNC_RESET : process(CLK)
     begin
       if rising_edge(CLK) then
-        reset_i_tmp <= RESET;
         last_STAT_TIMEOUT <= STAT_TIMEOUT;
       end if;
     end process;
 
   gen_resetedge : if FPGA_TYPE = 5 generate  --timing via primary clock net gives hold violations for BRAM
+    reset_i_tmp <= RESET;
     reset_i <= reset_i_tmp when falling_edge(CLK);
   else generate
+    reset_i_tmp <= RESET;
     reset_i <= reset_i_tmp when rising_edge(CLK);
   end generate;
     
@@ -1156,12 +1164,11 @@ end generate;
   BUS_MASTER_IN.data    <= DAT_DATA_IN;
   
   
---Fucking Modelsim wants it like this...
 THE_BUS_HANDLER : trb_net16_regio_bus_handler
   generic map(
-    PORT_NUMBER    => 8,
-    PORT_ADDRESSES => (0 => x"0000", 1 => x"4000", 2 => x"4020", 3 => x"4030", 4 => x"4040", 5 => x"4050", 6 => x"4060", 7 => x"7000", others => x"0000"),
-    PORT_ADDR_MASK => (0 => 16,      1 => 5,       2 => 4,       3 => 4,       4 => 4,       5 => 0,       6 => 4,       7 => 1,       others => 0),
+    PORT_NUMBER    => 9,
+    PORT_ADDRESSES => (0 => x"0000", 1 => x"4000", 2 => x"4020", 3 => x"4030", 4 => x"4040", 5 => x"4050", 6 => x"4060", 7 => x"7000", 8 => x"4180", others => x"0000"),
+    PORT_ADDR_MASK => (0 => 16,      1 => 5,       2 => 4,       3 => 4,       4 => 4,       5 => 0,       6 => 4,       7 => 1,       8 => 6,       others => 0),
     PORT_MASK_ENABLE => 0
     )
   port map(
@@ -1193,6 +1200,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler
     BUS_ADDR_OUT(99 downto 96)   => lsm_addr,
     BUS_ADDR_OUT(111 downto 100) => dummy(72 downto 61),
     BUS_ADDR_OUT(112 downto 112) => busaddr_addr(0 downto 0),
+    BUS_ADDR_OUT(133 downto 128) => busstat_addr(5 downto 0),
     BUS_DATA_IN(31 downto 0)     => REGIO_DATA_IN,
     BUS_DATA_IN(63 downto 32)    => stat_packets_data,
     BUS_DATA_IN(95 downto 64)    => stat_errorbits_data,
@@ -1201,6 +1209,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler
     BUS_DATA_IN(191 downto 160)  => global_time,
     BUS_DATA_IN(223 downto 192)  => lsm_data,
     BUS_DATA_IN(255 downto 224)  => busaddr_datatx,    
+    BUS_DATA_IN(287 downto 256)  => busstat_datatx,
     BUS_DATA_OUT(31 downto 0)    => REGIO_DATA_OUT,
     BUS_DATA_OUT(63 downto 32)   => dummy(104 downto 73),
     BUS_DATA_OUT(95 downto 64)   => dummy(136 downto 105),
@@ -1209,6 +1218,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler
     BUS_DATA_OUT(191 downto 160) => dummy(232 downto 201),
     BUS_DATA_OUT(223 downto 192) => dummy(264 downto 233),
     BUS_DATA_OUT(255 downto 224) => busaddr_datarx,
+    BUS_DATA_OUT(287 downto 256) => busstat_datarx,    
     BUS_DATAREADY_IN(0)          => REGIO_DATAREADY_IN,
     BUS_DATAREADY_IN(1)          => stat_packets_ready,
     BUS_DATAREADY_IN(2)          => stat_errorbits_ready,
@@ -1217,6 +1227,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler
     BUS_DATAREADY_IN(5)          => last_stat_globaltime_read,
     BUS_DATAREADY_IN(6)          => last_lsm_read,
     BUS_DATAREADY_IN(7)          => busaddr_rack,
+    BUS_DATAREADY_IN(8)          => busstat_rack,
     BUS_NO_MORE_DATA_IN(0)       => REGIO_NO_MORE_DATA_IN,
     BUS_NO_MORE_DATA_IN(1)       => '0',
     BUS_NO_MORE_DATA_IN(2)       => '0',
@@ -1225,6 +1236,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler
     BUS_NO_MORE_DATA_IN(5)       => '0',
     BUS_NO_MORE_DATA_IN(6)       => '0',
     BUS_NO_MORE_DATA_IN(7)       => '0',
+    BUS_NO_MORE_DATA_IN(8)       => '0',
     BUS_READ_ENABLE_OUT(0)       => REGIO_READ_ENABLE_OUT,
     BUS_READ_ENABLE_OUT(1)       => stat_packets_read,
     BUS_READ_ENABLE_OUT(2)       => stat_errorbits_read,
@@ -1233,6 +1245,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler
     BUS_READ_ENABLE_OUT(5)       => stat_globaltime_read,
     BUS_READ_ENABLE_OUT(6)       => lsm_read,
     BUS_READ_ENABLE_OUT(7)       => busaddr_read,    
+    BUS_READ_ENABLE_OUT(8)       => busstat_read,    
     BUS_TIMEOUT_OUT(0)           => REGIO_TIMEOUT_OUT,
     BUS_TIMEOUT_OUT(1)           => dummy(265),
     BUS_TIMEOUT_OUT(2)           => dummy(266),
@@ -1248,6 +1261,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler
     BUS_UNKNOWN_ADDR_IN(5)       => last_stat_globaltime_write,
     BUS_UNKNOWN_ADDR_IN(6)       => lsm_write,
     BUS_UNKNOWN_ADDR_IN(7)       => '0',
+    BUS_UNKNOWN_ADDR_IN(8)       => busstat_write,
     BUS_WRITE_ACK_IN(0)          => REGIO_WRITE_ACK_IN,
     BUS_WRITE_ACK_IN(1)          => stat_packets_ack,
     BUS_WRITE_ACK_IN(2)          => '0',
@@ -1256,6 +1270,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler
     BUS_WRITE_ACK_IN(5)          => '0',
     BUS_WRITE_ACK_IN(6)          => '0',
     BUS_WRITE_ACK_IN(7)          => busaddr_wack,
+    BUS_WRITE_ACK_IN(8)          => '0',
     BUS_WRITE_ENABLE_OUT(0)      => REGIO_WRITE_ENABLE_OUT,
     BUS_WRITE_ENABLE_OUT(1)      => stat_packets_write,
     BUS_WRITE_ENABLE_OUT(2)      => stat_errorbits_write,
@@ -1264,6 +1279,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler
     BUS_WRITE_ENABLE_OUT(5)      => stat_globaltime_write,
     BUS_WRITE_ENABLE_OUT(6)      => lsm_write,
     BUS_WRITE_ENABLE_OUT(7)      => busaddr_write,
+    BUS_WRITE_ENABLE_OUT(8)      => busstat_write,
     STAT_DEBUG  => open
     );
 
@@ -1331,11 +1347,10 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler
         WRITE_OUT         => ONEWIRE_WRITE,
         TEMP_OUT          => TEMP_OUT,
         ID_OUT            => UNIQUE_ID_OUT,                
-        STAT              => open
+        STAT              => i2c_status
         );
   end generate;  
   
-  
 -------------------------------------------------
 -- Include variable Endpoint ID
 -------------------------------------------------
@@ -1394,6 +1409,17 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1');
       end if;  
     end if;
   end process;     
+
+
+  proc_status : process begin
+    wait until rising_edge(CLK);
+    busstat_rack <= '0';
+    if busstat_read = '1' then
+      busstat_rack <= '1';
+      busstat_datatx <= HC_STAT_REGS(to_integer(unsigned(busstat_addr(5 downto 0)))*32+31 downto to_integer(unsigned(busstat_addr(5 downto 0)))*32);
+    end if;
+  end process;
+  
   
   gen_timeout_values : for k in 0 to 3 generate
     proc_get_timeout_value : process(CLK)
@@ -1835,8 +1861,8 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1');
 --   buf_STAT_DEBUG(6 downto 4)  <= hub_to_buf_INIT_DATA(2**(c_MUX_WIDTH-1)*MII_NUMBER*16+2 downto 2**(c_MUX_WIDTH-1)*MII_NUMBER*16);
 --   buf_STAT_DEBUG(7)  <= buf_HUB_STAT_CHANNEL(3*16+1);
 --   
---   buf_STAT_DEBUG(8)  <= reset_i_mux_io(2*MII_NUMBER+6);
---   buf_STAT_DEBUG(9)  <= reset_i_mux_io(3*MII_NUMBER+6);
+  buf_STAT_DEBUG(8)  <= reset_i_mux_io(1);
+  buf_STAT_DEBUG(9)  <= reset_i_mux_io(2);
 --   buf_STAT_DEBUG(10) <= HUB_CTRL_final_activepoints(3*32+6);
 --   buf_STAT_DEBUG(11) <= STAT_TIMEOUT(3*32+6);
 --   buf_STAT_DEBUG(12) <= buf_to_hub_REPLY_DATAREADY(6*4+3);

diff --git a/trb_net16_hub_streaming_port_sctrl_cts.vhd b/trb_net16_hub_streaming_port_sctrl_cts.vhd
index fe694c353e83473179f67f1a628def15d6f7b84f..49c0fb6968ad266fbb60fe15bf5d2079d3a6e2b9 100644 (file)
--- a/trb_net16_hub_streaming_port_sctrl_cts.vhd
+++ b/trb_net16_hub_streaming_port_sctrl_cts.vhd
@@ -58,7 +58,7 @@ entity trb_net16_hub_streaming_port_sctrl_cts is
     CLOCK_FREQUENCY         : integer range 1 to 200 := 100;
     USE_ONEWIRE             : integer range 0 to 3 := c_YES;
     BROADCAST_SPECIAL_ADDR  : std_logic_vector(7 downto 0) := x"FF";
-    RDO_ADDITIONAL_PORT     : integer range 1 to 7 := 2; -- real limit to be explored
+    RDO_ADDITIONAL_PORT     : integer range 0 to 7 := 2; -- real limit to be explored
     RDO_DATA_BUFFER_DEPTH            : integer range 9 to 14         := 9;
     RDO_DATA_BUFFER_FULL_THRESH      : integer range 0 to 2**14-2    := 2**8;
     RDO_HEADER_BUFFER_DEPTH          : integer range 9 to 14         := 9;