attribute HGROUP of Behavioral : architecture is "SPI_group";
-- Signals
- type STATES is (SLEEP,DONE);--RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK
- signal CURRENT_STATE, NEXT_STATE: STATES;
+ type STATES is (SLEEP,DONE);--RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK
+ signal CURRENT_STATE, NEXT_STATE: STATES;
- signal status_data : std_logic_vector(31 downto 0);
- signal spi_busy : std_logic;
+ signal status_data : std_logic_vector(31 downto 0);
+ signal spi_busy : std_logic;
- signal reg_ctrl_data : std_logic_vector(31 downto 0); -- CMD, ADH, ADM, ADL
- signal reg_status_data : std_logic_vector(31 downto 0); -- MAX
+ signal reg_ctrl_data : std_logic_vector(31 downto 0); -- CMD, ADH, ADM, ADL
+ signal reg_status_data : std_logic_vector(31 downto 0); -- MAX
- signal reg_bus_data_out : std_logic_vector(31 downto 0); -- readback
+ signal reg_bus_data_out : std_logic_vector(31 downto 0); -- readback
- signal spi_bsm : std_logic_vector(7 downto 0);
- signal spi_debug : std_logic_vector(31 downto 0);
+ signal spi_bsm : std_logic_vector(7 downto 0);
+ signal spi_debug : std_logic_vector(31 downto 0);
- signal spi_start_x : std_logic;
- signal spi_start : std_logic;
+ signal spi_start_x : std_logic;
+ signal spi_start : std_logic;
- -- State machine signals
- signal bus_busy_x : std_logic;
- signal bus_busy : std_logic;
- signal bus_ack_x : std_logic;
- signal bus_ack : std_logic;
- signal store_wr_x : std_logic;
- signal store_wr : std_logic;
- signal store_rd_x : std_logic;
- signal store_rd : std_logic;
+ -- State machine signals
+ signal bus_busy_x : std_logic;
+ signal bus_busy : std_logic;
+ signal bus_ack_x : std_logic;
+ signal bus_ack : std_logic;
+ signal store_wr_x : std_logic;
+ signal store_wr : std_logic;
+ signal store_rd_x : std_logic;
+ signal store_rd : std_logic;
- signal reset_i : std_logic;
+ signal reset_i : std_logic;
attribute syn_preserve : boolean;
attribute syn_keep : boolean;
store_wr_x <= '0';
store_rd_x <= '0';
case CURRENT_STATE is
- when SLEEP =>
- if ( (spi_busy = '0') and (bus_read_in = '1') ) then
- NEXT_STATE <= DONE;
- store_rd_x <= '1';
- elsif( (spi_busy = '0') and (bus_write_in = '1') ) then
- NEXT_STATE <= DONE;
- store_wr_x <= '1';
- elsif( (bus_addr_in(0) = '0') and (spi_busy = '1') and (bus_read_in = '1') ) then
- NEXT_STATE <= SLEEP; -- CMD register is busy protected
- bus_busy_x <= '1';
- elsif( (bus_addr_in(0) = '0') and (spi_busy = '1') and (bus_write_in = '1') ) then
- NEXT_STATE <= SLEEP; -- CMD register is busy protected
- bus_busy_x <= '1';
- elsif( (bus_addr_in(0) = '1') and (spi_busy = '1') and (bus_read_in = '1') ) then
- NEXT_STATE <= DONE; -- STATUS register is not
- store_rd_x <= '1';
- elsif( (bus_addr_in(0) = '1') and (spi_busy = '1') and (bus_write_in = '1') ) then
- NEXT_STATE <= DONE; -- STATUS register is not
- store_wr_x <= '1';
- else
- NEXT_STATE <= SLEEP;
- end if;
--- when RD_RDY =>
--- NEXT_STATE <= RD_ACK;
--- bus_ack_x <= '1';
--- when WR_RDY =>
--- NEXT_STATE <= WR_ACK;
--- bus_ack_x <= '1';
--- when RD_ACK =>
--- if( bus_read_in = '0' ) then
--- NEXT_STATE <= DONE;
--- else
--- NEXT_STATE <= RD_ACK;
--- bus_ack_x <= '1';
--- end if;
--- when WR_ACK =>
--- if( bus_write_in = '0' ) then
--- NEXT_STATE <= DONE;
--- else
--- NEXT_STATE <= WR_ACK;
--- bus_ack_x <= '1';
--- end if;
--- when RD_BSY =>
--- if( bus_read_in = '0' ) then
--- NEXT_STATE <= DONE;
--- else
--- NEXT_STATE <= RD_BSY;
--- bus_busy_x <= '1';
--- end if;
--- when WR_BSY =>
--- if( bus_write_in = '0' ) then
--- NEXT_STATE <= DONE;
--- else
--- NEXT_STATE <= WR_BSY;
--- bus_busy_x <= '1';
--- end if;
- when DONE =>
- NEXT_STATE <= SLEEP;
- bus_ack_x <= '1';
- when others =>
- NEXT_STATE <= SLEEP;
+ when SLEEP =>
+ if ( (spi_busy = '0') and (bus_read_in = '1') ) then
+ NEXT_STATE <= DONE;
+ store_rd_x <= '1';
+ elsif( (spi_busy = '0') and (bus_write_in = '1') ) then
+ NEXT_STATE <= DONE;
+ store_wr_x <= '1';
+ elsif( (bus_addr_in(0) = '0') and (spi_busy = '1') and (bus_read_in = '1') ) then
+ NEXT_STATE <= SLEEP; -- CMD register is busy protected
+ bus_busy_x <= '1';
+ elsif( (bus_addr_in(0) = '0') and (spi_busy = '1') and (bus_write_in = '1') ) then
+ NEXT_STATE <= SLEEP; -- CMD register is busy protected
+ bus_busy_x <= '1';
+ elsif( (bus_addr_in(0) = '1') and (spi_busy = '1') and (bus_read_in = '1') ) then
+ NEXT_STATE <= DONE; -- STATUS register is not
+ store_rd_x <= '1';
+ elsif( (bus_addr_in(0) = '1') and (spi_busy = '1') and (bus_write_in = '1') ) then
+ NEXT_STATE <= DONE; -- STATUS register is not
+ store_wr_x <= '1';
+ else
+ NEXT_STATE <= SLEEP;
+ end if;
+ when DONE =>
+ NEXT_STATE <= SLEEP;
+ bus_ack_x <= '1';
+ when others =>
+ NEXT_STATE <= SLEEP;
end case;
end process TRANSFORM;
-- register write
THE_WRITE_REG_PROC: process( clk_in )
- begin
- if( rising_edge(clk_in) ) then
- if ( reset_i = '1' ) then
- reg_ctrl_data <= (others => '0');
- reg_status_data <= (others => '0');
- spi_start <= '0';
- elsif( (store_wr = '1') and (bus_addr_in(0) = '0') ) then
- reg_ctrl_data <= bus_data_in;
- spi_start <= spi_start_x;
- elsif( (store_wr = '1') and (bus_addr_in(0) = '1') ) then
- reg_status_data <= bus_data_in;
- spi_start <= spi_start_x;
- else
- spi_start <= spi_start_x;
- end if;
- end if;
- end process THE_WRITE_REG_PROC;
+begin
+ if( rising_edge(clk_in) ) then
+ if ( reset_i = '1' ) then
+ reg_ctrl_data <= (others => '0');
+ reg_status_data <= (others => '0');
+ spi_start <= '0';
+ elsif( (store_wr = '1') and (bus_addr_in(0) = '0') ) then
+ reg_ctrl_data <= bus_data_in;
+ spi_start <= spi_start_x;
+ elsif( (store_wr = '1') and (bus_addr_in(0) = '1') ) then
+ reg_status_data <= bus_data_in;
+ spi_start <= spi_start_x;
+ else
+ spi_start <= spi_start_x;
+ end if;
+ end if;
+end process THE_WRITE_REG_PROC;
spi_start_x <= '1' when ( (store_wr = '1') and (bus_addr_in(0) = '0') ) else '0';
bus_ack_out <= bus_ack;
bus_busy_out <= bus_busy;
bus_data_out <= reg_bus_data_out;
-stat(31 downto 3) <= spi_debug(31 downto 3); --status_data;
-stat(2) <= spi_start;
-stat(1) <= bus_write_in;
-stat(0) <= bus_read_in;
+
+stat(31 downto 2) <= spi_debug(31 downto 2);
+stat(1) <= spi_busy;
+stat(0) <= spi_start;
end Behavioral;
-- missing: end of PP/RDCMD by data_done signal.\r
\r
entity spi_slim is\r
- generic(\r
- SLOW_SPI : integer range c_NO to c_YES := c_YES\r
- );\r
- port(\r
- SYSCLK : in std_logic; -- 100MHz sysclock\r
- RESET : in std_logic; -- synchronous reset\r
- -- Command interface\r
- START_IN : in std_logic; -- one start pulse\r
- BUSY_OUT : out std_logic; -- SPI transactions are ongoing\r
- CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte\r
- ADL_IN : in std_logic_vector(7 downto 0); -- low address byte\r
- ADM_IN : in std_logic_vector(7 downto 0); -- mid address byte\r
- ADH_IN : in std_logic_vector(7 downto 0); -- high address byte\r
- MAX_IN : in std_logic_vector(7 downto 0); -- number of bytes to write / read (PP/RDCMD)\r
- TXDATA_IN : in std_logic_vector(7 downto 0); -- byte to be transmitted next\r
- TX_RD_OUT : out std_logic;\r
- RXDATA_OUT : out std_logic_vector(7 downto 0); -- current received byte\r
- RX_WR_OUT : out std_logic;\r
- TX_RX_A_OUT : out std_logic_vector(7 downto 0); -- memory block counter for PP/RDCMD\r
- -- SPI interface\r
- SPI_SCK_OUT : out std_logic;\r
- SPI_CS_OUT : out std_logic;\r
- SPI_SDI_IN : in std_logic;\r
- SPI_SDO_OUT : out std_logic;\r
- -- DEBUG\r
- CLK_EN_OUT : out std_logic;\r
- BSM_OUT : out std_logic_vector(7 downto 0);\r
- DEBUG_OUT : out std_logic_vector(31 downto 0)\r
- );\r
+ generic(\r
+ SLOW_SPI : integer range c_NO to c_YES := c_YES\r
+ );\r
+ port(\r
+ SYSCLK : in std_logic; -- 100MHz sysclock\r
+ RESET : in std_logic; -- synchronous reset\r
+ -- Command interface\r
+ START_IN : in std_logic; -- one start pulse\r
+ BUSY_OUT : out std_logic; -- SPI transactions are ongoing\r
+ CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte\r
+ ADL_IN : in std_logic_vector(7 downto 0); -- low address byte\r
+ ADM_IN : in std_logic_vector(7 downto 0); -- mid address byte\r
+ ADH_IN : in std_logic_vector(7 downto 0); -- high address byte\r
+ MAX_IN : in std_logic_vector(7 downto 0); -- number of bytes to write / read (PP/RDCMD)\r
+ TXDATA_IN : in std_logic_vector(7 downto 0); -- byte to be transmitted next\r
+ TX_RD_OUT : out std_logic;\r
+ RXDATA_OUT : out std_logic_vector(7 downto 0); -- current received byte\r
+ RX_WR_OUT : out std_logic;\r
+ TX_RX_A_OUT : out std_logic_vector(7 downto 0); -- memory block counter for PP/RDCMD\r
+ -- SPI interface\r
+ SPI_SCK_OUT : out std_logic;\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SDI_IN : in std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ -- DEBUG\r
+ CLK_EN_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
end entity;\r
\r
architecture Behavioral of spi_slim is\r
\r
--- new clock divider\r
-signal div_counter : std_logic_vector(1+SLOW_SPI downto 0);\r
-signal div_done_x : std_logic;\r
-signal div_done : std_logic; -- same as clk_en\r
-signal clk_en : std_logic; -- same as div_done\r
-\r
--- Statemachine signals\r
-type state_t is (IDLE,CSL,TXCMD,TXADD_H,TXADD_M,TXADD_L,TXDATA,RXDATA,\r
- WAIT1,WAIT2,WAIT3,WAIT4,WAIT5,WAIT6,WAIT7,WAIT8,CSH);\r
-signal STATE, NEXT_STATE : state_t;\r
-\r
-signal rx_ena_x : std_logic;\r
-signal rx_ena : std_logic;\r
-signal tx_ena_x : std_logic;\r
-signal tx_ena : std_logic;\r
-signal busy_x : std_logic;\r
-signal busy : std_logic;\r
-signal spi_cs_x : std_logic; -- SPI chip select (low active)\r
-signal spi_cs : std_logic;\r
-signal spi_sck_x : std_logic; -- SPI clock (rising edge active, from counter)\r
-signal spi_sck : std_logic;\r
-signal tx_load_x : std_logic; -- load TX shift register\r
-signal tx_load : std_logic;\r
-signal tx_done_x : std_logic; -- one memory byte sent\r
-signal tx_done : std_logic;\r
-signal tx_sel_x : std_logic_vector(2 downto 0); -- select TX content\r
-signal tx_sel : std_logic_vector(2 downto 0);\r
-signal rx_store_x : std_logic; -- store RX shift register\r
-signal rx_store : std_logic;\r
-signal rx_complete : std_logic;\r
-signal rst_addr_x : std_logic; -- reset address counter\r
-signal rst_addr : std_logic;\r
-\r
-signal inc_addr_rx_x : std_logic;\r
-signal inc_addr_rx : std_logic;\r
-signal inc_addr_tx_x : std_logic;\r
-signal inc_addr_tx : std_logic;\r
-signal ce_addr_x : std_logic;\r
-signal ce_addr : std_logic;\r
-\r
-signal addr_ctr : std_logic_vector(7 downto 0);\r
-signal data_done_x : std_logic;\r
-signal data_done : std_logic_vector(5 downto 0);\r
-\r
-signal last_tx_bit_x : std_logic;\r
-signal last_tx_bit : std_logic;\r
-signal is_data_x : std_logic;\r
-signal is_data : std_logic;\r
-\r
--- debug signals\r
-signal bsm_x : std_logic_vector(7 downto 0);\r
-signal debug_x : std_logic_vector(31 downto 0);\r
-\r
-signal start : std_logic; -- buffered start_in signal, as we have a clocked down state machine\r
-signal cmd_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
-signal adh_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
-signal adm_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
-signal adl_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
-signal max_int : std_logic_vector(7 downto 0);\r
-\r
--- transmitter\r
-signal tx_sreg : std_logic_vector(7 downto 0);\r
-signal tx_reg_comb : std_logic_vector(7 downto 0); -- multiplexer\r
-signal tx_bit_cnt : std_logic_vector(3 downto 0);\r
-\r
--- receiver\r
-signal rx_sreg : std_logic_vector(7 downto 0);\r
-signal rx_bit_cnt_clr : std_logic;\r
-signal rx_bit_cnt : std_logic_vector(3 downto 0);\r
-\r
--- registers\r
-signal rx_data : std_logic_vector(7 downto 0);\r
-\r
--- FLASH commands\r
--- single byte commands\r
-constant NOP : std_logic_vector(7 downto 0) := x"FF"; -- no cmd to execute\r
-constant WREN : std_logic_vector(7 downto 0) := x"06"; -- write enable -- OK -- CMD\r
-constant WRDI : std_logic_vector(7 downto 0) := x"04"; -- write disable -- OK -- CMD\r
-constant ERASE : std_logic_vector(7 downto 0) := x"C7"; -- chip erase -- OK -- CMD\r
-constant DPD : std_logic_vector(7 downto 0) := x"b9"; -- deep powerdown -- OK -- CMD\r
-constant RDPD : std_logic_vector(7 downto 0) := x"ab"; -- resume powerdown -- OK -- CMD\r
-\r
-constant RDID : std_logic_vector(7 downto 0) := x"9f"; -- read signature -- OK -- CMD + readbyte(n)\r
-constant RDSR : std_logic_vector(7 downto 0) := x"05"; -- read status reg -- OK -- CMD + readbyte(n)\r
-\r
-constant WRSR : std_logic_vector(7 downto 0) := x"01"; -- write stat. reg -- OK -- CMD + writebyte(1)\r
-\r
-constant SE64 : std_logic_vector(7 downto 0) := x"d8"; -- sector erase 64kB -- OK -- CMD + ADH + ADM + ADL\r
-constant SE32 : std_logic_vector(7 downto 0) := x"52"; -- sector erase 32kB -- OK -- CMD + ADH + ADM + ADL\r
-constant SE4 : std_logic_vector(7 downto 0) := x"20"; -- sector erase 32kB -- OK -- CMD + ADH + ADM + ADL\r
-constant SECP : std_logic_vector(7 downto 0) := x"36"; -- sector protect -- OK -- CMD + ADH + ADM + ADL\r
-constant SECU : std_logic_vector(7 downto 0) := x"39"; -- sector unprotect -- OK -- CMD + ADH + ADM + ADL\r
-\r
-constant RDCMD : std_logic_vector(7 downto 0) := x"03"; -- read data -- OK -- CMD + ADH + ADM + ADL + readbyte(n)\r
-constant RDSPR : std_logic_vector(7 downto 0) := x"3c"; -- read sect. prot. -- -- CMD + ADH + ADM + ADL + readbye(n)\r
-constant PP : std_logic_vector(7 downto 0) := x"02"; -- page program -- OK -- CMD + ADH + ADM + ADL + writebyte(n)\r
-\r
+ -- new clock divider\r
+ signal div_counter : std_logic_vector(1+SLOW_SPI downto 0);\r
+ signal div_done_x : std_logic;\r
+ signal div_done : std_logic; -- same as clk_en\r
+ signal clk_en : std_logic; -- same as div_done\r
+\r
+ -- Statemachine signals\r
+ type state_t is (IDLE,CSL,TXCMD,TXADD_H,TXADD_M,TXADD_L,TXDATA,RXDATA,\r
+ WAIT1,WAIT2,WAIT3,WAIT4,WAIT5,WAIT6,WAIT7,WAIT8,CSH);\r
+ signal STATE, NEXT_STATE : state_t; \r
+ \r
+ signal rx_ena_x : std_logic;\r
+ signal rx_ena : std_logic;\r
+ signal tx_ena_x : std_logic;\r
+ signal tx_ena : std_logic;\r
+ signal busy_x : std_logic;\r
+ signal busy : std_logic;\r
+ signal spi_cs_x : std_logic; -- SPI chip select (low active)\r
+ signal spi_cs : std_logic;\r
+ signal spi_sck_x : std_logic; -- SPI clock (rising edge active, from counter)\r
+ signal spi_sck : std_logic;\r
+ signal tx_load_x : std_logic; -- load TX shift register\r
+ signal tx_load : std_logic;\r
+ signal tx_done_x : std_logic; -- one memory byte sent\r
+ signal tx_done : std_logic;\r
+ signal tx_sel_x : std_logic_vector(2 downto 0); -- select TX content\r
+ signal tx_sel : std_logic_vector(2 downto 0);\r
+ signal rx_store_x : std_logic; -- store RX shift register\r
+ signal rx_store : std_logic;\r
+ signal rx_complete : std_logic;\r
+ signal rst_addr_x : std_logic; -- reset address counter\r
+ signal rst_addr : std_logic;\r
+\r
+ signal inc_addr_rx_x : std_logic;\r
+ signal inc_addr_rx : std_logic;\r
+ signal inc_addr_tx_x : std_logic;\r
+ signal inc_addr_tx : std_logic;\r
+ signal ce_addr_x : std_logic;\r
+ signal ce_addr : std_logic;\r
+\r
+ signal addr_ctr : std_logic_vector(7 downto 0);\r
+ signal data_done_x : std_logic; \r
+ signal data_done : std_logic_vector(5 downto 0);\r
+\r
+ signal last_tx_bit_x : std_logic;\r
+ signal last_tx_bit : std_logic;\r
+ signal is_data_x : std_logic;\r
+ signal is_data : std_logic;\r
+\r
+ -- debug signals\r
+ signal bsm_x : std_logic_vector(7 downto 0);\r
+ signal debug_x : std_logic_vector(31 downto 0);\r
+\r
+ signal start : std_logic; -- buffered start_in signal, as we have a clocked down state machine\r
+ signal cmd_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
+ signal adh_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
+ signal adm_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
+ signal adl_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
+ signal max_int : std_logic_vector(7 downto 0);\r
+\r
+ -- transmitter\r
+ signal tx_sreg : std_logic_vector(7 downto 0);\r
+ signal tx_reg_comb : std_logic_vector(7 downto 0); -- multiplexer\r
+ signal tx_bit_cnt : std_logic_vector(3 downto 0);\r
+\r
+ -- receiver\r
+ signal rx_sreg : std_logic_vector(7 downto 0);\r
+ signal rx_bit_cnt_clr : std_logic;\r
+ signal rx_bit_cnt : std_logic_vector(3 downto 0);\r
+\r
+ -- registers\r
+ signal rx_data : std_logic_vector(7 downto 0);\r
+\r
+ -- FLASH commands\r
+ -- single byte commands\r
+ constant NOP : std_logic_vector(7 downto 0) := x"FF"; -- no cmd to execute\r
+ constant WREN : std_logic_vector(7 downto 0) := x"06"; -- write enable -- OK -- CMD\r
+ constant WRDI : std_logic_vector(7 downto 0) := x"04"; -- write disable -- OK -- CMD\r
+ constant ERASE : std_logic_vector(7 downto 0) := x"C7"; -- chip erase -- OK -- CMD\r
+ constant DPD : std_logic_vector(7 downto 0) := x"b9"; -- deep powerdown -- OK -- CMD\r
+ constant RDPD : std_logic_vector(7 downto 0) := x"ab"; -- resume powerdown -- OK -- CMD\r
+\r
+ constant RDID : std_logic_vector(7 downto 0) := x"9f"; -- read signature -- OK -- CMD + readbyte(n)\r
+ constant RDSR : std_logic_vector(7 downto 0) := x"05"; -- read status reg -- OK -- CMD + readbyte(n)\r
+\r
+ constant WRSR : std_logic_vector(7 downto 0) := x"01"; -- write stat. reg -- OK -- CMD + writebyte(1)\r
+\r
+ constant SE64 : std_logic_vector(7 downto 0) := x"d8"; -- sector erase 64kB -- OK -- CMD + ADH + ADM + ADL\r
+ constant SE32 : std_logic_vector(7 downto 0) := x"52"; -- sector erase 32kB -- OK -- CMD + ADH + ADM + ADL\r
+ constant SE4 : std_logic_vector(7 downto 0) := x"20"; -- sector erase 32kB -- OK -- CMD + ADH + ADM + ADL\r
+ constant SECP : std_logic_vector(7 downto 0) := x"36"; -- sector protect -- OK -- CMD + ADH + ADM + ADL\r
+ constant SECU : std_logic_vector(7 downto 0) := x"39"; -- sector unprotect -- OK -- CMD + ADH + ADM + ADL\r
+\r
+ constant RDCMD : std_logic_vector(7 downto 0) := x"03"; -- read data -- OK -- CMD + ADH + ADM + ADL + readbyte(n)\r
+ constant RDSPR : std_logic_vector(7 downto 0) := x"3c"; -- read sect. prot. -- -- CMD + ADH + ADM + ADL + readbye(n)\r
+ constant PP : std_logic_vector(7 downto 0) := x"02"; -- page program -- OK -- CMD + ADH + ADM + ADL + writebyte(n)\r
\r
begin\r
\r
-----------------------------------------------------------\r
-- SPI clock generator\r
-----------------------------------------------------------\r
-THE_CLOCK_DIVIDER: process(sysclk)\r
+THE_CLOCK_DIVIDER: process( SYSCLK )\r
begin\r
- if( rising_edge(sysclk) ) then\r
- if( reset = '1' ) then\r
- div_counter <= (others => '0');\r
- div_done <= '0';\r
- spi_sck <= spi_sck_x;--'0';\r
- else\r
- div_counter <= div_counter + 1;\r
- div_done <= div_done_x;\r
- spi_sck <= spi_sck_x;\r
- end if;\r
+ if( rising_edge(SYSCLK) ) then\r
+ if( RESET = '1' ) then\r
+ div_counter <= (others => '0');\r
+ div_done <= '0';\r
+ spi_sck <= spi_sck_x;--'0';\r
+ else\r
+ div_counter <= div_counter + 1;\r
+ div_done <= div_done_x;\r
+ spi_sck <= spi_sck_x;\r
end if;\r
+ end if;\r
end process THE_CLOCK_DIVIDER;\r
\r
div_done_x <= '1' when ( or_all(div_counter) = '0' ) else '0';\r
-----------------------------------------------------------\r
-- start signal and local register sets for CMD and ADR\r
-----------------------------------------------------------\r
-THE_START_PROC: process(sysclk)\r
+THE_START_PROC: process( SYSCLK )\r
begin\r
- if( rising_edge(sysclk) ) then\r
- if ( reset = '1' ) then\r
- start <= '0';\r
- cmd_int <= (others => '0');\r
- adh_int <= (others => '0');\r
- adm_int <= (others => '0');\r
- adl_int <= (others => '0');\r
- max_int <= (others => '0');\r
- elsif( (start_in = '1') and (busy = '0') ) then\r
- start <= '1';\r
- cmd_int <= cmd_in;\r
- adh_int <= adh_in;\r
- adm_int <= adm_in;\r
- adl_int <= adl_in;\r
- max_int <= max_in;\r
- elsif( busy = '1' ) then\r
- start <= '0';\r
- end if;\r
+ if( rising_edge(SYSCLK) ) then\r
+ if ( RESET = '1' ) then\r
+ start <= '0';\r
+ cmd_int <= (others => '0');\r
+ adh_int <= (others => '0');\r
+ adm_int <= (others => '0');\r
+ adl_int <= (others => '0');\r
+ max_int <= (others => '0');\r
+ elsif( (START_IN = '1') and (busy = '0') ) then\r
+ start <= '1';\r
+ cmd_int <= cmd_in;\r
+ adh_int <= adh_in;\r
+ adm_int <= adm_in;\r
+ adl_int <= adl_in;\r
+ max_int <= max_in;\r
+ elsif( busy = '1' ) then\r
+ start <= '0';\r
end if;\r
+ end if;\r
end process THE_START_PROC;\r
\r
-----------------------------------------------------------\r
-- statemachine: clocked process\r
-----------------------------------------------------------\r
-THE_STATEMACHINE: process( sysclk )\r
+THE_STATEMACHINE: process( SYSCLK )\r
begin\r
- if( rising_edge(sysclk) ) then\r
- if ( reset = '1' ) then\r
- STATE <= IDLE;\r
- rx_ena <= '0';\r
- tx_ena <= '0';\r
- busy <= '0';\r
- spi_cs <= spi_cs_x;--'1';\r
- tx_load <= '0';\r
- tx_sel <= "000";\r
- rx_store <= '0';\r
- rst_addr <= '0';\r
- tx_done <= '0';\r
- is_data <= '0';\r
- elsif( clk_en = '1' ) then\r
- STATE <= NEXT_STATE;\r
- rx_ena <= rx_ena_x;\r
- tx_ena <= tx_ena_x;\r
- busy <= busy_x;\r
- spi_cs <= spi_cs_x;\r
- tx_load <= tx_load_x;\r
- tx_sel <= tx_sel_x;\r
- rx_store <= rx_store_x;\r
- rst_addr <= rst_addr_x;\r
- tx_done <= tx_done_x;\r
- is_data <= is_data_x;\r
- end if;\r
+ if( rising_edge(SYSCLK) ) then\r
+ if ( RESET = '1' ) then\r
+ STATE <= IDLE;\r
+ rx_ena <= '0';\r
+ tx_ena <= '0';\r
+ busy <= '0';\r
+ spi_cs <= spi_cs_x;--'1';\r
+ tx_load <= '0';\r
+ tx_sel <= "000";\r
+ rx_store <= '0';\r
+ rst_addr <= '0';\r
+ tx_done <= '0';\r
+ is_data <= '0';\r
+ elsif( clk_en = '1' ) then\r
+ STATE <= NEXT_STATE;\r
+ rx_ena <= rx_ena_x;\r
+ tx_ena <= tx_ena_x;\r
+ busy <= busy_x;\r
+ spi_cs <= spi_cs_x;\r
+ tx_load <= tx_load_x;\r
+ tx_sel <= tx_sel_x;\r
+ rx_store <= rx_store_x;\r
+ rst_addr <= rst_addr_x;\r
+ tx_done <= tx_done_x;\r
+ is_data <= is_data_x;\r
end if;\r
+ end if;\r
end process THE_STATEMACHINE;\r
\r
-----------------------------------------------------------\r
-----------------------------------------------------------\r
THE_STATE_TRANSITIONS: process( STATE, cmd_int, start, tx_bit_cnt, rx_bit_cnt, data_done(5) )\r
begin\r
- rx_ena_x <= '0';\r
- tx_ena_x <= '0';\r
- busy_x <= '1';\r
- spi_cs_x <= '1';\r
- tx_load_x <= '0';\r
- tx_sel_x <= "000";\r
- rx_store_x <= '0';\r
- rst_addr_x <= '0';\r
- tx_done_x <= '0';\r
- is_data_x <= '0';\r
- case STATE is\r
- when IDLE =>\r
- if( start = '1' ) then\r
- NEXT_STATE <= CSL;\r
- spi_cs_x <= '0';\r
- tx_load_x <= '1';\r
- tx_sel_x <= "000";\r
- rst_addr_x <= '1';\r
- else\r
- NEXT_STATE <= IDLE;\r
- busy_x <= '0';\r
- end if;\r
-\r
- when CSL =>\r
- NEXT_STATE <= TXCMD;\r
- tx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
-\r
- when TXCMD =>\r
- if( tx_bit_cnt < x"7" ) then\r
- NEXT_STATE <= TXCMD;\r
- tx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- else\r
- case cmd_int is\r
- when WREN | WRDI | ERASE | DPD | RDPD\r
- => NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- when SE64 | SE32 | SE4 | PP | RDCMD | SECP | SECU | RDSPR\r
- => NEXT_STATE <= WAIT1;\r
- spi_cs_x <= '0';\r
- tx_load_x <= '1';\r
- tx_sel_x <= "001"; -- ADH\r
- when WRSR => NEXT_STATE <= WAIT1;\r
- spi_cs_x <= '0';\r
- tx_load_x <= '1';\r
- tx_sel_x <= "100"; -- TXDATA\r
- is_data_x <= '1';\r
- when RDSR | RDID\r
- => NEXT_STATE <= WAIT1;\r
- spi_cs_x <= '0';\r
- tx_load_x <= '1';\r
- tx_sel_x <= "110"; -- "00"\r
- when others => NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- end case;\r
- end if;\r
-\r
- when WAIT1 =>\r
- case cmd_int is\r
- when SE64 | SE32 | SE4 | PP | RDCMD | SECP | SECU | RDSPR\r
- => NEXT_STATE <= TXADD_H;\r
- tx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- when RDSR | RDID\r
- => NEXT_STATE <= RXDATA;\r
- rx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- when WRSR => NEXT_STATE <= TXDATA;\r
- tx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- is_data_x <= '1';\r
- when others => NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- end case;\r
-\r
- when TXADD_H =>\r
- if( tx_bit_cnt < x"7" ) then\r
- NEXT_STATE <= TXADD_H;\r
- tx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- else\r
- NEXT_STATE <= WAIT2;\r
- spi_cs_x <= '0';\r
- tx_load_x <= '1';\r
- tx_sel_x <= "010"; -- ADM\r
- end if;\r
-\r
- when WAIT2 =>\r
- NEXT_STATE <= TXADD_M;\r
- tx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
-\r
- when TXADD_M =>\r
- if( tx_bit_cnt < x"7" ) then\r
- NEXT_STATE <= TXADD_M;\r
- tx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- else\r
- NEXT_STATE <= WAIT3;\r
- spi_cs_x <= '0';\r
- tx_load_x <= '1';\r
- tx_sel_x <= "011"; -- ADL\r
- end if;\r
-\r
- when WAIT3 =>\r
- NEXT_STATE <= TXADD_L;\r
- tx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
-\r
- when TXADD_L =>\r
- if( tx_bit_cnt < x"7" ) then\r
- NEXT_STATE <= TXADD_L;\r
- tx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- else\r
- case cmd_int is\r
- when PP => NEXT_STATE <= WAIT6;\r
- tx_load_x <= '1';\r
- tx_sel_x <= "100"; -- TXDATA\r
- spi_cs_x <= '0';\r
- when SE64 | SE32 | SE4 | SECP | SECU\r
- => NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- when RDCMD | RDSPR\r
- => NEXT_STATE <= WAIT4;\r
- spi_cs_x <= '0';\r
- tx_load_x <= '1';\r
- tx_sel_x <= "110"; -- "00"\r
- when others => NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- end case;\r
- end if;\r
-\r
- when WAIT4 =>\r
- case cmd_int is\r
- when RDCMD | RDSPR\r
- => NEXT_STATE <= RXDATA;\r
- rx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- when others => NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- end case;\r
-\r
- when RXDATA =>\r
- if( rx_bit_cnt < x"7" ) then\r
- NEXT_STATE <= RXDATA;\r
- rx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- else\r
- case cmd_int is\r
- when RDCMD | RDSR | RDID | RDSPR\r
- => NEXT_STATE <= WAIT7;\r
- spi_cs_x <= '0';\r
- rx_store_x <= '1';\r
- when others => NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- rx_store_x <= '1';\r
- end case;\r
- end if;\r
-\r
- when WAIT6 =>\r
- case cmd_int is\r
- when PP => if( data_done(5) = '1' ) then\r
- NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- else\r
- NEXT_STATE <= TXDATA;\r
- tx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- is_data_x <= '1';\r
- end if;\r
- when others => NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- end case;\r
-\r
- when TXDATA =>\r
- if( tx_bit_cnt < x"7" ) then\r
- NEXT_STATE <= TXDATA;\r
- tx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- else\r
- case cmd_int is\r
- when PP => NEXT_STATE <= WAIT6;\r
- spi_cs_x <= '0';\r
- tx_done_x <= '1';\r
- tx_load_x <= '1';\r
- tx_sel_x <= "100"; -- TXDATA\r
- when others => NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- end case;\r
- end if;\r
- is_data_x <= '1';\r
-\r
- when WAIT7 =>\r
- NEXT_STATE <= WAIT8;\r
- spi_cs_x <= '0';\r
-\r
- when WAIT8 =>\r
- case cmd_int is\r
- when RDCMD | RDID | RDSR | RDSPR\r
- => if( data_done(5) = '1' ) then\r
- NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- else\r
- NEXT_STATE <= RXDATA;\r
- rx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- end if;\r
- when others => NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- end case;\r
-\r
- when WAIT5 =>\r
- NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
-\r
- when CSH =>\r
- NEXT_STATE <= IDLE;\r
- busy_x <= '0';\r
+ rx_ena_x <= '0';\r
+ tx_ena_x <= '0';\r
+ busy_x <= '1';\r
+ spi_cs_x <= '1';\r
+ tx_load_x <= '0';\r
+ tx_sel_x <= "000";\r
+ rx_store_x <= '0';\r
+ rst_addr_x <= '0';\r
+ tx_done_x <= '0';\r
+ is_data_x <= '0';\r
+ case STATE is\r
+ when IDLE =>\r
+ if( start = '1' ) then\r
+ NEXT_STATE <= CSL;\r
+ spi_cs_x <= '0';\r
+ tx_load_x <= '1';\r
+ tx_sel_x <= "000";\r
+ rst_addr_x <= '1';\r
+ else\r
+ NEXT_STATE <= IDLE;\r
+ busy_x <= '0';\r
+ end if;\r
+\r
+ when CSL =>\r
+ NEXT_STATE <= TXCMD;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+\r
+ when TXCMD =>\r
+ if( tx_bit_cnt < x"7" ) then\r
+ NEXT_STATE <= TXCMD;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ else\r
+ case cmd_int is\r
+ when WREN | WRDI | ERASE | DPD | RDPD\r
+ => NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ when SE64 | SE32 | SE4 | PP | RDCMD | SECP | SECU | RDSPR\r
+ => NEXT_STATE <= WAIT1;\r
+ spi_cs_x <= '0';\r
+ tx_load_x <= '1';\r
+ tx_sel_x <= "001"; -- ADH\r
+ when WRSR\r
+ => NEXT_STATE <= WAIT1;\r
+ spi_cs_x <= '0';\r
+ tx_load_x <= '1';\r
+ tx_sel_x <= "100"; -- TXDATA\r
+ is_data_x <= '1';\r
+ when RDSR | RDID\r
+ => NEXT_STATE <= WAIT1;\r
+ spi_cs_x <= '0';\r
+ tx_load_x <= '1';\r
+ tx_sel_x <= "110"; -- "00"\r
+ when others \r
+ => NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ end case;\r
+ end if;\r
\r
- end case;\r
+ when WAIT1 =>\r
+ case cmd_int is\r
+ when SE64 | SE32 | SE4 | PP | RDCMD | SECP | SECU | RDSPR\r
+ => NEXT_STATE <= TXADD_H;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ when RDSR | RDID\r
+ => NEXT_STATE <= RXDATA;\r
+ rx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ when WRSR \r
+ => NEXT_STATE <= TXDATA;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ is_data_x <= '1';\r
+ when others\r
+ => NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ end case;\r
+\r
+ when TXADD_H =>\r
+ if( tx_bit_cnt < x"7" ) then\r
+ NEXT_STATE <= TXADD_H;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ else\r
+ NEXT_STATE <= WAIT2;\r
+ spi_cs_x <= '0';\r
+ tx_load_x <= '1';\r
+ tx_sel_x <= "010"; -- ADM\r
+ end if;\r
+\r
+ when WAIT2 =>\r
+ NEXT_STATE <= TXADD_M;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+\r
+ when TXADD_M =>\r
+ if( tx_bit_cnt < x"7" ) then\r
+ NEXT_STATE <= TXADD_M;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ else\r
+ NEXT_STATE <= WAIT3;\r
+ spi_cs_x <= '0';\r
+ tx_load_x <= '1';\r
+ tx_sel_x <= "011"; -- ADL\r
+ end if;\r
+\r
+ when WAIT3 =>\r
+ NEXT_STATE <= TXADD_L;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+\r
+ when TXADD_L =>\r
+ if( tx_bit_cnt < x"7" ) then\r
+ NEXT_STATE <= TXADD_L;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ else\r
+ case cmd_int is\r
+ when PP \r
+ => NEXT_STATE <= WAIT6;\r
+ tx_load_x <= '1';\r
+ tx_sel_x <= "100"; -- TXDATA\r
+ spi_cs_x <= '0';\r
+ when SE64 | SE32 | SE4 | SECP | SECU\r
+ => NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ when RDCMD | RDSPR\r
+ => NEXT_STATE <= WAIT4;\r
+ spi_cs_x <= '0';\r
+ tx_load_x <= '1';\r
+ tx_sel_x <= "110"; -- "00"\r
+ when others \r
+ => NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ end case;\r
+ end if;\r
+\r
+ when WAIT4 =>\r
+ case cmd_int is\r
+ when RDCMD | RDSPR\r
+ => NEXT_STATE <= RXDATA;\r
+ rx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ when others\r
+ => NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ end case;\r
+\r
+ when RXDATA =>\r
+ if( rx_bit_cnt < x"7" ) then\r
+ NEXT_STATE <= RXDATA;\r
+ rx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ else\r
+ case cmd_int is\r
+ when RDCMD | RDSR | RDID | RDSPR\r
+ => NEXT_STATE <= WAIT7;\r
+ spi_cs_x <= '0';\r
+ rx_store_x <= '1';\r
+ when others\r
+ => NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ rx_store_x <= '1';\r
+ end case;\r
+ end if;\r
+\r
+ when WAIT6 =>\r
+ case cmd_int is\r
+ when PP \r
+ => if( data_done(5) = '1' ) then\r
+ NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ else\r
+ NEXT_STATE <= TXDATA;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ is_data_x <= '1';\r
+ end if;\r
+ when others \r
+ => NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ end case;\r
+\r
+ when TXDATA =>\r
+ if( tx_bit_cnt < x"7" ) then\r
+ NEXT_STATE <= TXDATA;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ else\r
+ case cmd_int is\r
+ when PP\r
+ => NEXT_STATE <= WAIT6;\r
+ spi_cs_x <= '0';\r
+ tx_done_x <= '1';\r
+ tx_load_x <= '1';\r
+ tx_sel_x <= "100"; -- TXDATA\r
+ when others\r
+ => NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ end case;\r
+ end if;\r
+ is_data_x <= '1';\r
+\r
+ when WAIT7 =>\r
+ NEXT_STATE <= WAIT8;\r
+ spi_cs_x <= '0';\r
+\r
+ when WAIT8 =>\r
+ case cmd_int is\r
+ when RDCMD | RDID | RDSR | RDSPR\r
+ => if( data_done(5) = '1' ) then\r
+ NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ else\r
+ NEXT_STATE <= RXDATA;\r
+ rx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ end if;\r
+ when others \r
+ => NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ end case;\r
+\r
+ when WAIT5 =>\r
+ NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+\r
+ when CSH =>\r
+ NEXT_STATE <= IDLE;\r
+ busy_x <= '0';\r
+\r
+ end case;\r
end process THE_STATE_TRANSITIONS;\r
\r
-- state machine output table\r
THE_STATEMACHINE_OUT: process( STATE )\r
begin\r
- -- default values\r
- rx_bit_cnt_clr <= '1';\r
-\r
- case STATE is\r
- when IDLE => bsm_x <= x"00";\r
- when CSL => bsm_x <= x"09";\r
- when TXCMD => bsm_x <= x"01";\r
- when TXDATA => bsm_x <= x"02";\r
- when TXADD_H => bsm_x <= x"03";\r
- when TXADD_M => bsm_x <= x"04";\r
- when TXADD_L => bsm_x <= x"05";\r
- when RXDATA => bsm_x <= x"07";\r
- when WAIT1 => bsm_x <= x"10";\r
- when WAIT2 => bsm_x <= x"11";\r
- when WAIT3 => bsm_x <= x"12";\r
- when WAIT4 => bsm_x <= x"13";\r
- when WAIT8 => bsm_x <= x"17";\r
- when WAIT6 => bsm_x <= x"15";\r
- when WAIT5 => bsm_x <= x"14";\r
- when WAIT7 => bsm_x <= x"16";\r
- when CSH => bsm_x <= x"08";\r
- when others => bsm_x <= x"ff";\r
- end case;\r
+ -- default values\r
+ rx_bit_cnt_clr <= '1';\r
+\r
+ case STATE is\r
+ when IDLE => bsm_x <= x"00";\r
+ when CSL => bsm_x <= x"09";\r
+ when TXCMD => bsm_x <= x"01";\r
+ when TXDATA => bsm_x <= x"02";\r
+ when TXADD_H => bsm_x <= x"03";\r
+ when TXADD_M => bsm_x <= x"04";\r
+ when TXADD_L => bsm_x <= x"05";\r
+ when RXDATA => bsm_x <= x"07";\r
+ when WAIT1 => bsm_x <= x"10";\r
+ when WAIT2 => bsm_x <= x"11";\r
+ when WAIT3 => bsm_x <= x"12";\r
+ when WAIT4 => bsm_x <= x"13";\r
+ when WAIT8 => bsm_x <= x"17";\r
+ when WAIT6 => bsm_x <= x"15";\r
+ when WAIT5 => bsm_x <= x"14";\r
+ when WAIT7 => bsm_x <= x"16";\r
+ when CSH => bsm_x <= x"08";\r
+ when others => bsm_x <= x"ff";\r
+ end case;\r
end process THE_STATEMACHINE_OUT;\r
\r
-- TX data register multiplexer\r
THE_TXREG_MUX: process( tx_sel, cmd_int, adh_int, adm_int, adl_int, txdata_in )\r
begin\r
- case tx_sel is\r
- when "000" => tx_reg_comb <= cmd_int;\r
- when "001" => tx_reg_comb <= adh_int;\r
- when "010" => tx_reg_comb <= adm_int;\r
- when "011" => tx_reg_comb <= adl_int;\r
- when "100" => tx_reg_comb <= txdata_in;\r
- when "101" => tx_reg_comb <= x"ee"; -- unused\r
- when "110" => tx_reg_comb <= x"00"; -- fixed value\r
- when "111" => tx_reg_comb <= x"aa"; -- fixed value\r
- when others => tx_reg_comb <= x"00";\r
- end case;\r
+ case tx_sel is\r
+ when "000" => tx_reg_comb <= cmd_int;\r
+ when "001" => tx_reg_comb <= adh_int;\r
+ when "010" => tx_reg_comb <= adm_int;\r
+ when "011" => tx_reg_comb <= adl_int;\r
+ when "100" => tx_reg_comb <= txdata_in;\r
+ when "101" => tx_reg_comb <= x"ee"; -- unused\r
+ when "110" => tx_reg_comb <= x"00"; -- fixed value\r
+ when "111" => tx_reg_comb <= x"aa"; -- fixed value\r
+ when others => tx_reg_comb <= x"00";\r
+ end case;\r
end process THE_TXREG_MUX;\r
\r
-- TXData shift register and bit counter\r
THE_TX_SHIFT_AND_BITCOUNT: process( sysclk )\r
begin\r
- if( rising_edge(sysclk) ) then\r
- if( reset = '1' ) then\r
- tx_sreg(6 downto 0) <= (others => '0');\r
- tx_bit_cnt <= (others => '0');\r
- last_tx_bit <= '0';\r
- elsif ( (clk_en = '1' ) and (tx_load = '1') ) then\r
- tx_bit_cnt <= (others => '0');\r
- tx_sreg <= tx_reg_comb;\r
- elsif( (clk_en = '1') and (tx_ena = '1') ) then\r
- tx_bit_cnt <= tx_bit_cnt + 1;\r
- tx_sreg <= tx_sreg (6 downto 0) & '0';\r
- end if;\r
- last_tx_bit <= last_tx_bit_x;\r
+ if( rising_edge(sysclk) ) then\r
+ if( reset = '1' ) then\r
+ tx_sreg(6 downto 0) <= (others => '0');\r
+ tx_bit_cnt <= (others => '0');\r
+ last_tx_bit <= '0';\r
+ elsif ( (clk_en = '1' ) and (tx_load = '1') ) then\r
+ tx_bit_cnt <= (others => '0');\r
+ tx_sreg <= tx_reg_comb;\r
+ elsif( (clk_en = '1') and (tx_ena = '1') ) then\r
+ tx_bit_cnt <= tx_bit_cnt + 1;\r
+ tx_sreg <= tx_sreg (6 downto 0) & '0';\r
end if;\r
+ last_tx_bit <= last_tx_bit_x;\r
+ end if;\r
end process THE_TX_SHIFT_AND_BITCOUNT;\r
\r
last_tx_bit_x <= '1' when ( tx_bit_cnt = x"7" ) else '0';\r
-- receiver shift register and bit counter\r
THE_RX_SHIFT_AND_BITCOUNT: process( sysclk )\r
begin\r
- if( rising_edge(sysclk) ) then\r
- if ( reset = '1' ) then\r
- rx_bit_cnt <= (others => '0');\r
- rx_sreg <= (others => '0');\r
- elsif( (clk_en = '1') and (rx_ena = '1') ) then\r
- rx_sreg <= rx_sreg (6 downto 0) & spi_sdi_in;\r
- case rx_bit_cnt is\r
- when x"0" | x"1" | x"2" | x"3" | x"4" | x"5" | x"6" =>\r
- rx_bit_cnt <= rx_bit_cnt + 1;\r
- when x"7" =>\r
- rx_bit_cnt <= (others => '0');\r
- when others =>\r
- null;\r
- end case;\r
- end if;\r
+ if( rising_edge(sysclk) ) then\r
+ if ( reset = '1' ) then\r
+ rx_bit_cnt <= (others => '0');\r
+ rx_sreg <= (others => '0');\r
+ elsif( (clk_en = '1') and (rx_ena = '1') ) then\r
+ rx_sreg <= rx_sreg (6 downto 0) & spi_sdi_in;\r
+ case rx_bit_cnt is\r
+ when x"0" | x"1" | x"2" | x"3" | x"4" | x"5" | x"6" =>\r
+ rx_bit_cnt <= rx_bit_cnt + 1;\r
+ when x"7" =>\r
+ rx_bit_cnt <= (others => '0');\r
+ when others =>\r
+ null;\r
+ end case;\r
end if;\r
+ end if;\r
end process THE_RX_SHIFT_AND_BITCOUNT;\r
\r
-- the rx_data register\r
THE_RXDATA_REG: process( sysclk )\r
begin\r
- if( rising_edge(sysclk) ) then\r
- if ( reset = '1' ) then\r
- rx_data <= (others => '0');\r
- rx_complete <= '0';\r
- elsif( (clk_en = '1') and (rx_store = '1') ) then\r
- rx_data <= rx_sreg;\r
- rx_complete <= '1';\r
- else\r
- rx_complete <= '0';\r
- end if;\r
+ if( rising_edge(sysclk) ) then\r
+ if ( reset = '1' ) then\r
+ rx_data <= (others => '0');\r
+ rx_complete <= '0';\r
+ elsif( (clk_en = '1') and (rx_store = '1') ) then\r
+ rx_data <= rx_sreg;\r
+ rx_complete <= '1';\r
+ else\r
+ rx_complete <= '0';\r
end if;\r
+ end if;\r
end process;\r
\r
-- address generator for external BRAM\r
THE_ADDR_COUNTER: process( sysclk )\r
begin\r
- if( rising_edge(sysclk) ) then\r
- if ( (reset = '1') or (rst_addr = '1') ) then\r
- addr_ctr <= (others => '0');\r
- data_done <= (others => '0');\r
- inc_addr_rx <= '0';\r
- inc_addr_tx <= '0';\r
- ce_addr <= '0';\r
- elsif( ce_addr = '1' ) then\r
- addr_ctr <= addr_ctr + 1;\r
- end if;\r
- data_done(5 downto 1) <= data_done(4 downto 0);\r
- data_done(0) <= data_done_x;\r
- inc_addr_rx <= inc_addr_rx_x;\r
- inc_addr_tx <= inc_addr_tx_x;\r
- ce_addr <= ce_addr_x;\r
+ if( rising_edge(sysclk) ) then\r
+ if ( (reset = '1') or (rst_addr = '1') ) then\r
+ addr_ctr <= (others => '0');\r
+ data_done <= (others => '0');\r
+ inc_addr_rx <= '0';\r
+ inc_addr_tx <= '0';\r
+ ce_addr <= '0';\r
+ elsif( ce_addr = '1' ) then\r
+ addr_ctr <= addr_ctr + 1;\r
end if;\r
+ data_done(5 downto 1) <= data_done(4 downto 0);\r
+ data_done(0) <= data_done_x;\r
+ inc_addr_rx <= inc_addr_rx_x;\r
+ inc_addr_tx <= inc_addr_tx_x;\r
+ ce_addr <= ce_addr_x;\r
+ end if;\r
end process THE_ADDR_COUNTER;\r
\r
inc_addr_rx_x <= '1' when ( rx_complete = '1' ) else '0';\r
data_done_x <= '1' when ( addr_ctr = max_int ) else '0';\r
\r
-- output signals\r
-spi_cs_out <= spi_cs;\r
-spi_sck_out <= spi_sck;\r
-spi_sdo_out <= tx_sreg(7);\r
-busy_out <= busy;\r
-\r
-tx_rd_out <= '0';\r
-rxdata_out <= rx_data;\r
-rx_wr_out <= rx_complete;\r
-tx_rx_a_out <= addr_ctr;\r
-\r
-clk_en_out <= clk_en;\r
-bsm_out <= bsm_x;\r
-debug_out <= debug_x;\r
-\r
+SPI_CS_OUT <= spi_cs;\r
+SPI_SCK_OUT <= spi_sck;\r
+SPI_SDO_OUT <= tx_sreg(7);\r
+BUSY_OUT <= busy;\r
+\r
+TX_RD_OUT <= '0';\r
+RXDATA_OUT <= rx_data;\r
+RX_WR_OUT <= rx_complete;\r
+TX_RX_A_OUT <= addr_ctr;\r
+\r
+CLK_EN_OUT <= clk_en;\r
+BSM_OUT <= bsm_x;\r
+DEBUG_OUT <= debug_x;\r
\r
end Behavioral;\r
jspc29 / trbnet.git / commitdiff