Go back to "Compiles at least"

diff --git a/ADC/compile_constraints.pl b/ADC/compile_constraints.pl
index cd1d711d5eb08adbca33bb2a709b82480b873559..d7a00c5cd1237ddccd5d7a94cd6813cdd56bc720 100755 (executable)
--- a/ADC/compile_constraints.pl
+++ b/ADC/compile_constraints.pl
@@ -69,12 +69,14 @@ my $lpf = join('', <FILE>);
 close FILE;
 
 $lpf =~ s#THE_TDC/#GEN_TDC.THE_TDC/#g;
-# only for TDC v1.6.3
-#$lpf =~ s#ff_array_en#ff_array_en_i#g;
 
 
 # make the LPF diamond 2.1 compatible
 # we assume that generate loops are all named with "gen_"
+#$lpf =~ s#(gen_)(\w+?)\.#$1$2_#gi;
+#$lpf =~ s#(gen_)(\w+?)(\d+)\.#$1$2$3_#gi;
+#$lpf =~ s#(gen_)(\w+?)(\*)\.#$1$2$3_#gi;
+#$lpf =~ s#SimAdder##g;
 sub replace_dot {
   my @m = @_;
   $m[1] =~ s/\./_/g;
@@ -83,6 +85,7 @@ sub replace_dot {
 $lpf =~ s#(BLKNAME\s+)(.+?)([;\s])#replace_dot($1,$2,$3)#eg;
 $lpf =~ s#(CELL\s+")(.+?)(")#replace_dot($1,$2,$3)#eg;
 $lpf =~ s#(NET\s+")(.+?)(")#replace_dot($1,$2,$3)#eg;
+$lpf =~ s#ff_array_en#ff_array_en_i#g;
 
 
 open FILE, ">$workdir/$TOPNAME.lpf" or die "Couldnt open file: $!";

diff --git a/ADC/config.vhd b/ADC/config.vhd
index b02066705717ad0c1b89c1549134ba26e5ffffb8..138db8d8da0e17f538d4e073d16b96739c43b38b 100644 (file)
--- a/ADC/config.vhd
+++ b/ADC/config.vhd
@@ -50,10 +50,14 @@ package config is
   constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 0;
   
   --> change names in constraints file
-  --ring buffer size: 32,64,96,128,dyn    
-  constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size:  0, 1, 2,  3,  7   
+  --ring buffer size: 32,64,96,128,dyn
+  --for TDC v1.6.3, only 0,1,3 are valid
+  constant RING_BUFFER_SIZE : integer range 0 to 7 := 3; --ring buffer size:  0, 1, 2,  3,  7   
 
 
+  constant TDC_CONTROL_REG_NR : integer := 6;
+  
+
   ------------------------------------------------------------------------------
   --End of design configuration
   ------------------------------------------------------------------------------

diff --git a/ADC/tdc_release b/ADC/tdc_release
index 043eaed755187bdef540148f05e28b03a930503c..3f0371b3bd681ac8224da969a193e997dd2a381a 120000 (symlink)
--- a/ADC/tdc_release
+++ b/ADC/tdc_release
@@ -1 +1 @@
-../../tdc/releases/tdc_v2.1.3/
\ No newline at end of file
+../../tdc/releases/tdc_v1.6.3
\ No newline at end of file

diff --git a/ADC/trb3_periph_adc.prj b/ADC/trb3_periph_adc.prj
index 40cb090e470f53be8dd27752dabef882fb4fd797..d57df2cfef6757c673cc7646492e88624df63abc 100644 (file)
--- a/ADC/trb3_periph_adc.prj
+++ b/ADC/trb3_periph_adc.prj
@@ -193,11 +193,8 @@ if {$INCLUDE_TDC == 1} {
    add_file -vhdl -lib "work" "tdc_release/LogicAnalyser.vhd"
    add_file -vhdl -lib "work" "tdc_release/Readout.vhd"
    add_file -vhdl -lib "work" "tdc_release/risingEdgeDetect.vhd"
-   add_file -vhdl -lib "work" "tdc_release/ROM_encoder_ecp3.vhd"
+   add_file -vhdl -lib "work" "tdc_release/ROM_encoder_3.vhd"
    add_file -vhdl -lib "work" "tdc_release/ShiftRegisterSISO.vhd"
-   add_file -vhdl -lib "work" "tdc_release/Stretcher_A.vhd"
-   add_file -vhdl -lib "work" "tdc_release/Stretcher_B.vhd"
-   add_file -vhdl -lib "work" "tdc_release/Stretcher.vhd"
    add_file -vhdl -lib "work" "tdc_release/TDC.vhd"
    add_file -vhdl -lib "work" "tdc_release/TriggerHandler.vhd"
    add_file -vhdl -lib "work" "tdc_release/up_counter.vhd"

diff --git a/ADC/trb3_periph_adc.vhd b/ADC/trb3_periph_adc.vhd
index 4d0fd22023d1843f40a39cf403cf755ca6176128..208efdff4ef293d4450c456ec11959e874705e9e 100644 (file)
--- a/ADC/trb3_periph_adc.vhd
+++ b/ADC/trb3_periph_adc.vhd
@@ -182,7 +182,6 @@ architecture trb3_periph_adc_arch of trb3_periph_adc is
   
   signal tdc_inputs                  : std_logic_vector(TDC_CHANNEL_NUMBER-2 downto 0);
   
-  constant TDC_CONTROL_REG_NR : integer := 8;
   type tdc_ctrl_reg_arr_t is array (0 to TDC_CONTROL_REG_NR-1) of std_logic_vector(31 downto 0);
   signal tdc_ctrl_reg_arr : tdc_ctrl_reg_arr_t;
   signal tdc_ctrl_reg   : std_logic_vector(TDC_CONTROL_REG_NR*32-1 downto 0);
@@ -584,6 +583,7 @@ LED_YELLOW <= not med_stat_op(11);
       generic map (
         CHANNEL_NUMBER => TDC_CHANNEL_NUMBER,     -- Number of TDC channels
         STATUS_REG_NR  => 21,           -- Number of status regs
+        TDC_VERSION => TDC_VERSION,
         CONTROL_REG_NR => TDC_CONTROL_REG_NR,  -- Number of control regs - higher than 8 check tdc_ctrl_addr
         DEBUG          => c_NO
         )
@@ -593,7 +593,7 @@ LED_YELLOW <= not med_stat_op(11);
         CLK_READOUT           => clk_100_i,  -- Clock for the readout
         REFERENCE_TIME        => timing_trg_received_i,   -- Reference time input
         HIT_IN                => tdc_inputs,      -- Channel start signals
-        HIT_CAL_IN            => osc_int,  --clk_20_i,    -- Hits for calibrating the TDC
+        HIT_CALIBRATION       => osc_int,  --clk_20_i,    -- Hits for calibrating the TDC
         TRG_WIN_PRE           => tdc_ctrl_reg(42 downto 32),  -- Pre-Trigger window width
         TRG_WIN_POST          => tdc_ctrl_reg(58 downto 48),  -- Post-Trigger window width
         --