###########################################################
##Relax some timing constraints
###########################################################
-#MULTICYCLE FROM CELL "MuPix3_Board_*/board_interface_1/hbus_from_mupix_sync" TO CELL "MuPix3_Board_*/HitbusHistogram_1/hitbus_buffer" 2 X;
-MULTICYCLE FROM CELL "MuPix3_Board_*/TimeWalkWithFiFo_1/hitbus_timeout_slow_sync*" TO CELL "MuPix3_Board_*/TimeWalkWithFiFo_1/hitbus_timeout_fast_sync*" 2 X;
\ No newline at end of file
+MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 50 ns;
+MULTICYCLE FROM CELL "MuPix3_Board_*/TimeWalkWithFiFo_1/hitbus_timeout_slow_sync*" TO CELL "MuPix3_Board_*/TimeWalkWithFiFo_1/hitbus_timeout_fast_sync*" 2 X;
+MULTICYCLE FROM CELL "THE_RESET_HANDLER/reset" TO CELL "THE_RESET_HANDLER/final_reset[0]" 10 ns;
\ No newline at end of file
port map (
clk_in => clk,
fast_clk_in => fast_clk,
+ reset => Reset,
mupixreadout => mupixreadout_i,
sout_c_from_mupix => sout_c_from_mupix,
sout_d_from_mupix => sout_d_from_mupix,
port(
clk_in : in std_logic;
fast_clk_in : in std_logic;
+ reset : in std_logic;
-- signals from mupix
mupixreadout : in MupixReadoutData;
sout_c_from_mupix : in std_logic;
begin
-- fast synchronize for hitbus and szintilator
- fast_sync: process (fast_clk_in) is
- begin -- process fast_sync
- if rising_edge(fast_clk_in) then
- hitbus_buf <= hbus_from_mupix;
- szintilator_sync_buf <= fpga_aux_from_board(0);
- szintilator_fast_sync <= szintilator_sync_buf;
- if invert_signals_int = '1' then
- hbus_from_mupix_fast_sync <= hitbus_buf;
- else
- hbus_from_mupix_fast_sync <= not hitbus_buf;
- end if;
- end if;
- end process fast_sync;
+ fast_sync : process(fast_clk_in) is
+ begin -- process fast_sync
+ if rising_edge(fast_clk_in) then
+ if reset = '1' then
+ hitbus_buf <= '0';
+ szintilator_sync_buf <= '0';
+ else
+ hitbus_buf <= hbus_from_mupix;
+ szintilator_sync_buf <= fpga_aux_from_board(0);
+ szintilator_fast_sync <= szintilator_sync_buf;
+ if invert_signals_int = '1' then
+ hbus_from_mupix_fast_sync <= hitbus_buf;
+ else
+ hbus_from_mupix_fast_sync <= not hitbus_buf;
+ end if;
+ end if;
+ end if;
+ end process fast_sync;
-- Synchronize input signals
- process
- begin
- wait until rising_edge(clk_in);
- fpga_aux_from_board_sync <= fpga_aux_from_board(5 downto 1);
- szintilator_sync <= fpga_aux_from_board(0);
- if invert_signals_int = '1' then
- mupixreadout_sync.hit_time <= not mupixreadout.hit_time;
- mupixreadout_sync.hit_row <= not mupixreadout.hit_row;
- mupixreadout_sync.hit_col <= not mupixreadout.hit_col;
- mupixreadout_sync.priout <= mupixreadout.priout; --is inverted on the chip
- sout_c_from_mupix_sync <= not sout_c_from_mupix;
- sout_d_from_mupix_sync <= not sout_d_from_mupix;
- hbus_from_mupix_sync <= hbus_from_mupix;
- else
- mupixreadout_sync.hit_time <= mupixreadout.hit_time;
- mupixreadout_sync.hit_row <= mupixreadout.hit_row;
- mupixreadout_sync.hit_col <= mupixreadout.hit_col;
- mupixreadout_sync.priout <= not mupixreadout.priout; --is inverted on the chip
- sout_c_from_mupix_sync <= sout_c_from_mupix;
- sout_d_from_mupix_sync <= sout_d_from_mupix;
- hbus_from_mupix_sync <= not hbus_from_mupix;
- end if;
- end process;
+ process(clk_in)
+ begin
+ if rising_edge(clk_in) then
+ if reset = '1' then
+ fpga_aux_from_board_sync <= (others => '0');
+ szintilator_sync <= '0';
+ hbus_from_mupix_sync <= '0';
+ sout_c_from_mupix_sync <= '0';
+ sout_d_from_mupix_sync <= '0';
+ mupixreadout_sync.hit_time <= (others => '0');
+ mupixreadout_sync.hit_row <= (others => '0');
+ mupixreadout_sync.hit_col <= (others => '0');
+ mupixreadout_sync.priout <= '0';
+ else
+ fpga_aux_from_board_sync <= fpga_aux_from_board(5 downto 1);
+ szintilator_sync <= fpga_aux_from_board(0);
+ if invert_signals_int = '1' then
+ mupixreadout_sync.hit_time <= not mupixreadout.hit_time;
+ mupixreadout_sync.hit_row <= not mupixreadout.hit_row;
+ mupixreadout_sync.hit_col <= not mupixreadout.hit_col;
+ mupixreadout_sync.priout <= mupixreadout.priout; --is inverted on the chip
+ sout_c_from_mupix_sync <= not sout_c_from_mupix;
+ sout_d_from_mupix_sync <= not sout_d_from_mupix;
+ hbus_from_mupix_sync <= hbus_from_mupix;
+ else
+ mupixreadout_sync.hit_time <= mupixreadout.hit_time;
+ mupixreadout_sync.hit_row <= mupixreadout.hit_row;
+ mupixreadout_sync.hit_col <= mupixreadout.hit_col;
+ mupixreadout_sync.priout <= not mupixreadout.priout; --is inverted on the chip
+ sout_c_from_mupix_sync <= sout_c_from_mupix;
+ sout_d_from_mupix_sync <= sout_d_from_mupix;
+ hbus_from_mupix_sync <= not hbus_from_mupix;
+ end if;
+ end if;
+ end if;
+ end process;
slv_bus_handler : process(CLK_IN)
begin
--readout signal registers
signal priout_reg : std_logic := '0';
+ signal ld_pix_i : std_logic := '0';
+ signal pulldown_i : std_logic := '0';
+ signal ld_col_i : std_logic := '0';
+ signal rd_col_i : std_logic := '0';
signal ld_pix_reg : std_logic := '0';
signal pulldown_reg : std_logic := '0';
signal ld_col_reg : std_logic := '0';
signal rd_col_reg : std_logic := '0';
+ attribute syn_preserve : boolean;
+ attribute syn_keep : boolean;
+ attribute syn_keep of ld_pix_reg, pulldown_reg, ld_col_reg, rd_col_reg : signal is true;
+ attribute syn_preserve of ld_pix_reg, pulldown_reg, ld_col_reg, rd_col_reg : signal is true;
--data multiplexing
signal selecthitgen : std_logic := '0';
if rising_edge(clk) then
if(rst = '1') then
ro_state <= idle;
- ld_pix_reg <= '0';
- ld_col_reg <= '0';
- rd_col_reg <= '0';
- pulldown_reg <= '0';
+ ld_pix_i <= '0';
+ ld_col_i <= '0';
+ rd_col_i <= '0';
+ pulldown_i <= '0';
ro_busy_mupix_i <= '0';
endofevent_mupix_i <= '0';
else
endofevent_mupix_i <= '0';
ro_busy_mupix_i <= '0';
increase_eventcounter_mpx_i <= '0';
- ld_pix_reg <= '0';
- pulldown_reg <= '0';
- ld_col_reg <= '0';
- rd_col_reg <= '0';
+ ld_pix_i <= '0';
+ pulldown_i <= '0';
+ ld_col_i <= '0';
+ rd_col_i <= '0';
case ro_state is
when pause =>
pausecounter <= pausecounter + 1;
if(start_mupix_ro_i = '1') then
ro_state <= loadpix;
ro_busy_mupix_i <= '1';
- ld_pix_reg <= '1';
+ ld_pix_i <= '1';
ro_delcounter <= unsigned(delaycounters1(7 downto 0));
increase_eventcounter_mpx_i <= '1';
else
--state machine
if(ro_delcounter = "00000000") then
ro_state <= pulld;
- pulldown_reg <= '1';
+ pulldown_i <= '1';
ro_delcounter <= unsigned(delaycounters1(15 downto 8));
else
- pulldown_reg <= '0';
+ pulldown_i <= '0';
ro_delcounter <= ro_delcounter - 1;
ro_state <= loadpix;
end if;
ro_state <= pulld;
if(ro_delcounter = "00000000") then
ro_state <= loadcol;
- ld_col_reg <= '1';
+ ld_col_i <= '1';
ro_delcounter <= unsigned(delaycounters1(23 downto 16));
end if;
when loadcol =>
if(ro_delcounter = "00000000") then
if mupixreadout.priout = '1' then
ro_state <= readcol;
- rd_col_reg <= '1';
+ rd_col_i <= '1';
ro_delcounter <= unsigned(delaycounters1(31 downto 24));
else
memwren_mupix_i <= '1';
ro_state <= readcol;
--issue read signal
if(ro_delcounter > unsigned(delaycounters1(31 downto 24)) - unsigned(delaycounters2(15 downto 8))) then
- rd_col_reg <= '1';
+ rd_col_i <= '1';
end if;
--sample priout
if (std_logic_vector(ro_delcounter) = delaycounters2(23 downto 16)) then
else
if ( mupixreadout.priout = '1' or (delaycounters2(23 downto 16) /= "00000000" and priout_reg = '1')) then
ro_state <= readcol;
- rd_col_reg <= '1';
+ rd_col_i <= '1';
ro_delcounter <= unsigned(delaycounters1(31 downto 24));
else
ro_state <= pulld;
- pulldown_reg <= '1';
+ pulldown_i <= '1';
ro_delcounter <= unsigned(delaycounters2(7 downto 0));
end if;
end if;
counter => graycount
);
+ output_pipeline : process (clk) is
+ begin
+ if rising_edge(clk) then
+ if rst = '1' then
+ ld_pix_reg <= '0';
+ pulldown_reg <= '0';
+ ld_col_reg <= '0';
+ rd_col_reg <= '0';
+ else
+ ld_pix_reg <= ld_pix_i;
+ pulldown_reg <= pulldown_i;
+ ld_col_reg <= ld_col_i;
+ rd_col_reg <= rd_col_i;
+ end if;
+ end if;
+ end process output_pipeline;
+
+
mupixcontrol.ldpix <= ld_pix_reg;
mupixcontrol.pulldown <= pulldown_reg;
mupixcontrol.ldcol <= ld_col_reg;
port (
clk_in : in std_logic;
fast_clk_in : in std_logic;
+ reset : in std_logic;
mupixreadout : in MupixReadoutData;
sout_c_from_mupix : in std_logic;
sout_d_from_mupix : in std_logic;
signal shiftregister : std_logic_vector(47 downto 0);
signal write_again : std_logic;
+ signal spi_data_i, spi_data_reg : std_logic;
+ signal spi_clk_i, spi_clk_reg : std_logic;
+ signal spi_ld_i, spi_ld_reg : std_logic;
+ attribute syn_preserve : boolean;
+ attribute syn_keep : boolean;
+ attribute syn_keep of spi_data_reg, spi_clk_reg, spi_ld_reg : signal is true;
+ attribute syn_preserve of spi_data_reg, spi_clk_reg, spi_ld_reg : signal is true;
+
+
signal ckdiv : unsigned(5 downto 0);
signal injection2_reg : std_logic_vector(15 downto 0) := (others => '0');
if (reset = '1') then
ckdiv <= (others => '0');
cyclecounter <= (others => '0');
- spi_data <= '0';
- spi_clk <= '0';
- spi_ld <= '0';
+ spi_data_i <= '0';
+ spi_clk_i <= '0';
+ spi_ld_i <= '0';
state <= waiting;
else
case state is
when waiting =>
ckdiv <= (others => '0');
cyclecounter <= (others => '0');
- spi_data <= '0';
- spi_clk <= '0';
- spi_ld <= '0';
+ spi_data_i <= '0';
+ spi_clk_i <= '0';
+ spi_ld_i <= '0';
state <= waiting;
if wren = '1' then
shiftregister <= injection2_reg & injection1_reg & threshold_reg;
if (ckdiv = "000000") then
cyclecounter <= cyclecounter + 1;
if (cyclecounter(0) = '0') then -- even cycles: push data, clock at '0'
- spi_data <= shiftregister(47);
+ spi_data_i <= shiftregister(47);
shiftregister(47 downto 1) <= shiftregister(46 downto 0);
shiftregister(0) <= '0';
- spi_clk <= '0';
+ spi_clk_i <= '0';
end if;
if (cyclecounter(0) = '1') then --odd cycles:
- spi_clk <= '1';
+ spi_clk_i <= '1';
end if;
if (cyclecounter = "01100000") then -- we are done...
state <= loading;
- spi_clk <= '1';
+ spi_clk_i <= '1';
cyclecounter <= "00000000";
end if;
end if;
if (ckdiv = "00000") then
cyclecounter <= cyclecounter + 1;
if (cyclecounter = "00000000") then
- spi_ld <= '1';
+ spi_ld_i <= '1';
elsif (cyclecounter = "00000001") then
- spi_clk <= '0';
+ spi_clk_i <= '0';
elsif (cyclecounter = "00000010") then
- spi_ld <= '0';
+ spi_ld_i <= '0';
state <= waiting;
end if;
end if;
end if;
end process SLV_HANDLER;
+ output_pipe : process (clk) is
+ begin
+ if rising_edge(clk) then
+ if reset = '1' then
+ spi_data_reg <= '0';
+ spi_clk_reg <= '0';
+ spi_ld_reg <= '0';
+ else
+ spi_data_reg <= spi_data_i;
+ spi_clk_reg <= spi_clk_i;
+ spi_ld_reg <= spi_ld_i;
+ end if;
+ end if;
+ end process output_pipe;
+
+
+ spi_data <= spi_data_reg;
+ spi_clk <= spi_clk_reg;
+ spi_ld <= spi_ld_reg;
+
end rtl;
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