changed Trbnet address of chain 0

diff --git a/soft/toolbox/jtag_atomic/boards.ini b/soft/toolbox/jtag_atomic/boards.ini
index fc2e68be426cd6e234436e26fdcdab9ccf7a7bd3..cf39550862e753534372de59c32c363175718617 100644 (file)
--- a/soft/toolbox/jtag_atomic/boards.ini
+++ b/soft/toolbox/jtag_atomic/boards.ini
@@ -4,7 +4,7 @@ FPGAboard_hostname=trb1577
 FPGAboard_staplfilename=jcb_trb_009.stapl
 FPGAboard_staplfilename_delay1=jcb_trb_008.stapl
 FPGAboard_addonortrb=trb
-FPGAtrbnetAddr=0xf013
+FPGAtrbnetAddr=0xf308
 CONFperiod_trbnetAddr=0xc001
 CONFoffspillcounter_trbnetAddr=0xc002
 CONFwaitstart_trbnetAddr=0xc007

diff --git a/soft/toolbox/jtag_atomic/chains.ini.chain0 b/soft/toolbox/jtag_atomic/chains.ini.chain0
index 7d5aaba846e27639711d3520db776e78d6bec995..d9617d114305473230b5cd5e0b8b12339bd233ad 100644 (file)
--- a/soft/toolbox/jtag_atomic/chains.ini.chain0
+++ b/soft/toolbox/jtag_atomic/chains.ini.chain0
@@ -1,4 +1,4 @@
-FPGAtrbnetAddr=0xf013
+FPGAtrbnetAddr=0xf308
 RAMtrbnetAddr=0xb000
 CMDreg_trbnetAddr=0xb120
 RAMbase_trbnetAddr=0xb121

diff --git a/vhdl/code/jtag_mvd.vhd b/vhdl/code/jtag_mvd.vhd
index 516ac6b1be0485ceabdd17a491a50ec85bf90d82..a3143c4f339a7ebed6ec0c342dd24dc0010ff96d 100644 (file)
--- a/vhdl/code/jtag_mvd.vhd
+++ b/vhdl/code/jtag_mvd.vhd
@@ -80,7 +80,7 @@ architecture jtag_mvd_arch of jtag_mvd is
   signal jtag_cmd_m26c_no_more_data_out      : std_logic_vector(NUM_CHAINS-1 downto 0);
   signal jtag_cmd_m26c_unknown_addr_out      : std_logic_vector(NUM_CHAINS-1 downto 0);
 
-
+  constant num_bus_handler_ports : integer := NUM_CHAINS + 1; 
   type jtag_counters_t is array(NUM_CHAINS-1 downto 0) of std_logic_vector(COUNTER_WIDTHS-1 downto 0);
   type jtag_long_counters_t is array(NUM_CHAINS-1 downto 0) of std_logic_vector(31 downto 0);
   signal jtagcmd_read_id_errors_count_out   : jtag_counters_t;
@@ -180,7 +180,7 @@ begin
 
 THE_BUS_HANDLER : trb_net16_regio_bus_handler
   generic map(
-    PORT_NUMBER    => 2,
+    PORT_NUMBER    => num_bus_handler_ports,
     PORT_ADDRESSES => (0 => x"1000", 1 => x"0000", 2 => x"0200", 3 => x"0400", 4 => x"0600", 5 => x"0800", others => x"0000"),
     PORT_ADDR_MASK => (0 => 8, others => 9)
     )
@@ -233,7 +233,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler
 -- The MAPS Clock PLL
 ---------------------------------------------------------------------------    
 
- THE_MAPS_PLL : entity work.pll_in100_out80
+ THE_MAPS_PLL : entity work.pll_in100_out80   --currently: 200 MHz in!
    port map(
     CLK    => CLK_MAPS_IN,
     CLKOP  => clk_maps,