--- /dev/null
+\subsection{Function of the FPGA based online calibration}
+The FPGA based online calibration uses incoming TDC data (FineTime) to find the minimal and maximum FineTime value of each channel of each (connected) FPGA. The number of TDC data values from each channel for one calibration set is selectable via register \texttt{0xE001}. The default value is 100.000. The minimum of needed TDC values to create new calibration limits is set to 10.000.\\
+Each TDC FineTime value is used to generate the new calibration limits for the bunch of (per default) next 100.000 Hits in the corresponding channel.\\
+Depending on the Trb-Hardware, the entities need some adaption of the generics.\\
+The incoming TDC data words are build as shown in Tab. \ref{tab:DataPaket}.
+
+\begin{table}[htp]
+\centering
+\vspace{0.3cm}
+\begin{tabular}{|l|r|}
+\hline
+Bits & explanation \\
+\hline
+\hline
+31 & TDC time data marker\\ \hline
+30 - 29 & reserved \\ \hline
+28 - 22 & channel number\\ \hline
+21 - 12 & FineTime value\\ \hline
+11 & edge type; '1': rising edge '0': falling edge\\\hline
+10 - 0 & CoarseTime\\ \hline
+\end{tabular}
+\caption{Scheme of a TDC time data word.}
+\label{tab:DataPaket}
+\end{table}
+
+The principal functionality is shown in Fig. \ref{schematic:TDC}. The data words are feed in the calibration by port \texttt{DIN}. The other ports are used to keep the data flow and tell the calibration the origin of the data as well as the trigger type that was used to produce the data.
+
+\subsubsection{read\_cnt}
+
+\texttt{read\_cnt} is the entity that decides, wether the incomiong data should be calibrated or not. The Entity collects all incoming FPGA addresses and gives each 16bit FPGA-address a internal 5bit address for the usage of the pseudoDPRAM.
+
+\subsubsection{proc\_reg}
+\texttt{proc\_reg} is a process that handles all the BUS communication. There the registers for the calibration control as well as the monitoring are managed.
+
+\subsubsection{cnt\_val}
+\texttt{cnt\_val} handels the neccessary statistics that is needed to generate new calibration limits for the current channel.
+\newpage
+
+\begin{figure}[htp]
+\centering
+\vspace{10mm}
+\hspace{0.9cm}
+\includegraphics[scale=0.92]{figures/TdcOnlineCalSchematic.pdf}
+\end{figure}
+
+
+\begin{figure}[htp]
+\centering
+\vspace{6mm}
+\hspace{0mm}
+\includegraphics[scale=0.92]{figures/TdcOnlineCalSchematic_2.pdf}
+\caption{Schematic der TDC Kalibrierung.}
+\label{schematic:TDC}
+\end{figure}
+
+\newpage
+\subsubsection{Memory and Memory\_curr}
+\texttt{Memory} and \texttt{Memory\_curr} are running in parrallel with the entity \texttt{cnt\_val}. Here the Memory for saving the limits for the following calibration and for the current
+calibration is managed. These entitys send out the min and max values for the main-entity \texttt{Cal\_Limits\_v2}.
+
+\subsubsection{Cal\_Limits\_v2}
+\texttt{Cal\_Limits\_v2} is the main entity. The counter values, min/max of the current and the next calibration are coming together. The entity creates the new limits, saves them, and also calculates a delta value - the difference between min and max.
+
+\subsubsection{LUT}
+After a delay of one clockcycle the data is transported to \texttt{LUT}. LUT has a lookup table for the slope of the linear calibration. In dependece of the delta value the slope is read out and send out to the next entitiy. In addition the multiplication factor is generated by using the finetime value and the min value.
+The entity also generates a flag, if the fineTime value is, by sttaistical flucuations, out of the min/max range of the calibration. This happens more often, if the amount of data for new limits is small.
+
+\subsubsection{calc\_output}
+\texttt{calc\_output} is the last entity of the calibration. The factor and the slope are mutiplied and a constant value of 512 is added. This is done to round the result and have a higher precision.
+The calibration is designed to give a result between 0 and 1000. The fineTime in the data stream later (on the EB side) needs only a multiplication of 5ps to get the final value.
+
+\subsubsection{fine out}
+The process \texttt{fine out} takes all the new calibrated data values and inserts, depending on the flags \textit{overshoot}, \textit{undershoot},\textit{BUS\_do\_Cal} and \textit{do\_cal\_in}, them into the finetime position (Bits 21:12) of the time data word.\\
+In case that the value is out of the calibration range, the \textit{undershoot} (a value that is smaller than the limits) is set to 1010. In case of a \textit{overshoot} (value is greater than the limits) it is set to 1015.
+
+\newpage
+
+\subsection{How to use the code}
+
+The top entity of the FPGA based online calibration is in the file calibration.vhd~. The entities interface is shown in listing \ref{Top_Entity_Ports}. Dependign of the hardware the FPGA-board different setting have to be done.
+\vspace{5mm}
+
+
+\begin{lstlisting}[caption={Ports of the TDC calibration top entity.},label=Top_Entity_Ports,style=vhdl]
+entity TDC_Calibration is
+ generic (
+ IS_COMBINER : integer range 0 to 1 := c_YES;
+ USE_STAT_BITS : integer range 0 to 1 := c_NO;
+ USE_DATA_WRITE : integer range 0 to 1 := c_NO;
+ USE_DATA_FINISHED : integer range 0 to 1 := c_NO;
+ USE_BUSY_RELEASE : integer range 0 to 1 := c_NO );
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ DIN : in std_logic_vector(31 downto 0);
+ DIN_TYPE : in std_logic_vector( 3 downto 0);
+ DIN_READY : in std_logic;
+ DIN_STAT : in std_logic_vector((31*IS_COMBINER) downto 0);
+ FPGA_in : in std_logic_vector(15 downto 0);
+ TRIGG_TYPE : in std_logic_vector( 3 downto 0);
+ DOUT : out std_logic_vector(31 downto 0);
+ DOUT_TYPE : out std_logic_vector( 3 downto 0);
+ DOUT_READY : out std_logic;
+ DOUT_STAT : out std_logic_vector((31*IS_COMBINER) downto 0);
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX;
+ DIN_info : in std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0);
+ DOUT_info : out std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0)
+ );
+end TDC_Calibration;
+
+\end{lstlisting}
+
+
+%\lstinputlisting[style=VHDL,caption=Ports of the TDC calibration top entity. , label=Top_Entity_Ports]{top_ent_ports.vhd}
+
+\begin{itemize}
+\item \texttt{DIN} is the input of the 32 bit TDC words. The calibration code detects on its own wether its a head, a time data, a trailer or a EPOCH word.
+
+\item \texttt{DIN\_TYPE} is used for a Hub based system that uses the streaming api. This port indicates, wheter it is real FEE data or some overhead from the HUBs.
+
+\item \texttt{DIN\_READY} is also for HUB based systems. It indicates, wether the 32-bits are build together from the 16-bit words. And gives a signal if the 32-bit word is ready for further actions.
+
+\item \texttt{DIN\_STAT} is used for HUB setups to send the status bits through.\\ \textit{(Maybe it will later get merged with DIN\_info)}
+
+\item \texttt{FPGA\_in} is the input of the FPGA-address of the FEE-board that sends the current TDC information.
+
+\item \texttt{TRIGG\_TYPE} is the input of the trigger type. This allows a selection of the calibration on different trigger types.
+
+\item \texttt{DOUT\_*} is the corresponging output. Only the DOUT port will be different from the original input, if the input word was a time data word that was calibrated.
+
+\item \texttt{DIN\_info} and \texttt{DOUT\_info} are ports for the use with a direct connection to the TDC. The standard configuration of the code is for the use in a HUB like environment.
+\end{itemize}
+If the code is used in a DiRICH Combiner or other HUB like setup, the generic \texttt{IS\_COMBINER} should be set to \texttt{c\_YES}. The other four generics can be set to \texttt{c\_NO}. This saves some hardware due to a reduction of the \texttt{DIN\_info} and \texttt{DOUT\_info} ports in width.\\
+If the calibration is directly connected to a TDC, the \textit{readout\_tx\_array\_t} has tobe connected. Thus one needs 32-bits for a status register, 1-bit for \texttt{data\_write} flag, one for the \texttt{data\_finished} flag and one for the \texttt{busy\_release} flag. In this case, \texttt{IS\_COMBINER} can be set to \texttt{c\_NO} and the other four to \texttt{c\_YES}. In the case of a direct connection the FPGA address can be taken from \texttt{TIMER.network\_address}. The port \texttt{DIN\_TYPE} has to be set to \texttt{0x4}. \texttt{DIN\_READY} is constantly set to 1. The corresponding output ports can be \textbf{open}.
+
+
+\subsection{Slow Control and Flash values}
+
+The slow control BUS of TrbNet gives access to the calibration registers. The registers for the calibration can be choosen as the programmer wants. The registers should be at \texttt{0xE000} till \texttt{0xE1FF}.
+\[\texttt{trbcmd r <TrbAddress> <RegisterAddress>}\]
+is used to read values.
+\[\texttt{trbcmd w <TrbAddress> <RegisterAddress> <Data>}\]
+is used to write values.\\
+Table \ref{tab:SCregisters} gives an overview over the registers and its use.
+
+\begin{table}[htp]
+\centering
+\vspace{0.3cm}
+
+ \begin{tabular}{|l|r|}
+ \hline
+ Registers & explanation \\
+ \hline
+ \hline
+ \texttt{0xE000} & Control of the calibration (see remark 1)\\ \hline
+ \texttt{0xE001} & statistics for next calibration. (Default: 100.000) \\ \hline
+ \texttt{0xE002}-\texttt{0xE01F}& Debugging\\ \hline
+ \texttt{0xE020}-\texttt{0xE02F}& internal mapping of FPGA addresses (see remark 2)\\ \hline
+ \texttt{0xE030}-\texttt{0xE03F}& Min and Max of channel 0 (see remark 3)\\ \hline
+ \texttt{0xE040}-\texttt{0xE1FF}& Min and Max of channel 1 to 32 (see remark 4)\\ \hline
+ \end{tabular}
+ \caption{Register usage. The values between 0xE003 and 0xE1FF are read only. The write function is used to set standard limits.}
+ \label{tab:SCregisters}
+\end{table}
+
+\subsubsection{Remark 1: \texttt{0xE000}}
+The register \texttt{0xE000} is the main control register of the calibration.\\
+\texttt{Bit 0} is used to de-/activate the calibration. If the bit is 1, the incoming data values are calibrated with the current calibration limits. If the bit is 0, the data is send out uncalibrated as in a normal design.\\
+\texttt{Bit 4} is used to stop the generation of calibration limits. It is possible to stop the generation of calibration limits and still calibrate with the existing limits.\\
+\texttt{Bits 11:8} are used to set a triggertype for the calibration. If the value is \texttt{0x0}, all trigger types are accepted. If the value is e.g. \texttt{0xd}, only calibration trigger values are used to generate new calibration limits.
+
+\subsubsection{Remark 2: \texttt{0xE020 to 0xE02F}}
+The register \texttt{0xE020 to 0xE02F} are used to read out the mapping of the FPGA-addresses to the internal numbering. The last nibble indicates the internal numbering value.
+If address \texttt{0xE020} has a value of e.g. \texttt{0x1234}, the FPGA-address \texttt{0x1234} is mapped internally to 0.
+This address also indicates, where the corresponding channel limits can be found (see Remark 3 and 4). As one can directly see, a maximum number of 16 connected FPGAs is supported.
+
+\subsubsection{Remark 3: \texttt{0xE030 to 0xE03F}}
+The register \texttt{0xE030 to 0xE02F} include the limits of channel 0 of the corresponding FPGAs. To stay at the example from last remark, the value in \texttt{0xE030} would be the min and max limit of channel 0 of FPGA \texttt{0x1234}.
+The bits \texttt{9:0} contain the min value. The bits \texttt{19:10} the max value.
+
+\subsubsection{Remark 3: \texttt{0xE040 to 0xE1FF}}
+These registers contain the limits of channel 1 to 32 of each connected FPGA.
+The registers \texttt{0xE040} to \texttt{0xE05F} include the 32 channels of FPGA number 0.\\
+The registers \texttt{0xE060} to \texttt{0xE07F} include the 32 channels of FPGA number 1, and so on.\\
+To stay with the example, register \texttt{0xE040} would contain the limits of channel 1 of FPGA \texttt{0x1234}. Register \texttt{0xE50} would contain the limits of channel 17 of FPGA \texttt{0x1234}.
+Again, the bits \texttt{9:0} contain the min value and the bits \texttt{19:10} the max value.
+
+\subsubsection{WebTool}
+A webtool is available to see all the values and control the calibration. It is available on git at \url{http://jspc29.x-matter.uni-frankfurt.de/git/} in the repository daqtools under web/htdocs/tdc/tdc\_cal.htm~.
+
+\begin{figure}[htp]
+\centering
+\hspace{0mm}
+\includegraphics[scale=0.27]{figures/tdc_cal_web.png}
+\caption{Web Tool for the online calibration.}
+\label{schematic:TDC}
+\end{figure}
+
+
+\subsection{BugList}
+\subsection*{Date: 2018-11-19}
+\begin{itemize}
+ \item Reading flashed values is not tested/well implemented
+ \item Web Interface has problems, when setting Trigger Type at setup with direct TDC connection.
+ \item minor improvements in hardware usage could be done
+\end{itemize}
+
+%\vspace{4cm}
+%Ab Adresse \texttt{0xE007} wird der Standardwert der Kalibrierung der einzelnen Kanäle gesetzt. \texttt{0xE007} entspricht Kanal 0 von FPGA 0, \texttt{0xE008} ist Kanal 1 von FPGA 0 und soweiter. Bisher wird nur ein FPGA genutzt und somit wurde die Funktionalität auch lediglich für diesen einen implementiert. Eine Erweiterung auf mehrere FPGAs ist sehr schnell zu implementieren. Um den Min und den Max Wert zu übertragen, muss der Min Wert in den Bits 0-9 und der Max Wert in den Bits 10-19 des Datenfeldes der Slow Control Adressierung stehen. Da diese Adressen primär für den Flash-Speicher gedacht sind, ist es nicht zu empfehlen Werte manuell zu hinterlegen. Um in den Flash zu schreiben, wird das Programm \textit{flash\_settings.pl} aus \textit{daqtools/tools}\footnote{\url{http://jspc29.x-matter.uni-frankfurt.de/git/?p=daqtools.git;a=tree}} genutzt. Dem Programm wird der Name eine Liste der Registeradressen mit dem entsprechenden Werten und die TrbAdresse übergeben.\\
+%Um einer falschen Kalibrierung zu Beginn durch Temperaturwechsel entgegen zu wirken, ist es zu empfehlen die Min und Max Werte des Flash-Speichers bei signifikanten Änderungen der Temperatur zu erneuern.
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jspc29 / daqdocu.git / commitdiff
