relaxed timing

diff --git a/gbe_trb/base/tx_fifo.vhd b/gbe_trb/base/tx_fifo.vhd
index e2cf503390fcb00efd30a7766a5bdeb666feea53..9bd55d9f12802a6b6ba5567774b3fe169d7c89ba 100644 (file)
--- a/gbe_trb/base/tx_fifo.vhd
+++ b/gbe_trb/base/tx_fifo.vhd
@@ -58,13 +58,14 @@ architecture tx_fifo_arch of tx_fifo is
 -- state machine signals\r
 \r
 -- Signals\r
-  signal frames_avail    : unsigned(7 downto 0);\r
-  signal frame_written   : std_logic;\r
-  signal frame_read      : std_logic;\r
-  signal mac_fifoeof     : std_logic;\r
-  signal mac_tx_read     : std_logic;\r
-  signal frame_active    : std_logic;\r
-  signal fifo_wr         : std_logic;\r
+  signal frames_avail      : unsigned(7 downto 0);\r
+  signal frame_written_x   : std_logic;\r
+  signal frame_written     : std_logic;\r
+  signal frame_read        : std_logic;\r
+  signal mac_fifoeof       : std_logic;\r
+  signal mac_tx_read       : std_logic;\r
+  signal frame_active      : std_logic;\r
+  signal fifo_wr           : std_logic;\r
 \r
 begin\r
 \r
@@ -104,8 +105,10 @@ begin
   mac_tx_read <= MAC_TX_READ_IN when rising_edge(CLK);\r
 \r
   -- one frame written to FIFO\r
-  frame_written <= '1' when (FIFO_D_IN(8) = '1') and (FIFO_WR_IN = '1') and (frame_active = '1') else '0';\r
+  frame_written_x <= '1' when (FIFO_D_IN(8) = '1') and (FIFO_WR_IN = '1') and (frame_active = '1') else '0'; -- HERE\r
 \r
+  frame_written   <= frame_written_x when rising_edge(CLK);\r
+  \r
   -- one frame read from FIFO\r
   frame_read <= '1' when (mac_fifoeof = '1') and (mac_tx_read = '1') else '0';\r
 \r