*** empty log message ***

diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd
index b3ac922e76c19deb1a8b51232aa9610216b34a7d..88890f5cb812a89d09e13a08100ddec449be2183 100644 (file)
--- a/trb_net16_endpoint_hades_full.vhd
+++ b/trb_net16_endpoint_hades_full.vhd
@@ -44,6 +44,7 @@ entity trb_net16_endpoint_hades_full is
     REGIO_COMPILE_VERSION    : std_logic_vector(15 downto 0) := x"0001";
     REGIO_HARDWARE_VERSION   : std_logic_vector(31 downto 0) := x"12345678";
     REGIO_USE_1WIRE_INTERFACE: integer := c_YES; --c_YES,c_NO,c_MONITOR
+    REGIO_USE_VAR_ENDPOINT_ID: integer range c_NO to c_YES := c_NO;
     CLOCK_FREQUENCY          : integer range 1 to 200 := 100
     );
 
@@ -121,8 +122,9 @@ entity trb_net16_endpoint_hades_full is
     REGIO_IDRAM_ADDR_IN       : in  std_logic_vector(2 downto 0) := "000";
     REGIO_IDRAM_WR_IN         : in  std_logic := '0';
     REGIO_ONEWIRE_INOUT       : inout std_logic;  --temperature sensor
-    REGIO_ONEWIRE_MONITOR_IN  : in  std_logic;
+    REGIO_ONEWIRE_MONITOR_IN  : in  std_logic := '0';
     REGIO_ONEWIRE_MONITOR_OUT : out std_logic;
+    REGIO_VAR_ENDPOINT_ID     : in  std_logic_vector(15 downto 0) := (others => '0');
 
     TRIGGER_MONITOR_IN        : in  std_logic;  --strobe when timing trigger received
     GLOBAL_TIME_OUT           : out std_logic_vector(31 downto 0); --global time, microseconds
@@ -214,7 +216,10 @@ signal buf_IDRAM_DATA_IN       :  std_logic_vector(15 downto 0);
 signal buf_IDRAM_DATA_OUT      :  std_logic_vector(15 downto 0);
 signal buf_IDRAM_ADDR_IN       :  std_logic_vector(2 downto 0);
 signal buf_IDRAM_WR_IN         :  std_logic;
-signal reset_no_link          :  std_logic;
+signal reset_no_link           :  std_logic;
+signal ONEWIRE_DATA            :  std_logic_vector(15 downto 0);
+signal ONEWIRE_ADDR            :  std_logic_vector(2 downto 0);
+signal ONEWIRE_WRITE           :  std_logic;
 
   signal buf_COMMON_STAT_REG_STROBE :  std_logic_vector((std_COMSTATREG)-1 downto 0);
   signal buf_COMMON_CTRL_REG_STROBE :  std_logic_vector((std_COMCTRLREG)-1 downto 0);
@@ -563,9 +568,9 @@ begin
               STAT_ADDR_DEBUG        => STAT_ADDR_DEBUG
               );
           gen_no1wire : if REGIO_USE_1WIRE_INTERFACE = c_NO generate
-            buf_IDRAM_DATA_IN <= REGIO_IDRAM_DATA_IN;
-            buf_IDRAM_ADDR_IN <= REGIO_IDRAM_ADDR_IN;
-            buf_IDRAM_WR_IN   <= REGIO_IDRAM_WR_IN;
+            ONEWIRE_DATA  <= REGIO_IDRAM_DATA_IN;
+            ONEWIRE_ADDR  <= REGIO_IDRAM_ADDR_IN;
+            ONEWIRE_WRITE <= REGIO_IDRAM_WR_IN;
             REGIO_IDRAM_DATA_OUT <= buf_IDRAM_DATA_OUT;
             REGIO_ONEWIRE_INOUT <= '0';
             REGIO_ONEWIRE_MONITOR_OUT <= '0';
@@ -588,9 +593,9 @@ begin
                 ONEWIRE  => REGIO_ONEWIRE_INOUT,
                 MONITOR_OUT => REGIO_ONEWIRE_MONITOR_OUT,
                 --connection to id ram, according to memory map in TrbNetRegIO
-                DATA_OUT => buf_IDRAM_DATA_IN,
-                ADDR_OUT => buf_IDRAM_ADDR_IN,
-                WRITE_OUT=> buf_IDRAM_WR_IN,
+                DATA_OUT => ONEWIRE_DATA,
+                ADDR_OUT => ONEWIRE_ADDR,
+                WRITE_OUT=> ONEWIRE_WRITE,
                 TEMP_OUT => temperature,
                 STAT     => STAT_ONEWIRE
                 );
@@ -607,9 +612,9 @@ begin
                 --connection to 1-wire interface
                 MONITOR_IN => REGIO_ONEWIRE_MONITOR_IN,
                 --connection to id ram, according to memory map in TrbNetRegIO
-                DATA_OUT => buf_IDRAM_DATA_IN,
-                ADDR_OUT => buf_IDRAM_ADDR_IN,
-                WRITE_OUT=> buf_IDRAM_WR_IN,
+                DATA_OUT => ONEWIRE_DATA,
+                ADDR_OUT => ONEWIRE_ADDR,
+                WRITE_OUT=> ONEWIRE_WRITE,
                 TEMP_OUT => temperature,
                 STAT     => STAT_ONEWIRE
                 );
@@ -707,6 +712,26 @@ begin
       CTRL               => CTRL_MPLEX
       );
 
+-------------------------------------------------
+-- Include variable Endpoint ID
+-------------------------------------------------
+  gen_var_endpoint_id : if REGIO_USE_VAR_ENDPOINT_ID = c_YES generate
+    buf_IDRAM_DATA_IN  <= REGIO_VAR_ENDPOINT_ID when RESET = '1' else ONEWIRE_DATA;
+    buf_IDRAM_ADDR_IN  <= "100"                 when RESET = '1' else ONEWIRE_ADDR;
+    buf_IDRAM_WR_IN    <= '1'                   when RESET = '1' else ONEWIRE_WRITE;
+  end generate;
+
+  gen_no_var_endpoint_id : if REGIO_USE_VAR_ENDPOINT_ID = c_NO generate
+    buf_IDRAM_DATA_IN  <= ONEWIRE_DATA;
+    buf_IDRAM_ADDR_IN  <= ONEWIRE_ADDR;
+    buf_IDRAM_WR_IN    <= ONEWIRE_WRITE;
+  end generate;
+
+
+
+-------------------------------------------------
+-- Common Status Register
+-------------------------------------------------
   proc_gen_common_stat_regs : process(REGIO_COMMON_STAT_REG_IN, trigger_number_match, temperature, int_trigger_num)
     begin
       buf_COMMON_STAT_REG_IN(3 downto 0)   <= REGIO_COMMON_STAT_REG_IN(3 downto 0);

diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd
index dd935c2d6f3fd47c87cdd61d99f958e745cf82a7..919e938898dbbce16b466b888700214efa446877 100644 (file)
--- a/trb_net16_hub_base.vhd
+++ b/trb_net16_hub_base.vhd
@@ -23,6 +23,7 @@ entity trb_net16_hub_base is
     COMPILE_TIME            : std_logic_vector(31 downto 0) := x"00000000";
     COMPILE_VERSION         : std_logic_vector(15 downto 0) := x"0001";
     INIT_ENDPOINT_ID        : std_logic_vector(15 downto 0) := x"0001";
+    USE_VAR_ENDPOINT_ID     : integer range c_NO to c_YES := c_NO;
     HARDWARE_VERSION        : std_logic_vector(31 downto 0) := x"12345678";
     CLOCK_FREQUENCY         : integer range 1 to 200 := 100;
     USE_ONEWIRE             : integer range 0 to 2 := c_YES;
@@ -69,36 +70,37 @@ entity trb_net16_hub_base is
     INT_REPLY_DATA_IN         : in  std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0) := (others => '0');
     INT_REPLY_PACKET_NUM_IN   : in  std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0) := (others => '0');
     INT_REPLY_READ_OUT        : out std_logic_vector (INT_NUMBER downto 0);
-    ONEWIRE               : inout std_logic;
-    ONEWIRE_MONITOR_IN    : in  std_logic := '0';
-    ONEWIRE_MONITOR_OUT   : out std_logic;
-    COMMON_STAT_REGS : in  std_logic_vector (std_COMSTATREG*32-1 downto 0) := (others => '0');  --Status of common STAT regs
-    COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0);  --Status of common STAT regs
-    MY_ADDRESS_OUT   : out std_logic_vector (15 downto 0);
+    ONEWIRE                      : inout std_logic;
+    ONEWIRE_MONITOR_IN           : in  std_logic := '0';
+    ONEWIRE_MONITOR_OUT          : out std_logic;
+    COMMON_STAT_REGS             : in  std_logic_vector (std_COMSTATREG*32-1 downto 0) := (others => '0');  --Status of common STAT regs
+    COMMON_CTRL_REGS             : out std_logic_vector (std_COMCTRLREG*32-1 downto 0);  --Status of common STAT regs
+    MY_ADDRESS_OUT               : out std_logic_vector (15 downto 0);
     --REGIO INTERFACE
-    REGIO_ADDR_OUT            : out std_logic_vector(16-1 downto 0);
-    REGIO_READ_ENABLE_OUT     : out std_logic;
-    REGIO_WRITE_ENABLE_OUT    : out std_logic;
-    REGIO_DATA_OUT            : out std_logic_vector(32-1 downto 0);
-    REGIO_DATA_IN             : in  std_logic_vector(32-1 downto 0) := (others => '0');
-    REGIO_DATAREADY_IN        : in  std_logic := '0';
-    REGIO_NO_MORE_DATA_IN     : in  std_logic := '0';
-    REGIO_WRITE_ACK_IN        : in  std_logic := '0';
-    REGIO_UNKNOWN_ADDR_IN     : in  std_logic := '0';
-    REGIO_TIMEOUT_OUT         : out std_logic;
-    TIMER_TICKS_OUT           : out std_logic_vector(1 downto 0);
+    REGIO_ADDR_OUT               : out std_logic_vector(16-1 downto 0);
+    REGIO_READ_ENABLE_OUT        : out std_logic;
+    REGIO_WRITE_ENABLE_OUT       : out std_logic;
+    REGIO_DATA_OUT               : out std_logic_vector(32-1 downto 0);
+    REGIO_DATA_IN                : in  std_logic_vector(32-1 downto 0) := (others => '0');
+    REGIO_DATAREADY_IN           : in  std_logic := '0';
+    REGIO_NO_MORE_DATA_IN        : in  std_logic := '0';
+    REGIO_WRITE_ACK_IN           : in  std_logic := '0';
+    REGIO_UNKNOWN_ADDR_IN        : in  std_logic := '0';
+    REGIO_TIMEOUT_OUT            : out std_logic;
+    REGIO_VAR_ENDPOINT_ID        : in  std_logic_vector(15 downto 0) := (others => '0');
+    TIMER_TICKS_OUT              : out std_logic_vector(1 downto 0);
 
     --Fixed status and control ports
-    HUB_STAT_CHANNEL      : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
-    HUB_STAT_GEN          : out std_logic_vector (31 downto 0);
-    MPLEX_CTRL            : in  std_logic_vector (MII_NUMBER*32-1 downto 0);
-    MPLEX_STAT            : out std_logic_vector (MII_NUMBER*32-1 downto 0);
-    STAT_REGS             : out std_logic_vector (16*32-1 downto 0);  --Status of custom STAT regs
-    STAT_CTRL_REGS        : out std_logic_vector (8*32-1 downto 0);  --Status of custom CTRL regs
+    HUB_STAT_CHANNEL             : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
+    HUB_STAT_GEN                 : out std_logic_vector (31 downto 0);
+    MPLEX_CTRL                   : in  std_logic_vector (MII_NUMBER*32-1 downto 0);
+    MPLEX_STAT                   : out std_logic_vector (MII_NUMBER*32-1 downto 0);
+    STAT_REGS                    : out std_logic_vector (16*32-1 downto 0);  --Status of custom STAT regs
+    STAT_CTRL_REGS               : out std_logic_vector (8*32-1 downto 0);  --Status of custom CTRL regs
 
     --Debugging registers
-    STAT_DEBUG            : out std_logic_vector (31 downto 0);      --free status regs for debugging
-    CTRL_DEBUG            : in  std_logic_vector (31 downto 0)      --free control regs for debugging
+    STAT_DEBUG                   : out std_logic_vector (31 downto 0);      --free status regs for debugging
+    CTRL_DEBUG                   : in  std_logic_vector (31 downto 0)      --free control regs for debugging
      -- bits 0-2 are NOT (inverted) error of streaming port
     );
 end entity;
@@ -221,6 +223,9 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is
   signal IDRAM_WR_IN : std_logic;
   signal IDRAM_ADDR_IN : std_logic_vector(2 downto 0);
   signal TEMP_OUT : std_logic_vector(11 downto 0);
+  signal ONEWIRE_DATA            :  std_logic_vector(15 downto 0);
+  signal ONEWIRE_ADDR            :  std_logic_vector(2 downto 0);
+  signal ONEWIRE_WRITE           :  std_logic;
 
   signal global_time : std_logic_vector(31 downto 0);
   signal local_time  : std_logic_vector(7 downto 0);
@@ -995,9 +1000,9 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler
         ONEWIRE  => ONEWIRE,
         MONITOR_OUT => ONEWIRE_MONITOR_OUT,
         --connection to id ram, according to memory map in TrbNetRegIO
-        DATA_OUT => IDRAM_DATA_IN,
-        ADDR_OUT => IDRAM_ADDR_IN,
-        WRITE_OUT=> IDRAM_WR_IN,
+        DATA_OUT => ONEWIRE_DATA,
+        ADDR_OUT => ONEWIRE_ADDR,
+        WRITE_OUT=> ONEWIRE_WRITE,
         TEMP_OUT => TEMP_OUT,
         STAT     => open
         );
@@ -1012,15 +1017,28 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler
         --connection to 1-wire interface
         MONITOR_IN => ONEWIRE_MONITOR_IN,
         --connection to id ram, according to memory map in TrbNetRegIO
-        DATA_OUT => IDRAM_DATA_IN,
-        ADDR_OUT => IDRAM_ADDR_IN,
-        WRITE_OUT=> IDRAM_WR_IN,
+        DATA_OUT => ONEWIRE_DATA,
+        ADDR_OUT => ONEWIRE_ADDR,
+        WRITE_OUT=> ONEWIRE_WRITE,
         TEMP_OUT => TEMP_OUT,
         STAT     => open
         );
   end generate;
 
+-------------------------------------------------
+-- Include variable Endpoint ID
+-------------------------------------------------
+  gen_var_endpoint_id : if USE_VAR_ENDPOINT_ID = c_YES generate
+    IDRAM_DATA_IN  <= REGIO_VAR_ENDPOINT_ID when RESET = '1' else ONEWIRE_DATA;
+    IDRAM_ADDR_IN  <= "100"                 when RESET = '1' else ONEWIRE_ADDR;
+    IDRAM_WR_IN    <= '1'                   when RESET = '1' else ONEWIRE_WRITE;
+  end generate;
 
+  gen_no_var_endpoint_id : if USE_VAR_ENDPOINT_ID = c_NO generate
+    IDRAM_DATA_IN  <= ONEWIRE_DATA;
+    IDRAM_ADDR_IN  <= ONEWIRE_ADDR;
+    IDRAM_WR_IN    <= ONEWIRE_WRITE;
+  end generate;
 
 ---------------------------------------------------------------------
 --Status of media interfaces

diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd
index dd90ca14d2205515fda40e57f06c01294bc17ec6..43cec47c040aaadaae208968a23a67abd4de9f6e 100644 (file)
--- a/trb_net16_hub_func.vhd
+++ b/trb_net16_hub_func.vhd
@@ -97,6 +97,7 @@ package trb_net16_hub_func is
     COMPILE_TIME            : std_logic_vector(31 downto 0) := x"00000000";
     COMPILE_VERSION         : std_logic_vector(15 downto 0) := x"0001";
     INIT_ENDPOINT_ID        : std_logic_vector(15 downto 0)  := x"0001";
+    USE_VAR_ENDPOINT_ID     : integer range c_NO to c_YES := c_NO;
     HARDWARE_VERSION        : std_logic_vector(31 downto 0) := x"12345678";
     CLOCK_FREQUENCY         : integer range 1 to 200 := 100;
     USE_ONEWIRE             : integer range 0 to 2 := c_YES;
@@ -154,6 +155,7 @@ package trb_net16_hub_func is
     REGIO_WRITE_ACK_IN        : in  std_logic := '0';
     REGIO_UNKNOWN_ADDR_IN     : in  std_logic := '0';
     REGIO_TIMEOUT_OUT         : out std_logic;
+    REGIO_VAR_ENDPOINT_ID        : in  std_logic_vector(15 downto 0) := (others => '0');
     TIMER_TICKS_OUT           : out std_logic_vector(1 downto 0);
     ONEWIRE               : inout std_logic;
     ONEWIRE_MONITOR_IN    : in  std_logic;

diff --git a/trb_net_components.vhd b/trb_net_components.vhd
index eb233587880869f66f981e525c6b478153608225..f973ec5c0f28ec62f43d706d9cdbc3986e8b9f11 100644 (file)
--- a/trb_net_components.vhd
+++ b/trb_net_components.vhd
@@ -320,6 +320,7 @@ package trb_net_components is
       REGIO_COMPILE_VERSION    : std_logic_vector(15 downto 0) := x"0001";
       REGIO_HARDWARE_VERSION   : std_logic_vector(31 downto 0) := x"12345678";
       REGIO_USE_1WIRE_INTERFACE: integer := c_YES; --c_YES,c_NO,c_MONITOR
+      REGIO_USE_VAR_ENDPOINT_ID: integer range c_NO to c_YES := c_NO;
       CLOCK_FREQUENCY          : integer range 1 to 200 := 100
       );
 
@@ -399,6 +400,7 @@ package trb_net_components is
       REGIO_ONEWIRE_INOUT       : inout std_logic;
       REGIO_ONEWIRE_MONITOR_IN  : in  std_logic := '0';
       REGIO_ONEWIRE_MONITOR_OUT : out std_logic;
+      REGIO_VAR_ENDPOINT_ID     : in  std_logic_vector(15 downto 0) := (others => '0');
 
       TRIGGER_MONITOR_IN        : in  std_logic;  --strobe when timing trigger received
       GLOBAL_TIME_OUT           : out std_logic_vector(31 downto 0); --global time, microseconds
@@ -1480,6 +1482,15 @@ package trb_net_components is
   end component;
 
 
+  component pll_in100_out25 is
+    port (
+      CLK: in std_logic;
+      CLKOP: out std_logic;
+      LOCK: out std_logic
+      );
+  end component;
+
+
   component pll25 is
     port(
       CLK  : in  std_logic;