set_option -disable_io_insertion 0
set_option -retiming 0
set_option -pipe 0
-#set_option -force_gsr
set_option -force_gsr false
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
add_file -vhdl -lib work "version.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
-add_file -vhdl -lib "work" "../base/trb3_components.vhd"
-
-add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
-add_file -vhdl -lib "work" "./trb3_central.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd"
+add_file -vhdl -lib work "../base/trb3_components.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
+
+
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf4.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf3.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf2.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
+
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo_dualclock_width_16_reg.vhd"
+
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
+
+
+add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd"
+
+add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd"
+add_file -vhdl -lib work "./trb3_central.vhd"
use work.trb_net_std.all;
use work.trb_net_components.all;
use work.trb3_components.all;
+use work.trb_net16_hub_func.all;
use work.version.all;
CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 1/0, off, 125 MHz possible
--SFP
- SFP_TX_FAULT : in std_logic_vector(7 downto 0); --TX broken
- SFP_RATE_SEL : out std_logic_vector(7 downto 0); --not supported by our SFP
- SFP_LOS : in std_logic_vector(7 downto 0); --Loss of signal
- SFP_MOD0 : in std_logic_vector(7 downto 0); --SFP present
- SFP_MOD1 : in std_logic_vector(7 downto 0); --I2C interface
- SFP_MOD2 : in std_logic_vector(7 downto 0); --I2C interface
- SFP_TXDIS : out std_logic_vector(7 downto 0); --disable TX
+ SFP_RX_P : in std_logic_vector(8 downto 1);
+ SFP_RX_N : in std_logic_vector(8 downto 1);
+ SFP_TX_P : out std_logic_vector(8 downto 1);
+ SFP_TX_N : out std_logic_vector(8 downto 1);
+ SFP_TX_FAULT : in std_logic_vector(8 downto 1); --TX broken
+ SFP_RATE_SEL : out std_logic_vector(8 downto 1); --not supported by our SFP
+ SFP_LOS : in std_logic_vector(8 downto 1); --Loss of signal
+ SFP_MOD0 : in std_logic_vector(8 downto 1); --SFP present
+ SFP_MOD1 : in std_logic_vector(8 downto 1); --I2C interface
+ SFP_MOD2 : in std_logic_vector(8 downto 1); --I2C interface
+ SFP_TXDIS : out std_logic_vector(8 downto 1); --disable TX
--Clock and Trigger Control
TRIGGER_SELECT : out std_logic; --trigger select for fan-out. 0: external, 1: signal from FPGA5
end entity;
architecture trb3_central_arch of trb3_central is
-
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
-
+ signal clear_i : std_logic;
+ signal reset_i : std_logic;
+ signal GSR_N : std_logic;
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
--FPGA Test
signal time_counter : unsigned(31 downto 0);
+
+ --Media Interface
+ signal med_stat_op : std_logic_vector (5*16-1 downto 0);
+ signal med_ctrl_op : std_logic_vector (5*16-1 downto 0);
+ signal med_stat_debug : std_logic_vector (5*64-1 downto 0);
+ signal med_ctrl_debug : std_logic_vector (5*64-1 downto 0);
+ signal med_data_out : std_logic_vector (5*16-1 downto 0);
+ signal med_packet_num_out : std_logic_vector (5*3-1 downto 0);
+ signal med_dataready_out : std_logic_vector (5*1-1 downto 0);
+ signal med_read_out : std_logic_vector (5*1-1 downto 0);
+ signal med_data_in : std_logic_vector (5*16-1 downto 0);
+ signal med_packet_num_in : std_logic_vector (5*3-1 downto 0);
+ signal med_dataready_in : std_logic_vector (5*1-1 downto 0);
+ signal med_read_in : std_logic_vector (5*1-1 downto 0);
+
+ --Hub
+ signal common_stat_regs : std_logic_vector (std_COMSTATREG*32-1 downto 0);
+ signal common_ctrl_regs : std_logic_vector (std_COMCTRLREG*32-1 downto 0);
+ signal my_address : std_logic_vector (16-1 downto 0);
+ signal regio_addr_out : std_logic_vector (16-1 downto 0);
+ signal regio_read_enable_out : std_logic;
+ signal regio_write_enable_out : std_logic;
+ signal regio_data_out : std_logic_vector (32-1 downto 0);
+ signal regio_data_in : std_logic_vector (32-1 downto 0);
+ signal regio_dataready_in : std_logic;
+ signal regio_no_more_data_in : std_logic;
+ signal regio_write_ack_in : std_logic;
+ signal regio_unknown_addr_in : std_logic;
+ signal regio_timeout_out : std_logic;
+
+ signal spictrl_read_en : std_logic;
+ signal spictrl_write_en : std_logic;
+ signal spictrl_data_in : std_logic_vector(31 downto 0);
+ signal spictrl_addr : std_logic;
+ signal spictrl_data_out : std_logic_vector(31 downto 0);
+ signal spictrl_ack : std_logic;
+ signal spictrl_busy : std_logic;
+ signal spimem_read_en : std_logic;
+ signal spimem_write_en : std_logic;
+ signal spimem_data_in : std_logic_vector(31 downto 0);
+ signal spimem_addr : std_logic_vector(5 downto 0);
+ signal spimem_data_out : std_logic_vector(31 downto 0);
+ signal spimem_ack : std_logic;
+
+ signal spi_bram_addr : std_logic_vector(7 downto 0);
+ signal spi_bram_wr_d : std_logic_vector(7 downto 0);
+ signal spi_bram_rd_d : std_logic_vector(7 downto 0);
+ signal spi_bram_we : std_logic;
+
+ signal delayed_restart_fpga : std_logic;
+ signal restart_fpga_counter : unsigned(11 downto 0);
+
begin
+---------------------------------------------------------------------------
+-- Reset Generation
+---------------------------------------------------------------------------
+
+GSR_N <= pll_lock;
+
+THE_RESET_HANDLER : trb_net_reset_handler
+ generic map(
+ RESET_DELAY => x"FEEE"
+ )
+ port map(
+ CLEAR_IN => '0', -- reset input (high active, async)
+ CLEAR_N_IN => '1', -- reset input (low active, async)
+ CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL!
+ SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock
+ PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
+ RESET_IN => '0', -- general reset signal (SYSCLK)
+ TRB_RESET_IN => med_stat_op(4*16+13), -- TRBnet reset signal (SYSCLK)
+ CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
+ DEBUG_OUT => open
+ );
+
---------------------------------------------------------------------------
-- Clock Handling
---------------------------------------------------------------------------
- THE_MAIN_PLL : pll_in200_out100
- port map(
- CLK => CLK_GPLL_LEFT,
- CLKOP => clk_100_i,
- CLKOK => clk_200_i,
- LOCK => pll_lock
- );
+THE_MAIN_PLL : pll_in200_out100
+ port map(
+ CLK => CLK_GPLL_LEFT,
+ CLKOP => clk_100_i,
+ CLKOK => clk_200_i,
+ LOCK => pll_lock
+ );
+
+
+---------------------------------------------------------------------------
+-- The TrbNet media interface (Uplink)
+---------------------------------------------------------------------------
+THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
+ generic map(
+ SERDES_NUM => 0, --number of serdes in quad
+ EXT_CLOCK => c_NO, --use internal clock
+ USE_200_MHZ => c_YES --run on 200 MHz clock
+ )
+ port map(
+ CLK => clk_200_i,
+ SYSCLK => clk_100_i,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ CLK_EN => '1',
+ --Internal Connection
+ MED_DATA_IN => med_data_out(79 downto 64),
+ MED_PACKET_NUM_IN => med_packet_num_out(14 downto 12),
+ MED_DATAREADY_IN => med_dataready_out(4),
+ MED_READ_OUT => med_read_in(4),
+ MED_DATA_OUT => med_data_in(79 downto 64),
+ MED_PACKET_NUM_OUT => med_packet_num_in(14 downto 12),
+ MED_DATAREADY_OUT => med_dataready_in(4),
+ MED_READ_IN => med_read_out(4),
+ REFCLK2CORE_OUT => open,
+ --SFP Connection
+ SD_RXD_P_IN => SFP_RX_P(1),
+ SD_RXD_N_IN => SFP_RX_N(1),
+ SD_TXD_P_OUT => SFP_TX_P(1),
+ SD_TXD_N_OUT => SFP_TX_N(1),
+ SD_REFCLK_P_IN => open,
+ SD_REFCLK_N_IN => open,
+ SD_PRSNT_N_IN => SFP_MOD0(1),
+ SD_LOS_IN => SFP_LOS(1),
+ SD_TXDIS_OUT => SFP_TXDIS(1),
+ -- Status and control port
+ STAT_OP => med_stat_op(79 downto 64),
+ CTRL_OP => med_ctrl_op(79 downto 64),
+ STAT_DEBUG => med_stat_debug(4*64+63 downto 4*64),
+ CTRL_DEBUG => (others => '0')
+ );
+
+
+SFP_TXDIS(8 downto 2) <= (others => '1');
+
+
+---------------------------------------------------------------------------
+-- The TrbNet media interface (to other FPGA)
+---------------------------------------------------------------------------
+med_stat_op(63 downto 0) <= x"0007000700070007";
+
+
+---------------------------------------------------------------------------
+-- The TrbNet Hub
+---------------------------------------------------------------------------
+
+THE_HUB : trb_net16_hub_base
+ generic map (
+ HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES),
+ IBUF_SECURE_MODE => c_YES,
+ MII_NUMBER => 5,
+ MII_IS_UPLINK => (4 => 1, others => 0),
+ MII_IS_DOWNLINK => (4 => 0, others => 1),
+ MII_IS_UPLINK_ONLY=> (4 => 1, others => 0),
+ INT_NUMBER => 0,
+ INT_CHANNELS => (0,1,3,3,3,3,3,3),
+ USE_ONEWIRE => c_YES,
+ COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
+ HARDWARE_VERSION => x"90000000",
+ INIT_ENDPOINT_ID => x"0005",
+ INIT_ADDRESS => x"F305",
+ BROADCAST_SPECIAL_ADDR => x"15"
+ )
+ port map (
+ CLK => clk_100_i,
+ RESET => reset_i,
+ CLK_EN => '1',
+
+ --Media interfacces
+ MED_DATAREADY_OUT(5*1-1 downto 0) => med_dataready_out,
+ MED_DATA_OUT(5*16-1 downto 0) => med_data_out,
+ MED_PACKET_NUM_OUT(5*3-1 downto 0) => med_packet_num_out,
+ MED_READ_IN(5*1-1 downto 0) => med_read_in,
+ MED_DATAREADY_IN(5*1-1 downto 0) => med_dataready_in,
+ MED_DATA_IN(5*16-1 downto 0) => med_data_in,
+ MED_PACKET_NUM_IN(5*3-1 downto 0) => med_packet_num_in,
+ MED_READ_OUT(5*1-1 downto 0) => med_read_out,
+ MED_STAT_OP(5*16-1 downto 0) => med_stat_op,
+ MED_CTRL_OP(5*16-1 downto 0) => med_ctrl_op,
+
+ COMMON_STAT_REGS => common_stat_regs,
+ COMMON_CTRL_REGS => common_ctrl_regs,
+ MY_ADDRESS_OUT => my_address,
+ --REGIO INTERFACE
+ REGIO_ADDR_OUT => regio_addr_out,
+ REGIO_READ_ENABLE_OUT => regio_read_enable_out,
+ REGIO_WRITE_ENABLE_OUT => regio_write_enable_out,
+ REGIO_DATA_OUT => regio_data_out,
+ REGIO_DATA_IN => regio_data_in,
+ REGIO_DATAREADY_IN => regio_dataready_in,
+ REGIO_NO_MORE_DATA_IN => regio_no_more_data_in,
+ REGIO_WRITE_ACK_IN => regio_write_ack_in,
+ REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
+ REGIO_TIMEOUT_OUT => regio_timeout_out,
+
+ ONEWIRE => TEMPSENS,
+ ONEWIRE_MONITOR_OUT => open,
+ --Status ports (for debugging)
+ MPLEX_CTRL => (others => '0'),
+ CTRL_DEBUG => (others => '0'),
+ STAT_DEBUG => open
+ );
+
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+THE_BUS_HANDLER : trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 2,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 1, 1 => 6, others => 0)
+ )
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+
+ DAT_ADDR_IN => regio_addr_out,
+ DAT_DATA_IN => regio_data_out,
+ DAT_DATA_OUT => regio_data_in,
+ DAT_READ_ENABLE_IN => regio_read_enable_out,
+ DAT_WRITE_ENABLE_IN => regio_write_enable_out,
+ DAT_TIMEOUT_IN => regio_timeout_out,
+ DAT_DATAREADY_OUT => regio_dataready_in,
+ DAT_WRITE_ACK_OUT => regio_write_ack_in,
+ DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
+ DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
+
+ --Bus Handler (SPI CTRL)
+ BUS_READ_ENABLE_OUT(0) => spictrl_read_en,
+ BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en,
+ BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in,
+ BUS_ADDR_OUT(0*16) => spictrl_addr,
+ BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
+ BUS_TIMEOUT_OUT(0) => open,
+ BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out,
+ BUS_DATAREADY_IN(0) => spictrl_ack,
+ BUS_WRITE_ACK_IN(0) => spictrl_ack,
+ BUS_NO_MORE_DATA_IN(0) => spictrl_busy,
+ BUS_UNKNOWN_ADDR_IN(0) => '0',
+ --Bus Handler (SPI Memory)
+ BUS_READ_ENABLE_OUT(1) => spimem_read_en,
+ BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,
+ BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in,
+ BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr,
+ BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
+ BUS_TIMEOUT_OUT(1) => open,
+ BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out,
+ BUS_DATAREADY_IN(1) => spimem_ack,
+ BUS_WRITE_ACK_IN(1) => spimem_ack,
+ BUS_NO_MORE_DATA_IN(1) => '0',
+ BUS_UNKNOWN_ADDR_IN(1) => '0',
+
+ STAT_DEBUG => open
+ );
+---------------------------------------------------------------------------
+-- SPI / Flash
+---------------------------------------------------------------------------
+
+THE_SPI_MASTER: spi_master
+ port map(
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ -- Slave bus
+ BUS_READ_IN => spictrl_read_en,
+ BUS_WRITE_IN => spictrl_write_en,
+ BUS_BUSY_OUT => spictrl_busy,
+ BUS_ACK_OUT => spictrl_ack,
+ BUS_ADDR_IN(0) => spictrl_addr,
+ BUS_DATA_IN => spictrl_data_in,
+ BUS_DATA_OUT => spictrl_data_out,
+ -- SPI connections
+ SPI_CS_OUT => FLASH_CS,
+ SPI_SDI_IN => FLASH_DOUT,
+ SPI_SDO_OUT => FLASH_CIN,
+ SPI_SCK_OUT => FLASH_CLK,
+ -- BRAM for read/write data
+ BRAM_A_OUT => spi_bram_addr,
+ BRAM_WR_D_IN => spi_bram_wr_d,
+ BRAM_RD_D_OUT => spi_bram_rd_d,
+ BRAM_WE_OUT => spi_bram_we,
+ -- Status lines
+ STAT => open
+ );
+
+-- data memory for SPI accesses
+THE_SPI_MEMORY: spi_databus_memory
+ port map(
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ -- Slave bus
+ BUS_ADDR_IN => spimem_addr,
+ BUS_READ_IN => spimem_read_en,
+ BUS_WRITE_IN => spimem_write_en,
+ BUS_ACK_OUT => spimem_ack,
+ BUS_DATA_IN => spimem_data_in,
+ BUS_DATA_OUT => spimem_data_out,
+ -- state machine connections
+ BRAM_ADDR_IN => spi_bram_addr,
+ BRAM_WR_D_OUT => spi_bram_wr_d,
+ BRAM_RD_D_IN => spi_bram_rd_d,
+ BRAM_WE_IN => spi_bram_we,
+ -- Status lines
+ STAT => open
+ );
+
+---------------------------------------------------------------------------
+-- Reboot FPGA
+---------------------------------------------------------------------------
+ PROC_REBOOT : process
+ begin
+ wait until rising_edge(clk_100_i);
+ if reset_i = '1' then
+ PROGRAMN <= '1';
+ delayed_restart_fpga <= '0';
+ restart_fpga_counter <= x"FFF";
+ else
+ PROGRAMN <= not delayed_restart_fpga;
+ delayed_restart_fpga <= '0';
+ if common_ctrl_regs(15) = '1' then
+ restart_fpga_counter <= x"000";
+ elsif restart_fpga_counter /= x"FFF" then
+ restart_fpga_counter <= restart_fpga_counter + 1;
+ if restart_fpga_counter >= x"F00" then
+ delayed_restart_fpga <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
---------------------------------------------------------------------------
-- Clock and Trigger Configuration
TRIGGER_OUT <= '0';
- SFP_TXDIS <= (others => '0');
---------------------------------------------------------------------------
-- FPGA communication
---------------------------------------------------------------------------
FPGA4_CONNECTOR <= (others => 'Z');
----------------------------------------------------------------------------
--- Flash ROM
----------------------------------------------------------------------------
- FLASH_CLK <= '0';
- FLASH_CS <= '0';
- FLASH_CIN <= '0';
- PROGRAMN <= '1';
-
---------------------------------------------------------------------------
-- Big AddOn Connector
---------------------------------------------------------------------------
---------------------------------------------------------------------------
LED_CLOCK_GREEN <= '0';
LED_CLOCK_RED <= '1';
- LED_GREEN <= not time_counter(24);
- LED_ORANGE <= not time_counter(25);
- LED_RED <= not time_counter(26);
- LED_TRIGGER_GREEN <= '0';
- LED_TRIGGER_RED <= '1';
- LED_YELLOW <= not time_counter(27);
+ LED_GREEN <= '0';
+ LED_ORANGE <= '1';
+ LED_RED <= '1';
+ LED_TRIGGER_GREEN <= not med_stat_op(4*16+9);
+ LED_TRIGGER_RED <= not (med_stat_op(4*16+11) or med_stat_op(4*16+10));
+ LED_YELLOW <= '1';
---------------------------------------------------------------------------
<Options/>
<Implementation title="trb3_central" dir="trb3_central" description="trb3_central" default_strategy="Strategy1">
<Options/>
- <Source name="../../base/trb3_central.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
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jspc29 / trb3.git / commitdiff