signal beam_inhibit_cntr_up, beam_inhibit_cntr_rst, internal_beam_inhibit : std_logic;
signal beam_inhibit_cntr,beam_inhibit_length_in_buf : std_logic_vector(31 downto 0);
-
+
signal reset_length : std_logic;
signal reset_cntr_after_enable : std_logic;
if rising_edge(TRIGGER_CLK) then
if RESET = '1' or START_BEAM_IN = '1' or BEAM_INHIBIT_LENGTH_IN = 0 or reset_length = '1' then
internal_beam_inhibit <= '0';
- elsif beam_inhibit_cntr = BEAM_INHIBIT_LENGTH_IN then
+ elsif beam_inhibit_cntr = beam_inhibit_length_in_buf then
internal_beam_inhibit <= '1';
else
internal_beam_inhibit <= internal_beam_inhibit;
CLK : in std_logic;
EDGE_CLK : in std_logic;
TRIG_IN : in std_logic_vector(63 downto 0);
- TRIG_OUT : out std_logic_vector(TRIGGER_INPUTS_NUMBER*4-1 downto 0);
+ TRIG_OUT : out std_logic_vector((TRIGGER_INPUTS_NUMBER+8)*4-1 downto 0);
FAST_LVDS_TIMING_IN : in std_logic_vector(3 downto 0);
FAST_PECL_TIMING_IN : in std_logic_vector(3 downto 0);
FAST_MDCA_TIMING_IN : in std_logic_vector(3 downto 0);
PECL_TIMING_OUT : out std_logic_vector(2 downto 0);
START_VETO_STRUCTURE_OUT : out std_logic_vector(23 downto 0);
HIST_DISABLE_IN : in std_logic_vector(39 downto 0);
- TRIG_CNTRL_IN : in std_logic_vector(7 downto 0);
+ TRIG_CNTRL_IN : in std_logic_vector(9 downto 0);
TRIG_STAT_OUT : out std_logic_vector(7 downto 0)
);
end component;
CLK_100 : in std_logic;
RESET : in std_logic;
EMERGENCY_STOP : in std_logic;
- TRIGGER_IN : in std_logic_vector(TRIGGER_INPUTS_NUMBER-1 downto 0);
- INPUT_ENABLE_IN : in std_logic_vector(TRIGGER_INPUTS_NUMBER-1 downto 0);
+ TRIGGER_IN : in std_logic_vector((TRIGGER_INPUTS_NUMBER+8)*4-1 downto 0);
+ INPUT_ENABLE_IN : in std_logic_vector(TRIGGER_INPUTS_NUMBER + 8 -1 downto 0);
DOWNSCALE_REGISTER_IN : in std_logic_vector((4*(TRIGGER_INPUTS_NUMBER)-1) downto 0);
- DELAY_TRIGGER_REGISTER_IN : in std_logic_vector((4*(TRIGGER_INPUTS_NUMBER)-1) downto 0);
+ DELAY_TRIGGER_REGISTER_IN : in std_logic_vector((4*(TRIGGER_INPUTS_NUMBER + 8)-1) downto 0);
DELAY_LARGE_TRIGGER_REGISTER_IN : in std_logic_vector((8*(12)-1) downto 0);
WIDTH_REGISTER_IN : in std_logic_vector((4*(TRIGGER_INPUTS_NUMBER+9)-1) downto 0);
WIDTH_REGISTER_LARGE_IN : in std_logic_vector((4*(TRIGGER_INPUTS_NUMBER+9)-1) downto 0);
HIGH_RATE_THRESHOLD_IN : in std_logic_vector(7 downto 0);
LOW_RATE_THRESHOLD_IN : in std_logic_vector(7 downto 0);
BEAM_STRUCTURE_OUT : out std_logic_vector(1 downto 0);
- TRIGGER_POLARITY : out std_logic_vector(TRIGGER_INPUTS_NUMBER - 1 downto 0);
+ TRIGGER_POLARITY : out std_logic_vector(TRIGGER_INPUTS_NUMBER + 8 - 1 downto 0);
TRIGGER_LOGIC_CTRL_IN_0 : in std_logic_vector(31 downto 0);
TRIGGER_LOGIC_CTRL_IN_1 : in std_logic_vector(31 downto 0);
TRIGGER_LOGIC_CTRL_IN_2 : in std_logic_vector(31 downto 0);
REGIO_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
CTS_NUMBER_IPU_DATA: integer range 0 to 9 :=2;
RW_REGISTERS_NUMBER : integer range 0 to 49 := 38;
- R_REGISTERS_NUMBER : integer range 0 to 105 := 103;
+ R_REGISTERS_NUMBER : integer range 0 to 120 := 103 + 8;
TRIGGER_INPUTS_NUMBER : integer range 0 to 64 := 36;
TRIGGER_OUTPUTS_NUMBER : integer range 0 to 64 := 19;
- SCALERS_NUMBER : integer range 0 to 127 := 95; --36 input scalers,
+ SCALERS_NUMBER : integer range 0 to 127 := 95 + 8; --36 input scalers,
--19 after dsc,
--17 after coincidence,
--19 accepted
+ -- one not used
+ -- 3 special
+ -- 8 from start Y
VECTOR_WIDTH : integer range 1 to 8 := 4;
CTS_MODE : integer range 0 to 1 :=1;
signal timer_ticks : std_logic_vector (1 downto 0);
--trigger logic
- signal input_enable_in_i : std_logic_vector(TRIGGER_INPUTS_NUMBER-1 downto 0);
+ signal input_enable_in_i : std_logic_vector(TRIGGER_INPUTS_NUMBER + 8 -1 downto 0);
signal downscale_register_in_i : std_logic_vector((4*(TRIGGER_INPUTS_NUMBER)-1) downto 0);
- signal delay_trigger_register_in_i : std_logic_vector((4*(TRIGGER_INPUTS_NUMBER)-1) downto 0);
+ signal delay_trigger_register_in_i : std_logic_vector((4*(TRIGGER_INPUTS_NUMBER + 8)-1) downto 0);
signal delay_large_trigger_register_in_i : std_logic_vector((8*(12)-1) downto 0);
signal width_register_in_i : std_logic_vector((4*(TRIGGER_INPUTS_NUMBER+9)-1) downto 0);
signal width_register_large_in_i : std_logic_vector((4*(TRIGGER_INPUTS_NUMBER+9)-1) downto 0);
signal token_out_i : std_logic;
signal save_scalers_out_i : std_logic;
signal saved_scalers_in_i : std_logic_vector(SCALERS_NUMBER*32 -1 downto 0);
- signal trigger_in : std_logic_vector(TRIGGER_INPUTS_NUMBER*4-1 downto 0);
+ signal trigger_in : std_logic_vector((TRIGGER_INPUTS_NUMBER+8)*4-1 downto 0);
signal send_scalers_i : std_logic;
--trigger_buffer
signal read_structure_in_buf, read_structure_finished_out_buf, read_structure_start_in_buf : std_logic_vector(0 downto 0);
signal beam_inhibit_buf : std_logic;
--polarity
- signal trigger_polarity_buf : std_logic_vector(TRIGGER_INPUTS_NUMBER - 1 downto 0);
+ signal trigger_polarity_buf : std_logic_vector(TRIGGER_INPUTS_NUMBER + 8 - 1 downto 0);
--rw register from fpga2
signal down_rw_register_out_buf : std_logic_vector(31 downto 0);
input_enable_in_i(31 downto 0) <= rw_register_i(3);
ts_gating_disable_in_i(31 downto 0) <= rw_register_i(5);
trigger_out_en_in_i(31 downto 0) <= rw_register_i(7);
- input_enable_in_i(TRIGGER_INPUTS_NUMBER-1 downto 32) <= rw_register_i(4)(TRIGGER_INPUTS_NUMBER-32-1 downto 0);
+ input_enable_in_i(TRIGGER_INPUTS_NUMBER + 8 -1 downto 32) <= rw_register_i(4)(TRIGGER_INPUTS_NUMBER-32-1 + 8 downto 0);
ts_gating_disable_in_i(TRIGGER_INPUTS_NUMBER-1 downto 32) <= rw_register_i(6)(TRIGGER_INPUTS_NUMBER-32-1 downto 0);
trigger_out_en_in_i(TRIGGER_INPUTS_NUMBER-1 downto 32) <= rw_register_i(8)(TRIGGER_INPUTS_NUMBER-32-1 downto 0);
end generate INPUT_ENABLE_B;
delay_trigger_register_in_i((i+1)*4-1 downto i*4) <= rw_register_i((i/8)+17)(((i mod 8)+1)*4-1 downto (i mod 8)*4);
end generate DOWNSCALE_DELAY_REGISTERS_INPUT_GENERATE;
+
+ DELAY_START_Y_REGISTERS: for i in 0 to 7 generate
+ delay_trigger_register_in_i((i+36+1)*4-1 downto (i+36)*4) <= rw_register_i((i/8)+22)(((i mod 8)+1)*4-1 downto (i mod 8)*4);
+ end generate DELAY_START_Y_REGISTERS;
+
delay_large_trigger_register_in_i <= rw_register_i(29) & rw_register_i(28) & rw_register_i(27);
WIDTH_REGISTERS_INPUT_GENERATE: for i in 0 to TRIGGER_INPUTS_NUMBER -1 + 9 generate
START_VETO_STRUCTURE_OUT => start_veto_beam_structure_buf,
HIST_DISABLE_IN(31 downto 0) => rw_register_i(23),
HIST_DISABLE_IN(39 downto 32) => rw_register_i(24)(7 downto 0),
- TRIG_CNTRL_IN => rw_register_i(26)(7 downto 0),
+ TRIG_CNTRL_IN => rw_register_i(26)(9 downto 0),
TRIG_STAT_OUT => r_register_i(2)(31 downto 24)
);
);
r_register_i(3) <= trigger_polarity_buf(31 downto 0);
- r_register_i(2)((TRIGGER_INPUTS_NUMBER - 32 - 1 + 5) downto 5) <= trigger_polarity_buf(TRIGGER_INPUTS_NUMBER - 1 downto 32);
+ r_register_i(2)((TRIGGER_INPUTS_NUMBER - 32 - 1 + 5 + 8) downto 5) <= trigger_polarity_buf(TRIGGER_INPUTS_NUMBER - 1 + 8 downto 32);
THE_CTS_FPGA1_TO_FPGA2: cts_fpga1_to_fpga2
end generate REWRITE_RW_REGISTER;
LED_GREEN <= '0';
- LED_ORANGE <= '0';
+ LED_ORANGE <= '1';
LED_RED <= '1';
LED_YELLOW <= '0';
PROGRAMN_OUT <= '1';
CLK_100 : in std_logic;
RESET : in std_logic;
EMERGENCY_STOP : in std_logic;
- TRIGGER_IN : in std_logic_vector(TRIGGER_INPUTS_NUMBER*4-1 downto 0);
- INPUT_ENABLE_IN : in std_logic_vector(TRIGGER_INPUTS_NUMBER-1 downto 0);
+ TRIGGER_IN : in std_logic_vector((TRIGGER_INPUTS_NUMBER+8)*4-1 downto 0);
+ INPUT_ENABLE_IN : in std_logic_vector(TRIGGER_INPUTS_NUMBER + 8 - 1 downto 0);
DOWNSCALE_REGISTER_IN : in std_logic_vector((4*(TRIGGER_INPUTS_NUMBER)-1) downto 0);
- DELAY_TRIGGER_REGISTER_IN : in std_logic_vector((4*(TRIGGER_INPUTS_NUMBER)-1) downto 0);
+ DELAY_TRIGGER_REGISTER_IN : in std_logic_vector((4*(TRIGGER_INPUTS_NUMBER + 8)-1) downto 0);
DELAY_LARGE_TRIGGER_REGISTER_IN : in std_logic_vector((8*(12)-1) downto 0);
WIDTH_REGISTER_IN : in std_logic_vector((4*(TRIGGER_INPUTS_NUMBER+9)-1) downto 0);
WIDTH_REGISTER_LARGE_IN : in std_logic_vector((4*(TRIGGER_INPUTS_NUMBER+9)-1) downto 0);
LOW_RATE_THRESHOLD_IN : in std_logic_vector(7 downto 0);
BEAM_STRUCTURE_OUT : out std_logic_vector(1 downto 0);
--debug & cntrl
- TRIGGER_POLARITY : out std_logic_vector(TRIGGER_INPUTS_NUMBER - 1 downto 0);
+ TRIGGER_POLARITY : out std_logic_vector(TRIGGER_INPUTS_NUMBER + 8 - 1 downto 0);
TRIGGER_LOGIC_CTRL_IN_0 : in std_logic_vector(31 downto 0);
TRIGGER_LOGIC_CTRL_IN_1 : in std_logic_vector(31 downto 0);
TRIGGER_LOGIC_CTRL_IN_2 : in std_logic_vector(31 downto 0);
signal CLK_800MHz : std_logic;
signal CLK_400MHz : std_logic;
- type trigger_array_type is array (0 to TRIGGER_INPUTS_NUMBER - 1) of std_logic_vector(VECTOR_WIDTH -1 downto 0);
+ type trigger_array_type is array (0 to (TRIGGER_INPUTS_NUMBER + 8 - 1)) of std_logic_vector(VECTOR_WIDTH -1 downto 0);
signal input_trigger_array,input_trigger_array_sync, input_trigger_array_sync_b : trigger_array_type;
signal pti_one_clock_in_array,pti_one_clock_out_array,pti_delayed_in_array,pti_delayed_out_array,pti_delayed_large_in_array,pti_delayed_large_out_array,pti_downscaled_in_array,pti_downscaled_out_array,pti_set_width_in_array,pti_set_width_large_in_array,pti_set_width_out_array,pti_set_width_small_out_array,pti_set_width_small_in_array,pti_set_width_large_out_array,one_clock_special_in,pti_and_gts_in_array,pti_and_gts_out_array : trigger_array_type;
signal update_out : std_logic_vector(TRIGGER_INPUTS_NUMBER - 1 downto 0);
signal scaler_in_for_fast_cts,downscale_in_for_fast_cts : std_logic_vector(SCALERS_NUMBER*2 - 1 downto 0);
-
+ signal scaler_in_for_starty_cts : std_logic_vector(7 downto 0);
+
signal multiplicity_in_array : std_logic_vector(5 downto 0);
signal tof_rpc_or, tof_rpc_sync, tof_rpc_fast, start_veto_anticoincidence_array,final_trigger_array,multiplicity_out_array : std_logic_vector(VECTOR_WIDTH - 1 downto 0);
signal multiplicity_out_array_delayed : std_logic_vector(VECTOR_WIDTH - 1 downto 0);
--large delay signals
-
+ signal start_large_delay_y_in, start_large_delay_y_out : std_logic_vector(31 downto 0);
signal start_veto_large_delay_in, start_veto_large_delay_out : std_logic_vector(63 downto 0);
signal tof_large_delay_in, tof_large_delay_out, rpc_large_delay_in, rpc_large_delay_out : std_logic_vector(23 downto 0);
signal tof56_large_delay_in, tof56_large_delay_out, rpc56_large_delay_in, rpc56_large_delay_out : std_logic_vector(15 downto 0);
signal start_signals_beam_straucture : std_logic_vector(7 downto 0);
signal individual_hist_signal_a, individual_hist_signal_b : std_logic;
--signal for polarity check
- signal input_polarity_sinal, output_polarity_signal : std_logic_vector(TRIGGER_INPUTS_NUMBER - 1 downto 0);
+ signal input_polarity_sinal, output_polarity_signal : std_logic_vector(TRIGGER_INPUTS_NUMBER + 8 - 1 downto 0);
--special scalers
signal trigg_relative_time, trigg_relative_time_saved : std_logic_vector(31 downto 0);
signal trigg_last_time, trigg_last_time_saved : std_logic_vector(31 downto 0);
-- 52:45 MDC not used curently
-- 53 TOF & MDC - not used currently
- REWRITE_INPUT_VECTOR_TO_ARRAY: for i in 0 to TRIGGER_INPUTS_NUMBER-1 generate
+ REWRITE_INPUT_VECTOR_TO_ARRAY: for i in 0 to TRIGGER_INPUTS_NUMBER + 8 - 1 generate
input_trigger_array(i) <= TRIGGER_IN((i+1)*4-1 downto i*4);
end generate REWRITE_INPUT_VECTOR_TO_ARRAY;
input_trigger_array_sync(33) <= input_trigger_array(33);
input_trigger_array_sync(34) <= input_trigger_array(34);
input_trigger_array_sync(35) <= input_trigger_array(35);
+
+ input_trigger_array_sync(36) <= not input_trigger_array(36);
+ input_trigger_array_sync(37) <= not input_trigger_array(37);
+ input_trigger_array_sync(38) <= not input_trigger_array(38);
+ input_trigger_array_sync(39) <= not input_trigger_array(39);
+ input_trigger_array_sync(40) <= not input_trigger_array(40);
+ input_trigger_array_sync(41) <= not input_trigger_array(41);
+ input_trigger_array_sync(42) <= not input_trigger_array(42);
+ input_trigger_array_sync(43) <= not input_trigger_array(43);
+
+
input_trigger_array_sync_b <= input_trigger_array_sync;
end if;
end process MAKE_CORRECT_POLARIZATION;
--check polarity
- SET_POLARITY: for i in 0 to TRIGGER_INPUTS_NUMBER - 1 generate
+ SET_POLARITY: for i in 0 to TRIGGER_INPUTS_NUMBER + 8 - 1 generate
INDIVIDUAL_SIGNALS_FOR_POLARITY : process (CLK, RESET)
begin
if rising_edge(CLK) then
THE_CTS_POLARITY_CHECK: cts_polarity_check
generic map (
- NUMBER_OF_SIGNALS => TRIGGER_INPUTS_NUMBER)
+ NUMBER_OF_SIGNALS => TRIGGER_INPUTS_NUMBER+8)
port map (
RESET => RESET,
CLK => CLK,
-------------------------------------------------------------------------------
-- ONE CLK LONG
-------------------------------------------------------------------------------
- ONE_CLK_CONNECTION: for i in 0 to TRIGGER_INPUTS_NUMBER - 1 generate
+ ONE_CLK_CONNECTION: for i in 0 to TRIGGER_INPUTS_NUMBER + 8 - 1 generate
THE_CTS_ONE_CLOCK: cts_one_clock
generic map (
VECTOR_WIDTH => VECTOR_WIDTH
pti_delayed_large_in_array <= pti_one_clock_out_array;
+
+ --START Y
+
+ START_Y_REWRITE: for i in 36 to 43 generate
+ start_large_delay_y_in((i-36+1)*4-1 downto (i-36)*4) <= pti_delayed_large_in_array(i);
+ pti_delayed_large_out_array(i) <= start_large_delay_y_out((i-36+1)*4-1 downto (i-36)*4);
+ end generate START_Y_REWRITE;
+
+ THE_CTS_DELAY_LARGE_START_Y : cts_delay_large
+ generic map (
+ VECTOR_WIDTH => 32)
+ port map (
+ RESET => RESET,
+ CLK => CLK,
+ DELAY_IN => DELAY_LARGE_TRIGGER_REGISTER_IN(7 downto 0),
+ DELAY_VECTOR_IN => start_large_delay_y_in,
+ DELAY_VECTOR_OUT => start_large_delay_y_out);
+
-- --start veto
+
START_VETO_LARGE_DELAY_IN_OUT: for i in 0 to 15 generate
start_veto_large_delay_in((i+1)*4-1 downto i*4) <= pti_delayed_large_in_array(i);
pti_delayed_in_array <= pti_delayed_large_out_array;
-- pti_delayed_in_array <= pti_one_clock_out_array;
- DELAY_CONNECTION: for i in 0 to TRIGGER_INPUTS_NUMBER - 1 generate
+ DELAY_CONNECTION: for i in 0 to TRIGGER_INPUTS_NUMBER + 8 - 1 generate
THE_CTS_DELAY : cts_delay
generic map (
DOWN_IN => '0');
end generate SCALER_A_CONNECTION;
+ SCALER_STARTY_CONNECTION: for i in 0 to 7 generate
+ LONG_SIGNAL_FOR_SCALERS : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ scaler_in_for_starty_cts(i) <= '0';
+ elsif pti_delayed_out_array(i+36) > 0 then
+ scaler_in_for_starty_cts(i) <= '1';
+ else
+ scaler_in_for_starty_cts(i) <= '0';
+ end if;
+ end if;
+ end process LONG_SIGNAL_FOR_SCALERS;
+
+ STARTY_CTS_SCALER_COUNTER: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 32)
+ port map (
+ CLK => CLK,
+ RESET => reset_scalers_sync,
+ COUNT_OUT => scalers(TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER-2+4+i), --3special scalers - one not used
+ UP_IN => scaler_in_for_starty_cts(i),
+ DOWN_IN => '0');
+ end generate SCALER_STARTY_CONNECTION;
+
-- THE_CTS_CHECK_DETECTOR_RATES: cts_check_detector_rates
-- generic map (
CLOCK_SIGNALS_FOR_ONE_CLOCK_SPECIAL : process (CLK, RESET)
begin
if rising_edge(CLK) then
- one_clock_special_in(0) <= pti_delayed_out_array(7) or pti_delayed_out_array(6) or pti_delayed_out_array(5) or pti_delayed_out_array(4) or pti_delayed_out_array(3) or pti_delayed_out_array(2) or pti_delayed_out_array(1) or pti_delayed_out_array(0); --START
+ one_clock_special_in(0) <= pti_delayed_out_array(7) or pti_delayed_out_array(6) or pti_delayed_out_array(5) or pti_delayed_out_array(4) or pti_delayed_out_array(3) or pti_delayed_out_array(2) or pti_delayed_out_array(1) or pti_delayed_out_array(0) or
+ pti_delayed_out_array(36) or pti_delayed_out_array(37) or pti_delayed_out_array(38) or pti_delayed_out_array(39) or pti_delayed_out_array(40) or pti_delayed_out_array(41) or pti_delayed_out_array(42) or pti_delayed_out_array(43)
+ ; --START
+
one_clock_special_in(1) <= pti_delayed_out_array(15) or pti_delayed_out_array(14) or pti_delayed_out_array(13) or pti_delayed_out_array(12) or pti_delayed_out_array(11) or pti_delayed_out_array(10) or pti_delayed_out_array(9) or pti_delayed_out_array(8);--VETO
end if;
end process CLOCK_SIGNALS_FOR_ONE_CLOCK_SPECIAL;
CLK : in std_logic;
EDGE_CLK : in std_logic;
TRIG_IN : in std_logic_vector(63 downto 0);
- TRIG_OUT : out std_logic_vector(TRIGGER_INPUTS_NUMBER*4-1 downto 0);
+ TRIG_OUT : out std_logic_vector((TRIGGER_INPUTS_NUMBER+8)*4-1 downto 0);
FAST_LVDS_TIMING_IN : in std_logic_vector(3 downto 0);
FAST_PECL_TIMING_IN : in std_logic_vector(3 downto 0);
FAST_MDCA_TIMING_IN : in std_logic_vector(3 downto 0);
PECL_TIMING_OUT : out std_logic_vector(2 downto 0);
START_VETO_STRUCTURE_OUT : out std_logic_vector(23 downto 0);
HIST_DISABLE_IN : in std_logic_vector(39 downto 0);
- TRIG_CNTRL_IN : in std_logic_vector(7 downto 0);
+ TRIG_CNTRL_IN : in std_logic_vector(9 downto 0);
TRIG_STAT_OUT : out std_logic_vector(7 downto 0)
);
end ddr2_busses;
end case;
end if;
end process SELECT_START_SIGNALS_FOR_TRIGGER;
+
+
+ SELECT_START_SIGNALS_FOR_TRIGGER_Y : process (CLK, RESET) --connector 1 and 2
+ begin
+ if rising_edge(CLK) then
+ case TRIG_CNTRL_IN(9 downto 8) is
+ when b"00" =>
+ TRIG_OUT(44*4-1 downto 36*4) <= output_from_fifo_sunch_a((13+16)*4-1 downto (12+16)*4) &
+ output_from_fifo_sunch_a((4+16)*4-1 downto (3+16)*4) &
+ output_from_fifo_sunch_a((14+16)*4-1 downto (13+16)*4) &
+ output_from_fifo_sunch_a((3+16)*4-1 downto (2+16)*4) &
+ output_from_fifo_sunch_a((15+16)*4-1 downto (14+16)*4) &
+ output_from_fifo_sunch_a((2+16)*4-1 downto (1+16)*4) &
+ output_from_fifo_sunch_a((16+16)*4-1 downto (15+16)*4) &
+ output_from_fifo_sunch_a((1+16)*4-1 downto 16*4);
+ when b"01" =>
+ TRIG_OUT(44*4-1 downto 36*4) <= output_from_fifo_sunch_a((11+16)*4-1 downto (10+16)*4) &
+ output_from_fifo_sunch_a((6+16)*4-1 downto (5+16)*4) &
+ output_from_fifo_sunch_a((12+16)*4-1 downto (11+16)*4) &
+ output_from_fifo_sunch_a((5+16)*4-1 downto (4+16)*4) &
+ output_from_fifo_sunch_a((13+16)*4-1 downto (12+16)*4) &
+ output_from_fifo_sunch_a((4+16)*4-1 downto (3+16)*4) &
+ output_from_fifo_sunch_a((14+16)*4-1 downto (13+16)*4) &
+ output_from_fifo_sunch_a((3+16)*4-1 downto (2+16)*4);
+ when b"10" =>
+ TRIG_OUT(44*4-1 downto 36*4) <= output_from_fifo_sunch_a((9+16)*4-1 downto (8+16)*4) &
+ output_from_fifo_sunch_a((8+16)*4-1 downto (7+16)*4) &
+ output_from_fifo_sunch_a((10+16)*4-1 downto (9+16)*4) &
+ output_from_fifo_sunch_a((7+16)*4-1 downto (6+16)*4) &
+ output_from_fifo_sunch_a((11+16)*4-1 downto (10+16)*4) &
+ output_from_fifo_sunch_a((6+16)*4-1 downto (5+16)*4) &
+ output_from_fifo_sunch_a((12+16)*4-1 downto (11+16)*4) &
+ output_from_fifo_sunch_a((5+16)*4-1 downto (4+16)*4);
+ when others =>
+ TRIG_OUT(44*4-1 downto 36*4) <= output_from_fifo_sunch_a((13+16)*4-1 downto (12+16)*4) &
+ output_from_fifo_sunch_a((4+16)*4-1 downto (3+16)*4) &
+ output_from_fifo_sunch_a((14+16)*4-1 downto (13+16)*4) &
+ output_from_fifo_sunch_a((3+16)*4-1 downto (2+16)*4) &
+ output_from_fifo_sunch_a((15+16)*4-1 downto (14+16)*4) &
+ output_from_fifo_sunch_a((2+16)*4-1 downto (1+16)*4) &
+ output_from_fifo_sunch_a((16+16)*4-1 downto (15+16)*4) &
+ output_from_fifo_sunch_a((1+16)*4-1 downto 16*4);
+ end case;
+ end if;
+ end process SELECT_START_SIGNALS_FOR_TRIGGER_Y;
+
+
--first 32 inputs are used for the START - first 16 for trggering and
--histograming next 16 for histograming only
package version is
- constant VERSION_NUMBER_TIME : integer := 1333366798;
+ constant VERSION_NUMBER_TIME : integer := 1334087142;
end package version;
jspc29 / ctsaddon.git / commitdiff