STAT_FIFO_TO_INT(11) <= fifo_to_int_read;
STAT_FIFO_TO_INT(14) <= fifo_to_int_full;
STAT_FIFO_TO_INT(15) <= fifo_to_int_empty;
+ STAT_FIFO_TO_INT(16) <= next_APL_DATAREADY_OUT;
+ STAT_FIFO_TO_INT(17) <= sbuf_to_apl_free;
+ STAT_FIFO_TO_INT(18) <= fifo_to_apl_read_before;
+ STAT_FIFO_TO_INT(19) <= fifo_to_apl_read;
+ STAT_FIFO_TO_INT(20) <= fifo_to_apl_empty;
+ STAT_FIFO_TO_INT(21) <= fifo_to_apl_write;
STAT_FIFO_TO_INT(7 downto 4) <= (others => '0');
STAT_FIFO_TO_INT(13 downto 12) <= (others => '0');
- STAT_FIFO_TO_INT(25 downto 16) <= (others => '0');
+ STAT_FIFO_TO_INT(25 downto 22) <= (others => '0');
STAT_FIFO_TO_INT(28 downto 26) <= state_bits_to_int;
STAT_FIFO_TO_INT(31 downto 29) <= state_bits_to_apl;
---------------------------------------
end if;
when sa_MY_ADDR =>
if APL_WRITE_4_PACKETS = 0 then
- next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and (or_all(fifo_to_apl_packet_num_out));
+ next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and (or_all(fifo_to_apl_packet_num_out)) and sbuf_to_apl_free;
throw_away <= not or_all(fifo_to_apl_packet_num_out);
else
- next_APL_DATAREADY_OUT <= fifo_to_apl_read_before;
+ next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and sbuf_to_apl_free;
end if;
fifo_to_apl_read <= not fifo_to_apl_empty and not (fifo_to_apl_read_before and not sbuf_to_apl_free and not throw_away);
if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT = "11" and sbuf_to_apl_free = '1' then
API_SEQNR_IN : in std_logic_vector (7 downto 0);
MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
+ --Port to write Unique ID
+ IDRAM_DATA_IN : in std_logic_vector(15 downto 0);
+ IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);
+ IDRAM_ADDR_IN : in std_logic_vector(2 downto 0);
+ IDRAM_WR_IN : in std_logic;
+
--Register in / out
REGISTERS_IN : in std_logic_vector(REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);
MY_ADDRESS_OUT => HUB_ADDRESS,
REGISTERS_IN => HC_STAT_REGS,
REGISTERS_OUT => HC_CTRL_REGS,
+ --Port to write Unique ID
+ IDRAM_DATA_IN => (others => '0'),
+ IDRAM_DATA_OUT => open,
+ IDRAM_ADDR_IN => (others => '0'),
+ IDRAM_WR_IN => '0',
DAT_ADDR_OUT => open,
DAT_READ_ENABLE_OUT => open,
DAT_WRITE_ENABLE_OUT=> open,
signal comb_INIT_next_read : std_logic;
signal reply_fsm_state : std_logic;
+ signal waiting_for_init_finish, next_waiting_for_init_finish : std_logic;
+
begin
REPLY_HEADER_OUT <= (others => '0');
reply_state_machine : process(REPLY_POOL_next_READ, current_state, packet_counter,
send_reply_trm, SEQ_NR, REPLY_combined_trm_F1, REPLY_combined_trm_F2,
comb_REPLY_muxed_DATAREADY, comb_REPLY_muxed_DATA,
- comb_REPLY_muxed_PACKET_NUM)
+ comb_REPLY_muxed_PACKET_NUM, waiting_for_init_finish)
begin
release_locked <= '0';
next_state <= current_state;
comb_REPLY_POOL_DATAREADY <= '0';
comb_REPLY_POOL_PACKET_NUM <= packet_counter;
comb_REPLY_POOL_DATA <= (others => '0');
-
+ next_waiting_for_init_finish <= waiting_for_init_finish;
if current_state = SENDING_DATA then
comb_REPLY_POOL_DATAREADY <= comb_REPLY_muxed_DATAREADY;
end if;
if current_state = SENDING_REPLY_TRM then
- comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read;
+ comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read and not waiting_for_init_finish;
+ if waiting_for_init_finish = '1' and init_locked = '1' then
+ release_locked <= '1'; --release only when init has finished too
+ next_state <= SENDING_DATA;
+ next_waiting_for_init_finish <= '0';
+ end if;
case packet_counter is
when "01" =>
comb_REPLY_POOL_DATA <= REPLY_combined_trm_F1;
comb_REPLY_POOL_DATA <= REPLY_combined_trm_F2;
when "11" =>
comb_REPLY_POOL_DATA <= "0000" & SEQ_NR & "0000";
- if REPLY_POOL_next_read = '1' then
- release_locked <= '1';
+ if REPLY_POOL_next_read = '1' and (init_locked = '1') then
+ release_locked <= '1'; --release only when init has finished too
next_state <= SENDING_DATA;
+ elsif init_locked = '0' then
+ next_waiting_for_init_finish <= '1';
end if;
when others =>
comb_REPLY_POOL_DATA <= (others => '0');
if RESET = '1' then
current_state <= SENDING_DATA;
REPLY_POOL_next_read <= '0';
+ waiting_for_init_finish <= '0';
else
current_state <= next_state;
REPLY_POOL_next_read <= comb_REPLY_POOL_next_read;
+ waiting_for_init_finish <= next_waiting_for_init_finish;
end if;
end if;
end process;
--REGISTERS with highest bit set are writeable (CTRL), with highest bit unset are readonly (STAT) from outside and vice versa from inside
--the highest address bit is not used to determine the data position inside REGISTER IN/OUT
--REGISTER_IN is not registered again
---if DAT-Port is not used, set DAT_DATAREADY_IN to '1'
API_RUN_IN : in std_logic;
API_SEQNR_IN : in std_logic_vector (7 downto 0);
+ --Port to write Unique ID
+ IDRAM_DATA_IN : in std_logic_vector(15 downto 0);
+ IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);
+ IDRAM_ADDR_IN : in std_logic_vector(2 downto 0);
+ IDRAM_WR_IN : in std_logic;
+
+
MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
- --Register in / out
+ --Common Register in / out
+-- COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0);
+-- COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+
+ --Custom Register in / out
REGISTERS_IN : in std_logic_vector(REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);
REGISTERS_OUT : out std_logic_vector(REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);
--if successful
DAT_DATA_IN : in std_logic_vector(REGISTER_WIDTH-1 downto 0);
DAT_DATAREADY_IN : in std_logic;
- DAT_NO_MORE_DATA_IN : in std_logic
+ DAT_NO_MORE_DATA_IN : in std_logic;
--To finish transmission, when reading from a fifo and it got empty
+ STAT : out std_logic_vector(31 downto 0)
);
end entity;
if API_PACKET_NUM_IN = "11" then
next_HDR_F3 <= API_DATA_IN;
case API_DATA_IN(3 downto 0) is
- when "1000" => next_state <= ONE_READ;
- when "1001" => next_state <= ONE_WRITE;
- when "1010" => next_state <= MEM_READ;
- when "1011" => next_state <= MEM_WRITE;
- when "1111" => next_state <= ADDRESS_RECV;
+ when c_read_register_type => next_state <= ONE_READ;
+ when c_write_register_type => next_state <= ONE_WRITE;
+ when c_read_multiple_type => next_state <= MEM_READ;
+ when c_write_multiple_type => next_state <= MEM_WRITE;
+ when c_network_control_type => next_state <= ADDRESS_RECV;
when others => next_state <= SEND_REPLY_SHORT_TRANSFER;
end case;
next_operation <= API_DATA_IN(3 downto 0);
DAT_ADDR_OUT <= buf_DAT_ADDR_OUT;
REGISTERS_OUT <= buf_REGISTERS_OUT;
-
+ STAT(0) <= ADR_REJECTED;
+ STAT(1) <= ADR_READ_IN;
+ STAT(2) <= ADR_DATAREADY_OUT;
+ STAT(3) <= ADR_DATAREADY_IN;
+ STAT(31 downto 4) <= (others => '0');
process(current_state)
begin
jspc29 / trbnet.git / commitdiff