trb3_gbe

diff --git a/trb3_gbe_test/trb3_central/serdes.ptx b/trb3_gbe_test/trb3_central/serdes.ptx
new file mode 100644 (file)
index 0000000..19450c3
--- /dev/null
+++ b/trb3_gbe_test/trb3_central/serdes.ptx
@@ -0,0 +1,223 @@
+       ch0_protocol    "GIGE"
+       xge_mode        "0"
+       ch0_rio_mode     "0"
+      ch0_pcie_mode    "0" 
+       ch0_fc_mode     "0"
+       ch0_uc_mode     "0"
+       ch0_pci_det_time_sel "00"
+       ch0_ge_an_en    "1"
+       ch1_protocol    "GIGE"
+       xge_mode        "0"
+       ch1_rio_mode     "0"
+      ch1_pcie_mode    "0" 
+       ch1_fc_mode     "0"
+       ch1_uc_mode     "0"
+       ch1_pci_det_time_sel "00"
+       ch1_ge_an_en    "1"
+       ch0_tpwdnb       "1"
+      ch0_rpwdnb       "1" 
+       ch1_tpwdnb       "1"
+      ch1_rpwdnb       "1" 
+       ch2_tpwdnb       "0"
+      ch2_rpwdnb       "0" 
+       ch3_tpwdnb       "0"
+      ch3_rpwdnb       "0" 
+       tx_datarate_range        "MED"
+       tx_vco_ck_div    "010"
+       ch0_rx_datarate_range    "MED"
+       ch0_rx_dco_ck_div        "010"
+       ch1_rx_datarate_range    "MED"
+       ch1_rx_dco_ck_div        "010"
+       refck25x         "0"
+      refck_mode       "01"
+       ch0_rate_mode_rx         "0"
+       ch0_div11_rx     "0"
+       ch1_rate_mode_rx         "0"
+       ch1_div11_rx     "0"
+       ch0_rate_mode_tx         "0"
+       ch0_div11_tx     "0"
+       ch1_rate_mode_tx         "0"
+       ch1_div11_tx     "0"
+       ch0_ff_tx_f_clk_dis      "0"
+       ch0_ff_tx_h_clk_en       "1"
+       ch0_tx_gear_mode         "0"
+       ch1_ff_tx_f_clk_dis      "0"
+       ch1_ff_tx_h_clk_en       "1"
+       ch1_tx_gear_mode         "0"
+       ch0_ff_rx_f_clk_dis      "0"
+       ch0_ff_rx_h_clk_en       "1"
+       ch0_rx_gear_mode         "0"
+       ch1_ff_rx_f_clk_dis      "0"
+       ch1_ff_rx_h_clk_en       "1"
+       ch1_rx_gear_mode         "0"
+       ch0_tx_gear_bypass       "0"
+       ch1_tx_gear_bypass       "0"
+       ch0_rx_gear_bypass       "0"
+       ch1_rx_gear_bypass       "0"
+       ch0_tdrv_amp     "000"
+    ch0_tdrv_drvcur_set  "100"
+    ch0_tdrv_amp_boost "0"
+       ch1_tdrv_amp     "000"
+    ch1_tdrv_drvcur_set  "100"
+    ch1_tdrv_amp_boost "0"
+       ch0_tdrv_pre_en  "0"
+       ch0_tdrv_pre_set        "00000"
+       ch1_tdrv_pre_en  "0"
+       ch1_tdrv_pre_set        "00000"
+       ch0_rterm_tx    "10"
+       ch1_rterm_tx    "10"
+       ch0_req_en      "0"
+       ch0_req_lvl_set "0"
+       ch0_rate_sel    "00"
+       ch1_req_en      "0"
+       ch1_req_lvl_set "0"
+       ch1_rate_sel    "00"
+       ch0_rterm_rx    "01"
+       ch1_rterm_rx    "01"
+       ch0_rcv_dcc_en  "0"
+       ch1_rcv_dcc_en  "0"
+       ch0_rlos_lset   "010"
+       ch1_rlos_lset   "010"
+       rlos_hisel      "0"
+       refck_rterm      "1"
+       refck_dcc_en     "0"
+       pll_lol_set      "00"
+       ch0_invert_tx   "0"
+       ch0_tx_sb_bypass        "0"
+       ch1_invert_tx   "0"
+       ch1_tx_sb_bypass        "0"
+       ch0_invert_rx   "0"
+       ch0_rx_sb_bypass        "0"
+       ch1_invert_rx   "0"
+       ch1_rx_sb_bypass        "0"
+       ch0_enc_bypass  "0"
+       ch1_enc_bypass  "0"
+       ch0_dec_bypass  "0"
+       ch1_dec_bypass  "0"
+       ch0_udf_comma_a "1010000011"
+       ch1_udf_comma_a "1010000011"
+       ch0_udf_comma_b "0101111100"
+       ch1_udf_comma_b "0101111100"
+       ch0_udf_comma_mask      "1111111111"
+       ch1_udf_comma_mask      "1111111111"
+       ch0_wa_bypass   "0"
+       ch1_wa_bypass   "0"
+       ch0_lsm_disable "0"
+       ch1_lsm_disable "0"
+       ch0_sel_sd_rx_clk       "1"
+       ch0_ctc_bypass  "1"
+       ch1_sel_sd_rx_clk       "1"
+       ch1_ctc_bypass  "1"
+       ch0_ch_match_3  "0110111100"
+       ch1_ch_match_3  "0110111100"
+       ch0_ch_match_4  "0001010000"
+       ch1_ch_match_4  "0001010000"
+       ch0_match_2_enable      "1"
+       ch0_match_4_enable      "0"
+       ch1_match_2_enable      "1"
+       ch1_match_4_enable      "0"
+       ch0_min_jpg_cnt "11"
+       ch1_min_jpg_cnt "11"
+       high_mark       "1001"
+       low_mark        "0111"
+       ch0_lb_ctl      "0000"
+       ch0_tdrv_dat_sel "00"
+       ch1_lb_ctl      "0000"
+       ch1_tdrv_dat_sel "00"
+       ch0_sb_pfifo_lp "0"
+       ch0_sb_loopback "0"
+       ch1_sb_pfifo_lp "0"
+       ch1_sb_loopback "0"
+       pfifo_clr_sel   "0"
+       ch0_fb_loopback "0"
+       ch1_fb_loopback "0"
+       refck_out_sel_1 "0"
+       plol_int_ctl    "0"
+       not_plol_int_ctl        "0"
+       ch0_pci_det_done_int_ctl        "0"
+       ch0_rlos_lo_int_ctl     "0"
+       ch0_i_rlos_lo_int_ctl   "0"
+       ch0_rlos_hi_int_ctl     "0"
+       ch0_i_rlos_hi_int_ctl   "0"
+       ch0_rlol_int_ctl        "0"
+       ch0_i_rlol_int_ctl      "0"
+       ls_sync_status_3_int_ctl        "0"
+       ls_sync_status_2_int_ctl        "0"
+       ls_sync_status_1_int_ctl        "0"
+       ls_sync_status_0_int_ctl        "0"
+       ls_sync_statusn_3_int_ctl       "0"
+       ls_sync_statusn_2_int_ctl       "0"
+       ls_sync_statusn_1_int_ctl       "0"
+       ls_sync_statusn_0_int_ctl       "0"
+       ch0_fb_tx_fifo_error_int_ctl    "0"
+       ch0_fb_rx_fifo_error_int_ctl    "0"
+       ch0_cc_overrun_int_ctl  "0"
+       ch0_cc_underrun_int_ctl "0"
+       plol_int_ctl    "0"
+       not_plol_int_ctl        "0"
+       ch1_pci_det_done_int_ctl        "0"
+       ch1_rlos_lo_int_ctl     "0"
+       ch1_i_rlos_lo_int_ctl   "0"
+       ch1_rlos_hi_int_ctl     "0"
+       ch1_i_rlos_hi_int_ctl   "0"
+       ch1_rlol_int_ctl        "0"
+       ch1_i_rlol_int_ctl      "0"
+       ls_sync_status_3_int_ctl        "0"
+       ls_sync_status_2_int_ctl        "0"
+       ls_sync_status_1_int_ctl        "0"
+       ls_sync_status_0_int_ctl        "0"
+       ls_sync_statusn_3_int_ctl       "0"
+       ls_sync_statusn_2_int_ctl       "0"
+       ls_sync_statusn_1_int_ctl       "0"
+       ls_sync_statusn_0_int_ctl       "0"
+       ch1_fb_tx_fifo_error_int_ctl    "0"
+       ch1_fb_rx_fifo_error_int_ctl    "0"
+       ch1_cc_overrun_int_ctl  "0"
+       ch1_cc_underrun_int_ctl "0"
+       plol_int_ctl    "0"
+       not_plol_int_ctl        "0"
+       ch2_pci_det_done_int_ctl        "0"
+       ch2_rlos_lo_int_ctl     "0"
+       ch2_i_rlos_lo_int_ctl   "0"
+       ch2_rlos_hi_int_ctl     "0"
+       ch2_i_rlos_hi_int_ctl   "0"
+       ch2_rlol_int_ctl        "0"
+       ch2_i_rlol_int_ctl      "0"
+       ls_sync_status_3_int_ctl        "0"
+       ls_sync_status_2_int_ctl        "0"
+       ls_sync_status_1_int_ctl        "0"
+       ls_sync_status_0_int_ctl        "0"
+       ls_sync_statusn_3_int_ctl       "0"
+       ls_sync_statusn_2_int_ctl       "0"
+       ls_sync_statusn_1_int_ctl       "0"
+       ls_sync_statusn_0_int_ctl       "0"
+       ch2_fb_tx_fifo_error_int_ctl    "0"
+       ch2_fb_rx_fifo_error_int_ctl    "0"
+       ch2_cc_overrun_int_ctl  "0"
+       ch2_cc_underrun_int_ctl "0"
+       plol_int_ctl    "0"
+       not_plol_int_ctl        "0"
+       ch3_pci_det_done_int_ctl        "0"
+       ch3_rlos_lo_int_ctl     "0"
+       ch3_i_rlos_lo_int_ctl   "0"
+       ch3_rlos_hi_int_ctl     "0"
+       ch3_i_rlos_hi_int_ctl   "0"
+       ch3_rlol_int_ctl        "0"
+       ch3_i_rlol_int_ctl      "0"
+       ls_sync_status_3_int_ctl        "0"
+       ls_sync_status_2_int_ctl        "0"
+       ls_sync_status_1_int_ctl        "0"
+       ls_sync_status_0_int_ctl        "0"
+       ls_sync_statusn_3_int_ctl       "0"
+       ls_sync_statusn_2_int_ctl       "0"
+       ls_sync_statusn_1_int_ctl       "0"
+       ls_sync_statusn_0_int_ctl       "0"
+       ch3_fb_tx_fifo_error_int_ctl    "0"
+       ch3_fb_rx_fifo_error_int_ctl    "0"
+       ch3_cc_overrun_int_ctl  "0"
+       ch3_cc_underrun_int_ctl "0"
+       bus8bit_sel     "0"
+       ch0_signal_detect       "1"
+       ch1_signal_detect       "1"
+       ch0_en_cg_align "0"
+       ch1_en_cg_align "0"

diff --git a/trb3_gbe_test/trb3_central/serdes.txt b/trb3_gbe_test/trb3_central/serdes.txt
new file mode 100644 (file)
index 0000000..0f479cc
--- /dev/null
+++ b/trb3_gbe_test/trb3_central/serdes.txt
@@ -0,0 +1,95 @@
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSD quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSD quad to the final design requirements.
+
+DEVICE_NAME "LFE3-150EA"
+CH0_PROTOCOL            "GIGE"
+CH1_PROTOCOL            "GIGE"
+CH0_MODE                "RXTX"
+CH1_MODE                "RXTX"
+CH2_MODE                "DISABLED"
+CH3_MODE                "DISABLED"
+CH0_CDR_SRC       "REFCLK_CORE"
+CH1_CDR_SRC       "REFCLK_CORE"
+PLL_SRC                 "REFCLK_CORE"
+TX_DATARATE_RANGE       "MED"
+CH0_RX_DATARATE_RANGE   "MED"
+CH1_RX_DATARATE_RANGE   "MED"
+REFCK_MULT              "10X"
+#REFCLK_RATE            125.0
+CH0_RX_DATA_RATE        "FULL"
+CH1_RX_DATA_RATE        "FULL"
+CH0_TX_DATA_RATE        "FULL"
+CH1_TX_DATA_RATE        "FULL"
+CH0_TX_DATA_WIDTH       "8"
+CH1_TX_DATA_WIDTH       "8"
+CH0_RX_DATA_WIDTH        "8"
+CH1_RX_DATA_WIDTH        "8"
+CH0_TX_FIFO       "ENABLED"
+CH1_TX_FIFO       "ENABLED"
+CH0_RX_FIFO        "ENABLED"
+CH1_RX_FIFO        "ENABLED"
+CH0_TDRV      "0"
+CH1_TDRV      "0"
+#CH0_TX_FICLK_RATE      125.0
+#CH1_TX_FICLK_RATE      125.0
+#CH0_RXREFCLK_RATE        "125.0"
+#CH1_RXREFCLK_RATE        "125.0"
+#CH0_RX_FICLK_RATE      125.0
+#CH1_RX_FICLK_RATE      125.0
+CH0_TX_PRE              "DISABLED"
+CH1_TX_PRE              "DISABLED"
+CH0_RTERM_TX            "50"
+CH1_RTERM_TX            "50"
+CH0_RX_EQ               "DISABLED"
+CH1_RX_EQ               "DISABLED"
+CH0_RTERM_RX            "50"
+CH1_RTERM_RX            "50"
+CH0_RX_DCC              "AC"
+CH1_RX_DCC              "AC"
+CH0_LOS_THRESHOLD_LO       "2"
+CH1_LOS_THRESHOLD_LO       "2"
+PLL_TERM                "50"
+PLL_DCC                 "AC"
+PLL_LOL_SET             "0"
+CH0_TX_SB               "DISABLED"
+CH1_TX_SB               "DISABLED"
+CH0_RX_SB               "DISABLED"
+CH1_RX_SB               "DISABLED"
+CH0_TX_8B10B            "ENABLED"
+CH1_TX_8B10B            "ENABLED"
+CH0_RX_8B10B            "ENABLED"
+CH1_RX_8B10B            "ENABLED"
+CH0_COMMA_A             "1100000101"
+CH1_COMMA_A             "1100000101"
+CH0_COMMA_B             "0011111010"
+CH1_COMMA_B             "0011111010"
+CH0_COMMA_M             "1111111111"
+CH1_COMMA_M             "1111111111"
+CH0_RXWA                "ENABLED"
+CH1_RXWA                "ENABLED"
+CH0_ILSM                "ENABLED"
+CH1_ILSM                "ENABLED"
+CH0_CTC                 "DISABLED"
+CH1_CTC                 "DISABLED"
+CH0_CC_MATCH3           "0110111100"
+CH0_CC_MATCH4           "0001010000"
+CH1_CC_MATCH3           "0110111100"
+CH1_CC_MATCH4           "0001010000"
+CH0_CC_MATCH_MODE       "2"
+CH1_CC_MATCH_MODE       "2"
+CH0_CC_MIN_IPG          "3"
+CH1_CC_MIN_IPG          "3"
+CCHMARK                 "9"
+CCLMARK                 "7"
+CH0_SSLB                "DISABLED"
+CH1_SSLB                "DISABLED"
+CH0_SPLBPORTS           "DISABLED"
+CH1_SPLBPORTS           "DISABLED"
+CH0_PCSLBPORTS          "DISABLED"
+CH1_PCSLBPORTS          "DISABLED"
+INT_ALL                 "DISABLED"
+QD_REFCK2CORE           "DISABLED"
+
+

diff --git a/trb3_gbe_test/trb3_central/sgmii33.ngo b/trb3_gbe_test/trb3_central/sgmii33.ngo
new file mode 100644 (file)
index 0000000..8e83e7a
Binary files /dev/null and b/trb3_gbe_test/trb3_central/sgmii33.ngo differ

diff --git a/trb3_gbe_test/trb3_central/trb3_central.lpf b/trb3_gbe_test/trb3_central/trb3_central.lpf
new file mode 100644 (file)
index 0000000..d060861
--- /dev/null
+++ b/trb3_gbe_test/trb3_central/trb3_central.lpf
@@ -0,0 +1,481 @@
+RVL_ALIAS "clk_gpll_right" "clk_gpll_right"; 
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+#################################################################
+# Basic Settings
+#################################################################
+SYSCONFIG MCCLK_FREQ=20 ;
+FREQUENCY PORT "CLK_PCLK_RIGHT" 200.000000 MHz ;
+FREQUENCY PORT "CLK_PCLK_LEFT" 200.000000 MHz ;
+FREQUENCY PORT "CLK_GPLL_RIGHT" 125.000000 MHz ;
+FREQUENCY PORT "CLK_GPLL_LEFT" 200.000000 MHz ;
+FREQUENCY PORT "CLK_EXT_3" 10.000000 MHz ;
+FREQUENCY PORT "CLK_EXT_4" 10.000000 MHz ;
+#################################################################
+# Clock I/O
+#################################################################
+#Additional signals from Clock-RJ-45
+LOCATE COMP "CLK_EXT_3" SITE "U9" ;#was SPARE_LINE_2
+LOCATE COMP "CLK_EXT_4" SITE "Y34" ;#was SPARE_LINE_4
+LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AH22" ;
+LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AH12" ;
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "Y28" ;
+LOCATE COMP "CLK_GPLL_LEFT" SITE "Y9" ;
+LOCATE COMP "CLK_PCLK_LEFT" SITE "V9" ;
+LOCATE COMP "CLK_PCLK_RIGHT" SITE "U28" ;
+DEFINE PORT GROUP "CLK_group" "CLK*" ;
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
+LOCATE COMP "ENPIRION_CLOCK" SITE "G18" ;
+IOBUF PORT "ENPIRION_CLOCK" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ;
+#################################################################
+# Trigger I/O
+#################################################################
+#Trigger from fan-out
+LOCATE COMP "TRIGGER_RIGHT" SITE "W30" ;
+IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
+LOCATE COMP "TRIGGER_LEFT" SITE "Y2" ;
+IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ;
+#To fan-out to all FPGA
+LOCATE COMP "TRIGGER_OUT" SITE "V7" ;
+IOBUF PORT "TRIGGER_OUT" IO_TYPE=LVDS25 ;
+#Additional lines on Trigger-RJ-45
+LOCATE COMP "TRIGGER_EXT_2" SITE "W2" ;
+LOCATE COMP "TRIGGER_EXT_3" SITE "W8" ;#was EXT_TRIG_2
+LOCATE COMP "TRIGGER_EXT_4" SITE "W4" ;#was EXT_TRIG_4
+DEFINE PORT GROUP "TRIGGER_EXT_group" "TRIGGER_EXT*" ;
+IOBUF GROUP "TRIGGER_EXT_group" IO_TYPE=LVDS25 ;
+#################################################################
+# Clock and Trigger Select
+#################################################################
+#Trigger select for fan-out. 0: external trigger. 1: TRIGGER_OUT
+LOCATE COMP "TRIGGER_SELECT" SITE "AA31" ;
+IOBUF PORT "TRIGGER_SELECT" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4 ;
+LOCATE COMP "CLK_MNGR1_USER_0" SITE "AA28" ;
+LOCATE COMP "CLK_MNGR1_USER_1" SITE "AA27" ;
+LOCATE COMP "CLK_MNGR1_USER_2" SITE "AB32" ;
+LOCATE COMP "CLK_MNGR1_USER_3" SITE "AB31" ;
+LOCATE COMP "CLK_MNGR2_USER_0" SITE "AE34" ;
+LOCATE COMP "CLK_MNGR2_USER_1" SITE "AE33" ;
+LOCATE COMP "CLK_MNGR2_USER_2" SITE "AB26" ;
+LOCATE COMP "CLK_MNGR2_USER_3" SITE "AB25" ;
+DEFINE PORT GROUP "CLK_MNGR_group" "CLK_MNGR*" ;
+IOBUF GROUP "CLK_MNGR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8 ;
+LOCATE COMP "CLOCK_SELECT" SITE "AA30" ;
+IOBUF PORT "CLOCK_SELECT" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4 ;
+#################################################################
+# LED
+#################################################################
+LOCATE COMP "LED_GREEN" SITE "A17" ;
+LOCATE COMP "LED_ORANGE" SITE "B17" ;
+LOCATE COMP "LED_RED" SITE "E19" ;
+LOCATE COMP "LED_YELLOW" SITE "E20" ;
+IOBUF PORT "LED_GREEN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ;
+IOBUF PORT "LED_ORANGE" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ;
+IOBUF PORT "LED_RED" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ;
+IOBUF PORT "LED_YELLOW" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ;
+LOCATE COMP "LED_TRIGGER_GREEN" SITE "AP5" ;
+LOCATE COMP "LED_TRIGGER_RED" SITE "AP6" ;
+LOCATE COMP "LED_CLOCK_GREEN" SITE "AL4" ;
+LOCATE COMP "LED_CLOCK_RED" SITE "AM4" ;
+IOBUF PORT "LED_TRIGGER_GREEN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+IOBUF PORT "LED_TRIGGER_RED" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+IOBUF PORT "LED_CLOCK_GREEN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+IOBUF PORT "LED_CLOCK_RED" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+#################################################################
+# Inter-FPGA Connection
+#################################################################
+LOCATE COMP "FPGA1_COMM_0" SITE "AC9" ;
+LOCATE COMP "FPGA1_COMM_10" SITE "AJ1" ;
+LOCATE COMP "FPGA1_COMM_11" SITE "AK1" ;
+LOCATE COMP "FPGA1_COMM_1" SITE "AC8" ;
+LOCATE COMP "FPGA1_COMM_2" SITE "AE2" ;
+LOCATE COMP "FPGA1_COMM_3" SITE "AE1" ;
+LOCATE COMP "FPGA1_COMM_4" SITE "AE4" ;
+LOCATE COMP "FPGA1_COMM_5" SITE "AE3" ;
+LOCATE COMP "FPGA1_COMM_6" SITE "AB10" ;
+LOCATE COMP "FPGA1_COMM_7" SITE "AC10" ;
+LOCATE COMP "FPGA1_COMM_8" SITE "AD4" ;
+LOCATE COMP "FPGA1_COMM_9" SITE "AD3" ;
+LOCATE COMP "FPGA2_COMM_0" SITE "P5" ;
+LOCATE COMP "FPGA2_COMM_10" SITE "M10" ;
+LOCATE COMP "FPGA2_COMM_11" SITE "N10" ;
+LOCATE COMP "FPGA2_COMM_1" SITE "P4" ;
+LOCATE COMP "FPGA2_COMM_2" SITE "N8" ;
+LOCATE COMP "FPGA2_COMM_3" SITE "P8" ;
+LOCATE COMP "FPGA2_COMM_4" SITE "M5" ;
+LOCATE COMP "FPGA2_COMM_5" SITE "N5" ;
+LOCATE COMP "FPGA2_COMM_6" SITE "R7" ;
+LOCATE COMP "FPGA2_COMM_7" SITE "R5" ;
+LOCATE COMP "FPGA2_COMM_8" SITE "N2" ;
+LOCATE COMP "FPGA2_COMM_9" SITE "N1" ;
+LOCATE COMP "FPGA3_COMM_0" SITE "AC28" ;
+LOCATE COMP "FPGA3_COMM_10" SITE "AF32" ;
+LOCATE COMP "FPGA3_COMM_11" SITE "AF31" ;
+LOCATE COMP "FPGA3_COMM_1" SITE "AB27" ;
+LOCATE COMP "FPGA3_COMM_2" SITE "AE32" ;
+LOCATE COMP "FPGA3_COMM_3" SITE "AE31" ;
+LOCATE COMP "FPGA3_COMM_4" SITE "AE30" ;
+LOCATE COMP "FPGA3_COMM_5" SITE "AE29" ;
+LOCATE COMP "FPGA3_COMM_6" SITE "AC25" ;
+LOCATE COMP "FPGA3_COMM_7" SITE "AC26" ;
+LOCATE COMP "FPGA3_COMM_8" SITE "AD26" ;
+LOCATE COMP "FPGA3_COMM_9" SITE "AD25" ;
+LOCATE COMP "FPGA4_COMM_0" SITE "AN32" ;
+LOCATE COMP "FPGA4_COMM_10" SITE "AM29" ;
+LOCATE COMP "FPGA4_COMM_11" SITE "AN29" ;
+LOCATE COMP "FPGA4_COMM_1" SITE "AM32" ;
+LOCATE COMP "FPGA4_COMM_2" SITE "AP29" ;
+LOCATE COMP "FPGA4_COMM_3" SITE "AP30" ;
+LOCATE COMP "FPGA4_COMM_4" SITE "AL30" ;
+LOCATE COMP "FPGA4_COMM_5" SITE "AM30" ;
+LOCATE COMP "FPGA4_COMM_6" SITE "AL31" ;
+LOCATE COMP "FPGA4_COMM_7" SITE "AM31" ;
+LOCATE COMP "FPGA4_COMM_8" SITE "AP31" ;
+LOCATE COMP "FPGA4_COMM_9" SITE "AN31" ;
+#################################################################
+# Connection to small AddOns
+#################################################################
+LOCATE COMP "FPGA1_CONNECTOR_0" SITE "AN1" ;
+LOCATE COMP "FPGA1_CONNECTOR_1" SITE "AN2" ;
+LOCATE COMP "FPGA1_CONNECTOR_2" SITE "AD9" ;
+LOCATE COMP "FPGA1_CONNECTOR_3" SITE "AD8" ;
+LOCATE COMP "FPGA1_CONNECTOR_4" SITE "AP2" ;
+LOCATE COMP "FPGA1_CONNECTOR_5" SITE "AP3" ;
+LOCATE COMP "FPGA1_CONNECTOR_6" SITE "AJ2" ;
+LOCATE COMP "FPGA1_CONNECTOR_7" SITE "AJ3" ;
+LOCATE COMP "FPGA2_CONNECTOR_0" SITE "P9" ;
+LOCATE COMP "FPGA2_CONNECTOR_1" SITE "P10" ;
+LOCATE COMP "FPGA2_CONNECTOR_2" SITE "R2" ;
+LOCATE COMP "FPGA2_CONNECTOR_3" SITE "R1" ;
+LOCATE COMP "FPGA2_CONNECTOR_4" SITE "P7" ;
+LOCATE COMP "FPGA2_CONNECTOR_5" SITE "P6" ;
+LOCATE COMP "FPGA2_CONNECTOR_6" SITE "R4" ;
+LOCATE COMP "FPGA2_CONNECTOR_7" SITE "R3" ;
+LOCATE COMP "FPGA3_CONNECTOR_0" SITE "AN34" ;
+LOCATE COMP "FPGA3_CONNECTOR_1" SITE "AN33" ;
+LOCATE COMP "FPGA3_CONNECTOR_2" SITE "AH33" ;
+LOCATE COMP "FPGA3_CONNECTOR_3" SITE "AJ33" ;
+LOCATE COMP "FPGA3_CONNECTOR_4" SITE "AP33" ;
+LOCATE COMP "FPGA3_CONNECTOR_5" SITE "AP32" ;
+LOCATE COMP "FPGA3_CONNECTOR_6" SITE "AL34" ;
+LOCATE COMP "FPGA3_CONNECTOR_7" SITE "AL33" ;
+LOCATE COMP "FPGA4_CONNECTOR_0" SITE "AK27" ;
+LOCATE COMP "FPGA4_CONNECTOR_1" SITE "AJ27" ;
+LOCATE COMP "FPGA4_CONNECTOR_2" SITE "AK28" ;
+LOCATE COMP "FPGA4_CONNECTOR_3" SITE "AJ28" ;
+LOCATE COMP "FPGA4_CONNECTOR_4" SITE "AH27" ;
+LOCATE COMP "FPGA4_CONNECTOR_5" SITE "AH28" ;
+LOCATE COMP "FPGA4_CONNECTOR_6" SITE "AL29" ;
+LOCATE COMP "FPGA4_CONNECTOR_7" SITE "AK29" ;
+DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
+IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+LOCATE COMP "FPGA1_TTL_0" SITE "J21" ;#202 #was F1_3V3_LINE etc.
+LOCATE COMP "FPGA1_TTL_1" SITE "H22" ;#204
+LOCATE COMP "FPGA1_TTL_2" SITE "A23" ;#206
+LOCATE COMP "FPGA1_TTL_3" SITE "B23" ;#208
+LOCATE COMP "FPGA2_TTL_0" SITE "E22" ;#202
+LOCATE COMP "FPGA2_TTL_1" SITE "E23" ;#204
+LOCATE COMP "FPGA2_TTL_2" SITE "C23" ;#206
+LOCATE COMP "FPGA2_TTL_3" SITE "D23" ;#208
+LOCATE COMP "FPGA3_TTL_0" SITE "K22" ;#202
+LOCATE COMP "FPGA3_TTL_1" SITE "K21" ;#204
+LOCATE COMP "FPGA3_TTL_2" SITE "A24" ;#206
+LOCATE COMP "FPGA3_TTL_3" SITE "B24" ;#208
+LOCATE COMP "FPGA4_TTL_0" SITE "G23" ;#202
+LOCATE COMP "FPGA4_TTL_1" SITE "H23" ;#204
+LOCATE COMP "FPGA4_TTL_2" SITE "D24" ;#206
+LOCATE COMP "FPGA4_TTL_3" SITE "E24" ;#208
+DEFINE PORT GROUP "FPGATTL_group" "*TTL*" ;
+IOBUF GROUP "FPGATTL_group" IO_TYPE=LVTTL33 PULLMODE=DOWN DRIVE=8 ;
+#################################################################
+# SFP Control / Status
+#################################################################
+LOCATE COMP "SFP_TX_FAULT_1" SITE "K23" ;
+LOCATE COMP "SFP_TX_FAULT_2" SITE "D21" ;
+LOCATE COMP "SFP_TX_FAULT_3" SITE "H19" ;
+LOCATE COMP "SFP_TX_FAULT_4" SITE "A18" ;
+LOCATE COMP "SFP_TX_FAULT_5" SITE "D25" ;
+LOCATE COMP "SFP_TX_FAULT_6" SITE "D27" ;
+LOCATE COMP "SFP_TX_FAULT_7" SITE "D20" ;
+LOCATE COMP "SFP_TX_FAULT_8" SITE "J19" ;
+LOCATE COMP "SFP_RATE_SEL_1" SITE "C25" ;
+LOCATE COMP "SFP_RATE_SEL_2" SITE "J22" ;
+LOCATE COMP "SFP_RATE_SEL_3" SITE "D19" ;
+LOCATE COMP "SFP_RATE_SEL_4" SITE "G19" ;
+LOCATE COMP "SFP_RATE_SEL_5" SITE "C27" ;
+LOCATE COMP "SFP_RATE_SEL_6" SITE "A29" ;
+LOCATE COMP "SFP_RATE_SEL_7" SITE "E16" ;
+LOCATE COMP "SFP_RATE_SEL_8" SITE "C20" ;
+LOCATE COMP "SFP_LOS_1" SITE "K24" ;
+LOCATE COMP "SFP_LOS_2" SITE "E21" ;
+LOCATE COMP "SFP_LOS_3" SITE "A19" ;
+LOCATE COMP "SFP_LOS_4" SITE "B18" ;
+LOCATE COMP "SFP_LOS_5" SITE "G26" ;
+LOCATE COMP "SFP_LOS_6" SITE "E27" ;
+LOCATE COMP "SFP_LOS_7" SITE "F21" ;
+LOCATE COMP "SFP_LOS_8" SITE "K19" ;
+LOCATE COMP "SFP_TXDIS_1" SITE "A25" ;
+LOCATE COMP "SFP_TXDIS_2" SITE "H20" ;
+LOCATE COMP "SFP_TXDIS_3" SITE "B19" ;
+LOCATE COMP "SFP_TXDIS_4" SITE "J18" ;
+LOCATE COMP "SFP_TXDIS_5" SITE "G25" ;
+LOCATE COMP "SFP_TXDIS_6" SITE "B28" ;
+LOCATE COMP "SFP_TXDIS_7" SITE "F22" ;
+LOCATE COMP "SFP_TXDIS_8" SITE "A20" ;
+LOCATE COMP "SFP_MOD0_1" SITE "B25" ;
+LOCATE COMP "SFP_MOD0_2" SITE "J20" ;
+LOCATE COMP "SFP_MOD0_3" SITE "K20" ;
+LOCATE COMP "SFP_MOD0_4" SITE "H18" ;
+LOCATE COMP "SFP_MOD0_5" SITE "C26" ;
+LOCATE COMP "SFP_MOD0_6" SITE "A28" ;
+LOCATE COMP "SFP_MOD0_7" SITE "A21" ;
+LOCATE COMP "SFP_MOD0_8" SITE "B20" ;
+LOCATE COMP "SFP_MOD1_1" SITE "C28" ;
+LOCATE COMP "SFP_MOD1_2" SITE "A22" ;
+LOCATE COMP "SFP_MOD1_3" SITE "L19" ;
+LOCATE COMP "SFP_MOD1_4" SITE "D18" ;
+LOCATE COMP "SFP_MOD1_5" SITE "D26" ;
+LOCATE COMP "SFP_MOD1_6" SITE "A26" ;
+LOCATE COMP "SFP_MOD1_7" SITE "B21" ;
+LOCATE COMP "SFP_MOD1_8" SITE "G20" ;
+LOCATE COMP "SFP_MOD2_1" SITE "D28" ;
+LOCATE COMP "SFP_MOD2_2" SITE "B22" ;
+LOCATE COMP "SFP_MOD2_3" SITE "C19" ;
+LOCATE COMP "SFP_MOD2_4" SITE "E18" ;
+LOCATE COMP "SFP_MOD2_5" SITE "B27" ;
+LOCATE COMP "SFP_MOD2_6" SITE "A27" ;
+LOCATE COMP "SFP_MOD2_7" SITE "F16" ;
+LOCATE COMP "SFP_MOD2_8" SITE "G21" ;
+DEFINE PORT GROUP "SFP_group" "SFP*" ;
+IOBUF GROUP "SFP_group" IO_TYPE=LVTTL33 PULLMODE=UP ;
+#################################################################
+# Main AddOn Connector 
+#################################################################
+LOCATE COMP "ADDON_RESET" SITE "J23" ;
+IOBUF PORT "ADDON_RESET" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ;
+LOCATE COMP "ADDON_TO_TRB_CLK" SITE "J17" ;
+IOBUF PORT "ADDON_TO_TRB_CLK" IO_TYPE=LVDS25 ;
+LOCATE COMP "TRB_TO_ADDON_CLK" SITE "K16" ;
+IOBUF PORT "TRB_TO_ADDON_CLK" IO_TYPE=LVCMOS25 ;
+LOCATE COMP "TRB_TO_ADDON_CLKb" SITE "L16" ;
+IOBUF PORT "TRB_TO_ADDON_CLKb" IO_TYPE=LVCMOS25 ;
+LOCATE COMP "ADO_LV_0" SITE "D5" ;
+LOCATE COMP "ADO_LV_1" SITE "C6" ;
+LOCATE COMP "ADO_LV_2" SITE "A4" ;
+LOCATE COMP "ADO_LV_3" SITE "A5" ;
+LOCATE COMP "ADO_LV_4" SITE "B4" ;
+LOCATE COMP "ADO_LV_5" SITE "A3" ;
+LOCATE COMP "ADO_LV_6" SITE "B3" ;
+LOCATE COMP "ADO_LV_7" SITE "A2" ;
+LOCATE COMP "ADO_LV_8" SITE "B1" ;
+LOCATE COMP "ADO_LV_9" SITE "B2" ;
+LOCATE COMP "ADO_LV_10" SITE "C3" ;
+LOCATE COMP "ADO_LV_11" SITE "C4" ;
+LOCATE COMP "ADO_LV_12" SITE "D3" ;
+LOCATE COMP "ADO_LV_13" SITE "C2" ;
+LOCATE COMP "ADO_LV_14" SITE "E4" ;
+LOCATE COMP "ADO_LV_15" SITE "D4" ;
+LOCATE COMP "ADO_LV_16" SITE "D6" ;
+LOCATE COMP "ADO_LV_17" SITE "C5" ;
+LOCATE COMP "ADO_LV_18" SITE "B6" ;
+LOCATE COMP "ADO_LV_19" SITE "A6" ;
+LOCATE COMP "ADO_LV_20" SITE "B7" ;
+LOCATE COMP "ADO_LV_21" SITE "A7" ;
+LOCATE COMP "ADO_LV_22" SITE "B8" ;
+LOCATE COMP "ADO_LV_23" SITE "C8" ;
+LOCATE COMP "ADO_LV_24" SITE "A8" ;
+LOCATE COMP "ADO_LV_25" SITE "A9" ;
+LOCATE COMP "ADO_LV_26" SITE "K11" ;
+LOCATE COMP "ADO_LV_27" SITE "J11" ;
+LOCATE COMP "ADO_LV_28" SITE "D12" ;
+LOCATE COMP "ADO_LV_29" SITE "E12" ;
+LOCATE COMP "ADO_LV_30" SITE "A12" ;
+LOCATE COMP "ADO_LV_31" SITE "B12" ;
+LOCATE COMP "ADO_LV_32" SITE "A11" ;
+LOCATE COMP "ADO_LV_33" SITE "B11" ;
+LOCATE COMP "ADO_LV_34" SITE "A10" ;
+LOCATE COMP "ADO_LV_35" SITE "B10" ;
+LOCATE COMP "ADO_LV_36" SITE "C11" ;
+LOCATE COMP "ADO_LV_37" SITE "D11" ;
+LOCATE COMP "ADO_LV_38" SITE "D9" ;
+LOCATE COMP "ADO_LV_39" SITE "C9" ;
+LOCATE COMP "ADO_LV_40" SITE "E11" ;
+LOCATE COMP "ADO_LV_41" SITE "F12" ;
+LOCATE COMP "ADO_LV_42" SITE "F10" ;
+LOCATE COMP "ADO_LV_43" SITE "E10" ;
+LOCATE COMP "ADO_LV_44" SITE "G11" ;
+LOCATE COMP "ADO_LV_45" SITE "G12" ;
+LOCATE COMP "ADO_LV_46" SITE "H11" ;
+LOCATE COMP "ADO_LV_47" SITE "H12" ;
+LOCATE COMP "ADO_LV_48" SITE "J14" ;
+LOCATE COMP "ADO_LV_49" SITE "H13" ;
+LOCATE COMP "ADO_LV_50" SITE "J12" ;
+LOCATE COMP "ADO_LV_51" SITE "K12" ;
+LOCATE COMP "ADO_LV_52" SITE "K13" ;
+LOCATE COMP "ADO_LV_53" SITE "J13" ;
+LOCATE COMP "ADO_LV_54" SITE "K14" ;
+LOCATE COMP "ADO_LV_55" SITE "K15" ;
+LOCATE COMP "ADO_LV_56" SITE "E13" ;
+LOCATE COMP "ADO_LV_57" SITE "F13" ;
+LOCATE COMP "ADO_LV_58" SITE "G13" ;
+LOCATE COMP "ADO_LV_59" SITE "H14" ;
+LOCATE COMP "ADO_LV_60" SITE "A13" ;
+LOCATE COMP "ADO_LV_61" SITE "B13" ;
+DEFINE PORT GROUP "ADO_LV_group" "ADO_LV*" ;
+IOBUF GROUP "ADO_LV_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ;
+LOCATE COMP "ADO_TTL_0" SITE "R26" ;
+LOCATE COMP "ADO_TTL_1" SITE "R25" ;
+LOCATE COMP "ADO_TTL_2" SITE "P26" ;
+LOCATE COMP "ADO_TTL_3" SITE "N26" ;
+LOCATE COMP "ADO_TTL_4" SITE "M25" ;
+LOCATE COMP "ADO_TTL_5" SITE "M26" ;
+LOCATE COMP "ADO_TTL_6" SITE "L26" ;
+LOCATE COMP "ADO_TTL_7" SITE "P28" ;
+LOCATE COMP "ADO_TTL_8" SITE "P27" ;
+LOCATE COMP "ADO_TTL_9" SITE "N27" ;
+LOCATE COMP "ADO_TTL_10" SITE "M27" ;
+LOCATE COMP "ADO_TTL_11" SITE "L28" ;
+LOCATE COMP "ADO_TTL_12" SITE "K29" ;
+LOCATE COMP "ADO_TTL_13" SITE "K30" ;
+LOCATE COMP "ADO_TTL_14" SITE "M28" ;
+LOCATE COMP "ADO_TTL_15" SITE "M29" ;
+LOCATE COMP "ADO_TTL_16" SITE "L33" ;
+LOCATE COMP "ADO_TTL_17" SITE "L32" ;
+LOCATE COMP "ADO_TTL_18" SITE "M30" ;
+LOCATE COMP "ADO_TTL_19" SITE "N32" ;
+LOCATE COMP "ADO_TTL_20" SITE "R27" ;
+LOCATE COMP "ADO_TTL_21" SITE "R28" ;
+LOCATE COMP "ADO_TTL_22" SITE "N28" ;
+LOCATE COMP "ADO_TTL_23" SITE "R29" ;
+LOCATE COMP "ADO_TTL_24" SITE "R30" ;
+LOCATE COMP "ADO_TTL_25" SITE "R31" ;
+LOCATE COMP "ADO_TTL_26" SITE "P32" ;
+LOCATE COMP "ADO_TTL_27" SITE "R34" ;
+LOCATE COMP "ADO_TTL_28" SITE "P33" ;
+LOCATE COMP "ADO_TTL_29" SITE "P34" ;
+LOCATE COMP "ADO_TTL_30" SITE "P30" ;
+LOCATE COMP "ADO_TTL_31" SITE "N34" ;
+LOCATE COMP "ADO_TTL_32" SITE "M34" ;
+LOCATE COMP "ADO_TTL_33" SITE "M31" ;
+LOCATE COMP "ADO_TTL_34" SITE "M33" ;
+LOCATE COMP "ADO_TTL_35" SITE "L34" ;
+LOCATE COMP "ADO_TTL_36" SITE "L31" ;
+LOCATE COMP "ADO_TTL_37" SITE "K34" ;
+LOCATE COMP "ADO_TTL_38" SITE "K33" ;
+LOCATE COMP "ADO_TTL_39" SITE "K32" ;
+LOCATE COMP "ADO_TTL_40" SITE "K31" ;
+LOCATE COMP "ADO_TTL_41" SITE "L30" ;
+LOCATE COMP "ADO_TTL_42" SITE "N33" ;
+LOCATE COMP "ADO_TTL_43" SITE "N30" ;
+LOCATE COMP "ADO_TTL_44" SITE "N29" ;
+LOCATE COMP "ADO_TTL_45" SITE "N31" ;
+LOCATE COMP "ADO_TTL_46" SITE "P31" ;
+DEFINE PORT GROUP "ADO_TTL_group" "ADO_TTL*" ;
+IOBUF GROUP "ADO_TTL_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8 ;
+LOCATE COMP "FS_PE_0" SITE "T26" ;
+LOCATE COMP "FS_PE_1" SITE "U26" ;
+LOCATE COMP "FS_PE_2" SITE "U27" ;
+LOCATE COMP "FS_PE_3" SITE "U31" ;
+LOCATE COMP "FS_PE_4" SITE "V33" ;
+LOCATE COMP "FS_PE_5" SITE "V34" ;
+LOCATE COMP "FS_PE_6" SITE "U32" ;
+LOCATE COMP "FS_PE_7" SITE "U34" ;
+LOCATE COMP "FS_PE_8" SITE "U33" ;
+LOCATE COMP "FS_PE_9" SITE "T34" ;
+LOCATE COMP "FS_PE_10" SITE "T33" ;
+LOCATE COMP "FS_PE_11" SITE "T32" ;
+LOCATE COMP "FS_PE_12" SITE "T31" ;
+LOCATE COMP "FS_PE_13" SITE "T30" ;
+LOCATE COMP "FS_PE_14" SITE "U30" ;
+LOCATE COMP "FS_PE_15" SITE "T29" ;
+LOCATE COMP "FS_PE_16" SITE "T28" ;
+LOCATE COMP "FS_PE_17" SITE "T27" ;
+DEFINE PORT GROUP "FS_PE_group" "FS_PE*" ;
+IOBUF GROUP "FS_PE_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8 ;
+#################################################################
+# Flash ROM and Reboot
+#################################################################
+LOCATE COMP "FLASH_CLK" SITE "C30" ;
+LOCATE COMP "FLASH_CS" SITE "A31" ;
+LOCATE COMP "FLASH_DIN" SITE "B31" ;
+LOCATE COMP "FLASH_DOUT" SITE "C29" ;
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+LOCATE COMP "PROGRAMN" SITE "H25" ;
+IOBUF PORT "PROGRAMN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ;
+#################################################################
+# Test Connector  (Order corrected to match pin-out of connector!)
+#################################################################
+LOCATE COMP "TEST_LINE_4" SITE "G4" ;# "TEST_LINE_0" 
+LOCATE COMP "TEST_LINE_5" SITE "G5" ;# "TEST_LINE_1" 
+LOCATE COMP "TEST_LINE_2" SITE "H5" ;# "TEST_LINE_2" 
+LOCATE COMP "TEST_LINE_3" SITE "H4" ;# "TEST_LINE_3" 
+LOCATE COMP "TEST_LINE_10" SITE "F2" ;# "TEST_LINE_4" 
+LOCATE COMP "TEST_LINE_11" SITE "F1" ;# "TEST_LINE_5" 
+LOCATE COMP "TEST_LINE_6" SITE "F3" ;# "TEST_LINE_6" 
+LOCATE COMP "TEST_LINE_7" SITE "E3" ;# "TEST_LINE_7" 
+LOCATE COMP "TEST_LINE_12" SITE "G2" ;# "TEST_LINE_8" 
+LOCATE COMP "TEST_LINE_13" SITE "G1" ;# "TEST_LINE_9" 
+LOCATE COMP "TEST_LINE_8" SITE "G3" ;# "TEST_LINE_10"
+LOCATE COMP "TEST_LINE_9" SITE "H3" ;# "TEST_LINE_11"
+LOCATE COMP "TEST_LINE_14" SITE "H1" ;# "TEST_LINE_12"
+LOCATE COMP "TEST_LINE_15" SITE "J1" ;# "TEST_LINE_13"
+LOCATE COMP "TEST_LINE_0" SITE "J3" ;# "TEST_LINE_14"
+LOCATE COMP "TEST_LINE_1" SITE "H2" ;# "TEST_LINE_15"
+LOCATE COMP "TEST_LINE_20" SITE "K4" ;# "TEST_LINE_16"
+LOCATE COMP "TEST_LINE_21" SITE "K3" ;# "TEST_LINE_17"
+LOCATE COMP "TEST_LINE_26" SITE "K7" ;# "TEST_LINE_18"
+LOCATE COMP "TEST_LINE_27" SITE "J6" ;# "TEST_LINE_19"
+LOCATE COMP "TEST_LINE_16" SITE "K2" ;# "TEST_LINE_20"
+LOCATE COMP "TEST_LINE_17" SITE "K1" ;# "TEST_LINE_21"
+LOCATE COMP "TEST_LINE_30" SITE "L10" ;# "TEST_LINE_22"
+LOCATE COMP "TEST_LINE_31" SITE "L9" ;# "TEST_LINE_23"
+LOCATE COMP "TEST_LINE_18" SITE "L2" ;# "TEST_LINE_24"
+LOCATE COMP "TEST_LINE_19" SITE "L1" ;# "TEST_LINE_25"
+LOCATE COMP "TEST_LINE_28" SITE "M8" ;# "TEST_LINE_26"
+LOCATE COMP "TEST_LINE_29" SITE "L7" ;# "TEST_LINE_27"
+LOCATE COMP "TEST_LINE_22" SITE "L5" ;# "TEST_LINE_28"
+LOCATE COMP "TEST_LINE_23" SITE "L4" ;# "TEST_LINE_29"
+LOCATE COMP "TEST_LINE_24" SITE "K6" ;# "TEST_LINE_30"
+LOCATE COMP "TEST_LINE_25" SITE "K5" ;# "TEST_LINE_31"
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8 ;
+#################################################################
+# Misc
+#################################################################
+LOCATE COMP "TEMPSENS" SITE "D22" ;
+IOBUF PORT "TEMPSENS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+#################################################################
+# Basic Settings
+#################################################################
+SYSCONFIG MCCLK_FREQ=20 ;
+FREQUENCY PORT "CLK_PCLK_RIGHT" 200.000000 MHz ;
+FREQUENCY PORT "CLK_PCLK_LEFT" 200.000000 MHz ;
+FREQUENCY PORT "CLK_GPLL_RIGHT" 125.000000 MHz ;
+FREQUENCY PORT "CLK_GPLL_LEFT" 200.000000 MHz ;
+FREQUENCY PORT "CLK_EXT_3" 10.000000 MHz ;
+FREQUENCY PORT "CLK_EXT_4" 10.000000 MHz ;
+#################################################################
+# Reset Nets
+#################################################################  
+GSR_NET NET "GSR_N";
+#################################################################
+# Locate Serdes and media interfaces
+#################################################################
+#LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+#LOCATE COMP "THE_MEDIA_ONBOARD/THE_SERDES/PCSD_INST" SITE "PCSC" ;
+LOCATE COMP "SERDES_INST/PCSD_INST" SITE "PCSB" ;
+FREQUENCY NET "SERDES_INST/FF_RX_F_CLK_0" 125.000000 MHz ;
+FREQUENCY NET "SERDES_INST/FF_TX_F_CLK_0" 125.000000 MHz ;
+BLOCK JTAGPATHS ;
+REGION "media_region" "ALU24_R88C44" 27 77 DEVSIZE;
+UGROUP "media_group" 
+       BLKNAME SERDES_INST
+       BLKNAME SGMII_INST
+       BLKNAME SGMII2_INST;
+LOCATE UGROUP "media_group" REGION "media_region" ;
+FREQUENCY NET "clk_125_i" 125.000000 MHz ;