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diff --git a/testbenches/error_check.vhd b/testbenches/error_check.vhd
new file mode 100644 (file)
index 0000000..4163959
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+++ b/testbenches/error_check.vhd
@@ -0,0 +1,90 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+USE ieee.math_real.all;
+
+library work;
+
+entity error_check is
+port(
+       RXCLK_IN             : in  std_logic;
+       RESET_IN             : in  std_logic;
+
+       DATA_TX_IN             : in  std_logic_vector(15 downto 0);
+       DATA_TX_DATAREADY_IN   : in  std_logic;
+       DATA_TX_READ_IN        : in  std_logic;
+       DATA_RX_IN             : in  std_logic_vector(15 downto 0);
+       DATA_RX_VALID_IN       : in  std_logic
+
+  );
+end entity;
+
+architecture arch of error_check is
+ 
+component fifo_18x2k_oreg is
+    port (
+        Data: in  std_logic_vector(17 downto 0); 
+        Clock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        AmFullThresh: in  std_logic_vector(10 downto 0); 
+        Q: out  std_logic_vector(17 downto 0); 
+        WCNT: out  std_logic_vector(11 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostFull: out  std_logic);
+end component;
+
+signal fifo_wr_en    : std_logic;
+signal fifo_q        : std_logic_vector(15 downto 0);
+signal data_q        : std_logic_vector(15 downto 0);
+signal data_qq       : std_logic_vector(15 downto 0);
+signal check_q       : std_logic;
+signal check_qq      : std_logic;
+
+
+begin
+
+SYNC_PROC : process
+begin
+       wait until rising_edge(RXCLK_IN);
+       data_q  <= data_qq;
+       data_qq <= DATA2_IN;
+       check_q <= check_qq;
+       check_qq <= DATA2_VALID_IN;
+
+end process;
+
+
+fifo_wr_en <= '1' when DATA_TX_DATAREADY_IN = '1' and DATA_TX_READ_IN = '1' else '0';
+fifo : fifo_18x2k_oreg
+    port map(
+        Data(15 downto 0)         => DATA_TX_IN,
+       data(17 downto 16)        => "00";
+        Clock        => RXCLK_IN,
+        WrEn         => fifo_wr_en,
+        RdEn         => DATA_RX_VALID_IN,
+        Reset        => RESET_IN,
+        AmFullThresh => open,
+        Q(15 downto 0)            => fifo_q,
+       Q(17 downto 16)           => open,
+        WCNT         => open,
+        Empty        => open,
+        Full         => open,
+        AlmostFull   => open
+);
+
+CHECK_PROC : process
+begin
+       wait until rising_edge(RXCLK_IN);
+
+       assert 
+               ((check_qq = '1') and 
+               (fifo_q(15 downto 4) /= data_q(15 downto 4)) and
+               (fifo_q(2 downto 0) /= data_q(2 downto 0)))
+       report "data invalid" severity warning;
+end process;
+
+
+end architecture;
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