HUB_ADDRESS : std_logic_vector(15 downto 0) := x"F001";
HUB_CTRL_CHANNELNUM : integer range 0 to 2**(MUX_WIDTH-1)-1 := 3;
HUB_CTRL_DEPTH : integer range 0 to 6 := 1;
+ HUB_CTRL_REG_ADDR_WIDTH : integer range 1 to 7 := 4;
--media interfaces
MII_NUMBER : integer range 2 to 16 := 2;
--each row is one media interface and each column is one channel. starting with 0,0, ending with 15,15
TRG_ERROR_PATTERN_IN : in std_logic_vector (TRG_NUMBER*32 downto 0);
TRG_RELEASE_IN : in std_logic_vector (TRG_NUMBER downto 0);
--Status ports (for debugging)
- HUB_STAT_CHANNEL : out std_logic_vector (2**(MUX_WIDTH-1)*32-1 downto 0);
+ HUB_STAT_CHANNEL : out std_logic_vector (2**(MUX_WIDTH-1)*16-1 downto 0);
HUB_STAT_GEN : out std_logic_vector (31 downto 0);
- HUB_CTRL_CHANNEL : in std_logic_vector (2**(MUX_WIDTH-1)*32-1 downto 0);
- HUB_CTRL_activepoints : in std_logic_vector (2**(MUX_WIDTH-1)*32-1 downto 0);
- HUB_CTRL_GEN : in std_logic_vector (31 downto 0);
+-- HUB_CTRL_CHANNEL : in std_logic_vector (2**(MUX_WIDTH-1)*16-1 downto 0);
+-- HUB_CTRL_activepoints : in std_logic_vector (2**(MUX_WIDTH-1)*32-1 downto 0);
+-- HUB_CTRL_GEN : in std_logic_vector (31 downto 0);
MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
- MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
- IOBUF_STAT_GEN : out std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
- IOBUF_STAT_LOCKED : out std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
- IOBUF_STAT_INIT_BUFFER : out std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
- IOBUF_STAT_REPLY_BUFFER : out std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
- IOBUF_CTRL_GEN : in std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
- IOBUF_CTRL_LOCKED : in std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
- IOBUF_STAT_CTRL_INIT_BUFFER : in std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
- IOBUF_STAT_CTRL_REPLY_BUFFER : in std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0)
+ MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0)
);
end entity;
signal hub_to_buf_INIT_PACKET_NUM:std_logic_vector (total_point_num*NUM_WIDTH-1 downto 0);
signal hub_to_buf_INIT_READ : std_logic_vector (total_point_num-1 downto 0);
- signal buf_to_hub_INIT_DATAREADY: std_logic_vector (total_point_num-1 downto 0);
- signal buf_to_hub_INIT_DATA : std_logic_vector (total_point_num*DATA_WIDTH-1 downto 0);
+ signal buf_to_hub_INIT_DATAREADY : std_logic_vector (total_point_num-1 downto 0);
+ signal buf_to_hub_INIT_DATA : std_logic_vector (total_point_num*DATA_WIDTH-1 downto 0);
signal buf_to_hub_INIT_PACKET_NUM:std_logic_vector (total_point_num*NUM_WIDTH-1 downto 0);
- signal buf_to_hub_INIT_READ : std_logic_vector (total_point_num-1 downto 0);
+ signal buf_to_hub_INIT_READ : std_logic_vector (total_point_num-1 downto 0);
- signal hub_to_buf_REPLY_DATAREADY: std_logic_vector (total_point_num-1 downto 0);
- signal hub_to_buf_REPLY_DATA : std_logic_vector (total_point_num*DATA_WIDTH-1 downto 0);
- signal hub_to_buf_REPLY_PACKET_NUM:std_logic_vector (total_point_num*NUM_WIDTH-1 downto 0);
- signal hub_to_buf_REPLY_READ : std_logic_vector (total_point_num-1 downto 0);
+ signal hub_to_buf_REPLY_DATAREADY : std_logic_vector (total_point_num-1 downto 0);
+ signal hub_to_buf_REPLY_DATA : std_logic_vector (total_point_num*DATA_WIDTH-1 downto 0);
+ signal hub_to_buf_REPLY_PACKET_NUM :std_logic_vector (total_point_num*NUM_WIDTH-1 downto 0);
+ signal hub_to_buf_REPLY_READ : std_logic_vector (total_point_num-1 downto 0);
signal hub_to_buf_REPLY_SEND_HEADER : std_logic_vector(total_point_num-1 downto 0);
- signal buf_to_hub_REPLY_DATAREADY: std_logic_vector (total_point_num-1 downto 0);
- signal buf_to_hub_REPLY_DATA : std_logic_vector (total_point_num*DATA_WIDTH-1 downto 0);
- signal buf_to_hub_REPLY_PACKET_NUM:std_logic_vector (total_point_num*NUM_WIDTH-1 downto 0);
- signal buf_to_hub_REPLY_READ : std_logic_vector (total_point_num-1 downto 0);
+ signal buf_to_hub_REPLY_DATAREADY : std_logic_vector (total_point_num-1 downto 0);
+ signal buf_to_hub_REPLY_DATA : std_logic_vector (total_point_num*DATA_WIDTH-1 downto 0);
+ signal buf_to_hub_REPLY_PACKET_NUM :std_logic_vector (total_point_num*NUM_WIDTH-1 downto 0);
+ signal buf_to_hub_REPLY_READ : std_logic_vector (total_point_num-1 downto 0);
signal buf_to_hub_REPLY_SEND_HEADER : std_logic_vector(total_point_num-1 downto 0);
signal HUB_INIT_DATAREADY_OUT : std_logic_vector (total_point_num-1 downto 0);
signal HUB_REPLY_READ_OUT : std_logic_vector (total_point_num-1 downto 0);
signal HUB_REPLY_SEND_HEADER_OUT : std_logic_vector (total_point_num-1 downto 0);
+ signal buf_HUB_STAT_CHANNEL : std_logic_vector (2**(MUX_WIDTH-1)*16-1 downto 0);
+ signal buf_HUB_STAT_GEN : std_logic_vector (31 downto 0);
+
signal HC_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0);
signal HC_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
signal HC_WRITE_IN : std_logic;
signal HC_RUN_OUT : std_logic;
signal HC_MY_ADDRESS_IN : std_logic_vector (15 downto 0);
signal HC_SEQNR_OUT : std_logic_vector (7 downto 0);
+ signal HC_STAT_REGS : std_logic_vector (2**(HUB_CTRL_REG_ADDR_WIDTH-1)*32-1 downto 0);
+ signal HC_CTRL_REGS : std_logic_vector (2**(HUB_CTRL_REG_ADDR_WIDTH-1)*32-1 downto 0);
+
+ signal HUB_MED_CONNECTED : std_logic_vector (31 downto 0);
+ signal HUB_CTRL_final_activepoints : std_logic_vector (2**(MUX_WIDTH-1)*32-1 downto 0);
+ signal HUB_CTRL_CHANNEL : std_logic_vector (2**(MUX_WIDTH-1)*16-1 downto 0);
+ signal HUB_CTRL_activepoints : std_logic_vector (2**(MUX_WIDTH-1)*32-1 downto 0);
+ signal HUB_CTRL_GEN : std_logic_vector (31 downto 0);
+ signal IOBUF_STAT_GEN : std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
+ signal IOBUF_STAT_LOCKED : std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
+ signal IOBUF_STAT_INIT_BUFFER : std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
+ signal IOBUF_STAT_REPLY_BUFFER : std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
+ signal IOBUF_CTRL_GEN : std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
+ signal IOBUF_CTRL_LOCKED : std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
+ signal IOBUF_STAT_CTRL_INIT_BUFFER : std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
+ signal IOBUF_STAT_CTRL_REPLY_BUFFER : std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
component trb_net16_hub_logic is
generic (
REPLY_DATA_OUT : out std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0);
REPLY_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0);
REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
- STAT : out std_logic_vector (31 downto 0);
- CTRL : in std_logic_vector (31 downto 0);
+ STAT : out std_logic_vector (15 downto 0);
+ STAT_POINTS_locked : out std_logic_vector (31 downto 0);
+ STAT_ERRORBITS : out std_logic_vector (31 downto 0);
+ CTRL : in std_logic_vector (15 downto 0);
CTRL_activepoints : in std_logic_vector (31 downto 0)
);
end component;
API_TYPE : integer := 1;
FIFO_TO_INT_DEPTH : integer := 1;
FIFO_TO_APL_DEPTH : integer := 1;
- FIFO_TERM_BUFFER_DEPTH : integer := 0);
+ FIFO_TERM_BUFFER_DEPTH : integer := 0;
+ SBUF_VERSION : integer := 0);
port(
-- Misc
CLK : in std_logic;
);
end component;
-
+ component trb_net16_regIO is
+ generic (
+ MY_ADDRESS : std_logic_vector(15 downto 0) := x"F001";
+ REGISTER_WIDTH : integer range 32 to 32 := 32;
+ ADDRESS_WIDTH : integer range 8 to 16 := 16;
+ ADDRESS_USED_WIDTH : integer range 1 to 16 := HUB_CTRL_REG_ADDR_WIDTH;
+ --standard values for output registers
+ RESET_REGISTER_OUT : std_logic_vector(2**(HUB_CTRL_REG_ADDR_WIDTH-1)*32-1 downto 0);
+ USED_REGISTER_OUT : std_logic_vector(2**(HUB_CTRL_REG_ADDR_WIDTH-1)-1 downto 0);
+ BITMASK_REGISTER_OUT : std_logic_vector(2**(HUB_CTRL_REG_ADDR_WIDTH-1)*32-1 downto 0);
+ --no data / address out?
+ NO_DAT_PORT : std_logic := '0'
+ );
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Port to API
+ API_DATA_OUT : out std_logic_vector (15 downto 0);
+ API_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ API_WRITE_OUT : out std_logic;
+ API_FIFO_FULL_IN : in std_logic;
+ API_SHORT_TRANSFER_OUT : out std_logic;
+ API_DTYPE_OUT : out std_logic_vector (3 downto 0);
+ API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
+ API_SEND_OUT : out std_logic;
+ API_TARGET_ADDRESS_OUT : out std_logic_vector (15 downto 0);
+ -- Receiver port
+ API_DATA_IN : in std_logic_vector (15 downto 0);
+ API_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ API_TYP_IN : in std_logic_vector (2 downto 0);
+ API_DATAREADY_IN : in std_logic;
+ API_READ_OUT : out std_logic;
+ -- APL Control port
+ API_RUN_IN : in std_logic;
+ API_MY_ADDRESS_OUT : out std_logic_vector (15 downto 0);
+ API_SEQNR_IN : in std_logic_vector (7 downto 0);
+ --Register in / outside
+ REGISTERS_IN : in std_logic_vector(REGISTER_WIDTH*2**(ADDRESS_USED_WIDTH-1)-1 downto 0);
+ REGISTERS_OUT : out std_logic_vector(REGISTER_WIDTH*2**(ADDRESS_USED_WIDTH-1)-1 downto 0);
+ --following ports only used when no internal register is accessed
+ DAT_ADDR_OUT : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
+ DAT_READ_ENABLE_OUT : out std_logic;
+ DAT_WRITE_ENABLE_OUT: out std_logic;
+ DAT_DATA_OUT : out std_logic_vector(REGISTER_WIDTH-1 downto 0);
+ DAT_DATA_IN : in std_logic_vector(REGISTER_WIDTH-1 downto 0);
+ DAT_DATAREADY_IN : in std_logic
+ );
+ end component;
begin
end generate;
end generate;
+ gen_MED_CON : for i in 0 to MII_NUMBER-1 generate
+ process(MED_ERROR_IN)
+ begin
+ if MED_ERROR_IN((i+1)*3-1 downto i*3) = ERROR_NC then
+ HUB_MED_CONNECTED(i) <= '0';
+ else
+ HUB_MED_CONNECTED(i) <= '1';
+ end if;
+ end process;
+
+ end generate;
+
+
+HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1');
+
+
--generate hub logic
gen_hub_logic: for i in 0 to 2**(MUX_WIDTH-1)-1 generate
constant point_num : integer := calc_point_number (MII_NUMBER, i, HUB_CTRL_CHANNELNUM, API_NUMBER, API_CHANNELS, TRG_NUMBER, TRG_CHANNELS);
constant first_point_num : integer := calc_first_point_number(MII_NUMBER, i, HUB_CTRL_CHANNELNUM, API_NUMBER, API_CHANNELS, TRG_NUMBER, TRG_CHANNELS);
constant next_point_num : integer := first_point_num + point_num;
begin
+
+ HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32) <= HUB_CTRL_activepoints((i+1)*32-1 downto i*32) and HUB_MED_CONNECTED;
HUBLOGIC : trb_net16_hub_logic
generic map (
--media interfaces
REPLY_DATA_OUT => HUB_REPLY_DATA_OUT(next_point_num*DATA_WIDTH-1 downto first_point_num*DATA_WIDTH),
REPLY_PACKET_NUM_OUT => HUB_REPLY_PACKET_NUM_OUT(next_point_num*NUM_WIDTH-1 downto first_point_num*NUM_WIDTH),
REPLY_READ_IN => HUB_REPLY_READ_IN(next_point_num-1 downto first_point_num),
- STAT => HUB_STAT_CHANNEL((i+1)*32-1 downto i*32),
- CTRL => HUB_CTRL_CHANNEL((i+1)*32-1 downto i*32),
- CTRL_activepoints => HUB_CTRL_activepoints((i+1)*32-1 downto i*32)
+ STAT => buf_HUB_STAT_CHANNEL((i+1)*16-1 downto i*16),
+ STAT_POINTS_locked => open,
+ STAT_ERRORBITS => open,
+ CTRL => HUB_CTRL_CHANNEL((i+1)*16-1 downto i*16),
+ CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32)
);
end generate;
+
+
+ hub_control : trb_net16_regIO
+ generic map(
+ MY_ADDRESS => HUB_ADDRESS,
+ REGISTER_WIDTH => 32,
+ ADDRESS_WIDTH => 16,
+ ADDRESS_USED_WIDTH => HUB_CTRL_REG_ADDR_WIDTH,
+ RESET_REGISTER_OUT => x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" &
+ x"00000000_00000000_00000000_00000000",
+ USED_REGISTER_OUT => "11111111",
+ BITMASK_REGISTER_OUT => x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" &
+ x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF",
+ NO_DAT_PORT => '1'
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- Port to API
+ API_DATA_OUT => HC_DATA_IN,
+ API_PACKET_NUM_OUT => HC_PACKET_NUM_IN,
+ API_WRITE_OUT => HC_WRITE_IN,
+ API_FIFO_FULL_IN => HC_FIFO_FULL_OUT,
+ API_SHORT_TRANSFER_OUT => HC_SHORT_TRANSFER_IN,
+ API_DTYPE_OUT => HC_DTYPE_IN,
+ API_ERROR_PATTERN_OUT => HC_ERROR_PATTERN_IN,
+ API_SEND_OUT => HC_SEND_IN,
+ API_TARGET_ADDRESS_OUT => open,
+ -- Receiver port
+ API_DATA_IN => HC_DATA_OUT,
+ API_PACKET_NUM_IN => HC_PACKET_NUM_OUT,
+ API_TYP_IN => HC_TYP_OUT,
+ API_DATAREADY_IN => HC_DATAREADY_OUT,
+ API_READ_OUT => HC_READ_IN,
+ -- HC Control port
+ API_RUN_IN => HC_RUN_OUT,
+ API_MY_ADDRESS_OUT => HC_MY_ADDRESS_IN,
+ API_SEQNR_IN => HC_SEQNR_OUT,
+ REGISTERS_IN => HC_STAT_REGS,
+ REGISTERS_OUT => HC_CTRL_REGS,
+ DAT_ADDR_OUT => open,
+ DAT_READ_ENABLE_OUT => open,
+ DAT_WRITE_ENABLE_OUT=> open,
+ DAT_DATA_OUT => open,
+ DAT_DATA_IN => x"00000000",
+ DAT_DATAREADY_IN => '0'
+ );
+
+--8x CTRL, 8x STAT
+
+
+ HUB_STAT_GEN <= buf_HUB_STAT_GEN;
+ HUB_STAT_CHANNEL <= buf_HUB_STAT_CHANNEL;
+
+
+
+ HC_STAT_REGS(31 downto 0) <= buf_HUB_STAT_GEN;
+ HC_STAT_REGS(32+2**(MUX_WIDTH-1)*16-1 downto 32) <= buf_HUB_STAT_CHANNEL;
+ HUB_CTRL_GEN <= HC_CTRL_REGS(31 downto 0);
+ HUB_CTRL_CHANNEL <= HC_CTRL_REGS(32+2**(MUX_WIDTH-1)*16-1 downto 32);
+ HUB_CTRL_activepoints <= HC_CTRL_REGS(128+2**(MUX_WIDTH-1)*32-1 downto 128);
+
+ HC_STAT_REGS(8*32-1 downto 96) <= (others => '0');
+
+
+
+ IOBUF_CTRL_GEN <= (others => '0');
+ IOBUF_CTRL_LOCKED <= (others => '0');
+ IOBUF_STAT_CTRL_INIT_BUFFER <= (others => '0');
+ IOBUF_STAT_CTRL_REPLY_BUFFER <= (others => '0');
+
+-- ADDR Name
+-- 0000 HUB_STAT_GEN
+-- 0001 HUB_STAT_CHANNEL1 & HUB_STAT_CHANNEL0
+-- 0010 HUB_STAT_CHANNEL3 & HUB_STAT_CHANNEL2
+-- 1000 HUB_CTRL_GEN
+-- 1001 HUB_CTRL_CHANNEL1 & HUB_CTRL_CHANNEL0
+-- 1010 HUB_CTRL_CHANNEL3 & HUB_CTRL_CHANNEL2
+-- 1100 HUB_CTRL_activepoints0
+-- 1101 HUB_CTRL_activepoints1
+-- 1110 HUB_CTRL_activepoints2
+-- 1111 HUB_CTRL_activepoints3
+
+
end architecture;
architecture trb_net16_hub_control_arch of trb_net16_hub_control is
+
+
begin
+ hub_control : trb_net16_regIO
+ generic map(
+ MY_ADDRESS => x"F001",
+ REGISTER_WIDTH => 32,
+ ADDRESS_WIDTH => 16,
+ ADDRESS_USED_WIDTH => 4,
+ NO_DAT_PORT => '1'
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- Port to API
+ API_DATA_OUT => HC_DATA_IN,
+ API_PACKET_NUM_OUT => HC_PACKET_NUM_IN,
+ API_WRITE_OUT => HC_WRITE_IN,
+ API_FIFO_FULL_IN => HC_FIFO_FULL_OUT,
+ API_SHORT_TRANSFER_OUT => HC_SHORT_TRANSFER_IN,
+ API_DTYPE_OUT => HC_DTYPE_IN,
+ API_ERROR_PATTERN_OUT => HC_ERROR_PATTERN_IN,
+ API_SEND_OUT => HC_SEND_IN,
+ API_TARGET_ADDRESS_OUT => (others => '0'),
+ -- Receiver port
+ API_DATA_IN => HC_DATA_OUT,
+ API_PACKET_NUM_IN => HC_PACKET_NUM_OUT,
+ API_TYP_IN => HC_TYP_OUT,
+ API_DATAREADY_IN => HC_DATAREADY_OUT,
+ API_READ_OUT => HC_READ_IN,
+ -- HC Control port
+ API_RUN_IN => HC_RUN_OUT,
+ API_MY_ADDRESS_OUT => HC_MY_ADDRESS_IN,
+ API_SEQNR_IN => HC_SEQNR_OUT,
+ REGISTERS_IN => HC_STAT_REGS,
+ REGISTERS_OUT => HC_CTRL_REGS,
+ DAT_ADDR_OUT => open,
+ DAT_READ_ENABLE_OUT => open,
+ DAT_WRITE_ENABLE_OUT=> open,
+ DAT_DATA_OUT => open,
+ DAT_DATA_IN => (others => '0'),
+ DAT_DATAREADY_IN => '0'
+ );
+
+
end architecture;
\ No newline at end of file
return integer is
begin
if(POINT < MII_NUMBER*2**(MUX_WIDTH-1)) then
- report integer'image(MII_DEPTH((POINT / 2**(MUX_WIDTH-1))*4 + (POINT mod 2**(MUX_WIDTH-1))));
+ --report integer'image(MII_DEPTH((POINT / 2**(MUX_WIDTH-1))*4 + (POINT mod 2**(MUX_WIDTH-1))));
return MII_DEPTH((POINT / 2**(MUX_WIDTH-1))*4 + (POINT mod 2**(MUX_WIDTH-1)));
elsif(POINT = MII_NUMBER*2**(MUX_WIDTH-1)) then
return HUB_CTRL_DEPTH;
REPLY_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0);
REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
--Status ports (for debugging)
- STAT : out std_logic_vector (31 downto 0);
+ STAT : out std_logic_vector (15 downto 0);
STAT_POINTS_locked : out std_logic_vector (31 downto 0);
STAT_ERRORBITS : out std_logic_vector (31 downto 0);
- CTRL : in std_logic_vector (31 downto 0);
+ CTRL : in std_logic_vector (15 downto 0);
CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1')
);
end entity;
begin
REPLY_HEADER_OUT <= (others => '0');
-STAT(23 downto 0) <= (others => '0');
-STAT(31 downto 24) <= data_counter;
+STAT(7 downto 0) <= (others => '0');
+STAT(15 downto 8) <= data_counter;
STAT_POINTS_locked(POINT_NUMBER-1 downto 0) <= not got_trm when locked = '1' else (others => '0');
STAT_POINTS_locked(31 downto POINT_NUMBER) <= (others => '0');
STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2;
INPUT_IN => INIT_DATAREADY_IN,
RESULT_OUT => init_arbiter_read_out,
ENABLE => not init_locked,
- CTRL => CTRL
+ CTRL => (others => '0')
);
init_arbiter_CLK_EN <= not locked;
INPUT_IN => reply_arbiter_input,
RESULT_OUT => REPLY_MUX_reading,
ENABLE => '1',
- CTRL => CTRL
+ CTRL => (others => '0')
);
reply_arbiter_input <= REPLY_DATAREADY_IN;
-- we have to care to read multiples of four packets from every point
-- release is currently done after first packet of TRM
- gen_reply_point_lock : process(comb_REPLY_POOL_PACKET_NUM, comb_REPLY_POOL_DATAREADY,
+ gen_reply_point_lock : process(comb_REPLY_POOL_PACKET_NUM, comb_REPLY_POOL_DATAREADY, REPLY_DATAREADY_IN,
saved_REPLY_TYPE, comb_REPLY_muxed_PACKET_NUM, comb_REPLY_muxed_DATAREADY,
comb_REPLY_muxed_DATA, buf_REPLY_READ_OUT, REPLY_MUX_reading)
begin
-- current_INT_READ_OUT <= tmp_INT_READ_OUT when endpoint_locked = '0'
-- else final_INT_READ_OUT;
-
+ STAT(15 downto 0) <= (others => '0');
STAT(17 downto 16) <= current_mux_buffer(DATA_WIDTH+1 downto DATA_WIDTH) xor current_mux_packet_number;
+ STAT(31 downto 18) <= (others => '0');
+
process(CLK)
begin
--REGISTER_IN is not registered again
--if DAT-Port is not used, set DAT_DATAREADY_IN to '1'
---APL-Port NOT implemented yet
+
entity trb_net16_regIO is
generic (
MY_ADDRESS : std_logic_vector(15 downto 0) := x"F001";
REGISTER_WIDTH : integer range 32 to 32 := 32;
ADDRESS_WIDTH : integer range 8 to 16 := 16;
- ADDRESS_USED_WIDTH : integer range 1 to 16 := 3;
+ ADDRESS_USED_WIDTH : integer range 1 to 5 := 4;
+ --standard values for output registers
+ RESET_REGISTER_OUT : std_logic_vector(2**(4-1)*32-1 downto 0) :=
+ x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
+ --set to 0 for unused ctrl registers to save resources
+ USED_REGISTER_OUT : std_logic_vector(2**(4-1)-1 downto 0) := "11111111";
+ --set to 0 for each unused bit in a register
+ BITMASK_REGISTER_OUT : std_logic_vector(2**(4-1)*32-1 downto 0) :=
+ x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF";
--no data / address out?
NO_DAT_PORT : std_logic := '0'
);
CLK_EN : in std_logic;
-- Port to API
- API_DATA_OUT: out std_logic_vector (15 downto 0);
- API_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
- API_WRITE_OUT: out std_logic;
- API_FIFO_FULL_IN: in std_logic;
- API_SHORT_TRANSFER_OUT: out std_logic;
- API_DTYPE_OUT: out std_logic_vector (3 downto 0);
- API_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0);
- API_SEND_OUT: out std_logic;
- API_TARGET_ADDRESS_OUT: out std_logic_vector (15 downto 0);
+ API_DATA_OUT : out std_logic_vector (15 downto 0);
+ API_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ API_WRITE_OUT : out std_logic;
+ API_FIFO_FULL_IN : in std_logic;
+ API_SHORT_TRANSFER_OUT : out std_logic;
+ API_DTYPE_OUT : out std_logic_vector (3 downto 0);
+ API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
+ API_SEND_OUT : out std_logic;
+ API_TARGET_ADDRESS_OUT : out std_logic_vector (15 downto 0);
-- Receiver port
- API_DATA_IN: in std_logic_vector (15 downto 0);
- API_PACKET_NUM_IN:in std_logic_vector (1 downto 0);
- API_TYP_IN: in std_logic_vector (2 downto 0);
- API_DATAREADY_IN: in std_logic;
- API_READ_OUT: out std_logic;
+ API_DATA_IN : in std_logic_vector (15 downto 0);
+ API_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ API_TYP_IN : in std_logic_vector (2 downto 0);
+ API_DATAREADY_IN : in std_logic;
+ API_READ_OUT : out std_logic;
-- APL Control port
- API_RUN_IN: in std_logic;
- API_MY_ADDRESS_OUT: out std_logic_vector (15 downto 0);
- API_SEQNR_IN: in std_logic_vector (7 downto 0);
+ API_RUN_IN : in std_logic;
+ API_MY_ADDRESS_OUT : out std_logic_vector (15 downto 0);
+ API_SEQNR_IN : in std_logic_vector (7 downto 0);
--Register in / outside
- REGISTERS_IN : in std_logic_vector(REGISTER_WIDTH*2**(ADDRESS_USED_WIDTH-1)-1 downto 0);
- REGISTERS_OUT : out std_logic_vector(REGISTER_WIDTH*2**(ADDRESS_USED_WIDTH-1)-1 downto 0);
+ REGISTERS_IN : in std_logic_vector(REGISTER_WIDTH*2**(ADDRESS_USED_WIDTH-1)-1 downto 0);
+ REGISTERS_OUT : out std_logic_vector(REGISTER_WIDTH*2**(ADDRESS_USED_WIDTH-1)-1 downto 0);
--following ports only used when no internal register is accessed
DAT_ADDR_OUT : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
--if successful
DAT_DATA_IN : in std_logic_vector(REGISTER_WIDTH-1 downto 0);
DAT_DATAREADY_IN : in std_logic
-
);
end entity;
);
end component;
- type fsm_state_t is (IDLE, HEADER_RECV, REG_READ, REG_WRITE,
+ type fsm_state_t is (IDLE, HEADER_RECV, REG_READ, REG_WRITE, WAIT_FOR_INIT_TRM,
SEND_REPLY_DATA_finish, SEND_REPLY_SHORT_TRANSFER, SEND_REPLY_DATA,
DAT_INT, DAT_WAIT);
signal current_state, next_state : fsm_state_t;
signal next_HDR_F1, next_HDR_F2, next_HDR_F3 : std_logic_vector(15 downto 0);
signal next_Reg_high, saved_Reg_high : std_logic_vector(15 downto 0);
signal next_Reg_low, saved_Reg_low : std_logic_vector(15 downto 0);
- signal next_address, address : std_logic_vector(15 downto 0);
+ signal next_address, address : std_logic_vector(15 downto 0) := x"0000";
signal next_operation, saved_operation : std_logic_vector(3 downto 0);
signal buf_API_READ_OUT, next_API_READ_OUT : std_logic;
signal reg_enable_pattern : std_logic_vector(2**(ADDRESS_USED_WIDTH-1)-1 downto 0);
+ signal state_bits : std_logic_vector(2 downto 0);
+
begin
pattern_gen_inst : trb_net_pattern_gen port map(address(ADDRESS_USED_WIDTH-2 downto 0), reg_enable_pattern);
+
fsm : process(current_state,
API_DATA_IN, API_PACKET_NUM_IN, API_TYP_IN, API_DATAREADY_IN, API_FIFO_FULL_IN, API_RUN_IN,
- HDR_F1, HDR_F2, HDR_F3, address, saved_Reg_high,
+ HDR_F1, HDR_F2, HDR_F3, address, saved_Reg_high, saved_Reg_low, saved_operation,
buf_API_SEND_OUT, buf_API_PACKET_NUM_OUT, buf_API_DATA_OUT, buf_API_SHORT_TRANSFER_OUT,
- REGISTERS_IN, buf_REGISTERS_OUT, reg_enable_pattern
+ REGISTERS_IN, buf_REGISTERS_OUT, reg_enable_pattern,
+ buf_DAT_DATA_OUT, buf_DAT_ADDR_OUT, DAT_DATAREADY_IN, DAT_DATA_IN
)
+ variable regnum : integer range 0 to 2**(ADDRESS_USED_WIDTH-1)-1;
begin
next_state <= current_state;
next_HDR_F1 <= HDR_F1;
next_DAT_READ_ENABLE_OUT <= '0';
next_DAT_WRITE_ENABLE_OUT <= '0';
next_DAT_ADDR_OUT <= buf_DAT_ADDR_OUT;
-
+
+ regnum := conv_integer(address(ADDRESS_USED_WIDTH-2 downto 0));
+
case current_state is
when IDLE =>
next_API_SEND_OUT <= '0';
when "11" =>
next_Reg_low <= API_DATA_IN;
REGISTERS_OUT_write_enable <= reg_enable_pattern;
- next_state <= SEND_REPLY_DATA;
+ next_state <= WAIT_FOR_INIT_TRM;
if or_all(address(ADDRESS_WIDTH-1 downto ADDRESS_USED_WIDTH)) = '1' then
if NO_DAT_PORT = '0' then
next_state <= DAT_INT;
null;
end case;
end if;
+
when REG_READ =>
if API_TYP_IN = TYPE_DAT and API_PACKET_NUM_IN = "01" and API_DATAREADY_IN = '1' then
next_address <= API_DATA_IN;
- next_state <= SEND_REPLY_DATA;
+ next_state <= WAIT_FOR_INIT_TRM;
if or_all(API_DATA_IN(ADDRESS_WIDTH-1 downto ADDRESS_USED_WIDTH)) = '1' then
if NO_DAT_PORT = '0' then
next_state <= DAT_INT;
end if;
end if;
end if;
+
+ when WAIT_FOR_INIT_TRM =>
+ if API_TYP_IN = TYPE_TRM and API_PACKET_NUM_IN = "11" then
+ next_state <= SEND_REPLY_DATA;
+ end if;
+
when SEND_REPLY_DATA =>
next_API_SEND_OUT <= '1';
-
if API_FIFO_FULL_IN = '1' then
next_API_WRITE_OUT <= '0';
else
elsif buf_API_PACKET_NUM_OUT = "01" then
next_API_PACKET_NUM_OUT <= "10";
if address(ADDRESS_USED_WIDTH-1) = '0' then
- next_API_DATA_OUT <= REGISTERS_IN
- (conv_integer(address(ADDRESS_USED_WIDTH-2 downto 0))*REGISTER_WIDTH+31 downto
- conv_integer(address(ADDRESS_USED_WIDTH-2 downto 0))*REGISTER_WIDTH+16);
+ next_API_DATA_OUT <= REGISTERS_IN(regnum*REGISTER_WIDTH+31 downto regnum*REGISTER_WIDTH+16);
else
- next_API_DATA_OUT <= buf_REGISTERS_OUT
- (conv_integer(address(ADDRESS_USED_WIDTH-2 downto 0))*REGISTER_WIDTH+31 downto
- conv_integer(address(ADDRESS_USED_WIDTH-2 downto 0))*REGISTER_WIDTH+16);
+ next_API_DATA_OUT <= buf_REGISTERS_OUT(regnum*REGISTER_WIDTH+31 downto regnum*REGISTER_WIDTH+16);
end if;
elsif buf_API_PACKET_NUM_OUT = "10" then
next_API_PACKET_NUM_OUT <= "11";
if address(ADDRESS_USED_WIDTH-1) = '0' then
- next_API_DATA_OUT <= REGISTERS_IN
- (conv_integer(address(ADDRESS_USED_WIDTH-2 downto 0))*REGISTER_WIDTH+15 downto
- conv_integer(address(ADDRESS_USED_WIDTH-2 downto 0))*REGISTER_WIDTH);
+ next_API_DATA_OUT <= REGISTERS_IN(regnum*REGISTER_WIDTH+15 downto regnum*REGISTER_WIDTH);
else
- next_API_DATA_OUT <= buf_REGISTERS_OUT
- (conv_integer(address(ADDRESS_USED_WIDTH-2 downto 0))*REGISTER_WIDTH+15 downto
- conv_integer(address(ADDRESS_USED_WIDTH-2 downto 0))*REGISTER_WIDTH);
+ next_API_DATA_OUT <= buf_REGISTERS_OUT(regnum*REGISTER_WIDTH+15 downto regnum*REGISTER_WIDTH);
end if;
next_state <= SEND_REPLY_DATA_finish;
end if;
next_API_SEND_OUT <= '0';
next_state <= IDLE;
-
when SEND_REPLY_SHORT_TRANSFER =>
- next_API_SHORT_TRANSFER_OUT <= '1';
- next_API_SEND_OUT <= '1';
- next_state <= SEND_REPLY_DATA_finish;
+ if API_TYP_IN = TYPE_TRM and API_PACKET_NUM_IN = "11" then
+ next_API_SHORT_TRANSFER_OUT <= '1';
+ next_API_SEND_OUT <= '1';
+ next_state <= SEND_REPLY_DATA_finish;
+ end if;
when DAT_INT =>
- next_DAT_DATA_OUT <= saved_Reg_high & saved_Reg_low;
- next_DAT_ADDR_OUT <= address;
- if saved_operation = "1000" then
- next_DAT_READ_ENABLE_OUT <= '1';
- elsif saved_operation = "1001" then
- next_DAT_WRITE_ENABLE_OUT <= '1';
+ if API_TYP_IN = TYPE_TRM and API_PACKET_NUM_IN = "11" then
+ next_DAT_DATA_OUT <= saved_Reg_high & saved_Reg_low;
+ next_DAT_ADDR_OUT <= address;
+ if saved_operation = "1000" then
+ next_DAT_READ_ENABLE_OUT <= '1';
+ elsif saved_operation = "1001" then
+ next_DAT_WRITE_ENABLE_OUT <= '1';
+ end if;
+ next_state <= DAT_WAIT;
end if;
- next_state <= DAT_WAIT;
when DAT_WAIT =>
if DAT_DATAREADY_IN = '1' then
next_API_DATA_OUT <= address;
next_API_SEND_OUT <= '1';
next_API_WRITE_OUT <= '1';
- elsif buf_API_PACKET_NUM_OUT = "01" then
+ end if;
+ if buf_API_PACKET_NUM_OUT = "01" then
next_API_PACKET_NUM_OUT <= "10";
next_API_DATA_OUT <= DAT_DATA_IN(31 downto 16);
next_API_WRITE_OUT <= '1';
end process;
gen_regout : for i in 0 to 2**(ADDRESS_USED_WIDTH-1)-1 generate
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- buf_REGISTERS_OUT((i+1)*REGISTER_WIDTH-1 downto i*REGISTER_WIDTH) <= (others => '0');
- elsif REGISTERS_OUT_write_enable(i) = '1' then
- buf_REGISTERS_OUT((i+1)*REGISTER_WIDTH-1 downto i*REGISTER_WIDTH) <= saved_Reg_high & API_DATA_IN;
- end if;
- end if;
- end process;
+ gen_regoutff1 : for j in i*REGISTER_WIDTH to (i+1)*REGISTER_WIDTH-1 generate
+ gen_regoutff : if USED_REGISTER_OUT(i) = '1' and BITMASK_REGISTER_OUT(j) = '1' generate
+ process(CLK)
+ variable tmp : std_logic_vector(REGISTER_WIDTH-1 downto 0);
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ buf_REGISTERS_OUT(j) <= RESET_REGISTER_OUT(j);
+ elsif REGISTERS_OUT_write_enable(i) = '1' then
+ tmp := saved_Reg_high & API_DATA_IN;
+ buf_REGISTERS_OUT(j) <= tmp(j-i*REGISTER_WIDTH);
+ end if;
+ end if;
+ end process;
+ end generate;
+ gen_regoutnull : if USED_REGISTER_OUT(i) = '0' or BITMASK_REGISTER_OUT(j) = '0' generate
+ buf_REGISTERS_OUT(j) <= RESET_REGISTER_OUT(j);
+ end generate;
+ end generate;
end generate;
API_READ_OUT <= buf_API_READ_OUT;
API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT;
API_DATA_OUT <= buf_API_DATA_OUT;
API_SHORT_TRANSFER_OUT <= buf_API_SHORT_TRANSFER_OUT;
- API_DTYPE_OUT <= (others => '0');
- API_MY_ADDRESS_OUT <= MY_ADDRESS;
- API_ERROR_PATTERN_OUT <= (others => '0');
+ API_DTYPE_OUT <= (others => '0');
+ API_MY_ADDRESS_OUT <= MY_ADDRESS;
+ API_ERROR_PATTERN_OUT <= (others => '0');
API_TARGET_ADDRESS_OUT <= (others => '0');
- DAT_DATA_OUT <= buf_DAT_DATA_OUT;
- DAT_READ_ENABLE_OUT <= buf_DAT_READ_ENABLE_OUT;
- DAT_WRITE_ENABLE_OUT <= buf_DAT_WRITE_ENABLE_OUT;
- DAT_ADDR_OUT <= buf_DAT_ADDR_OUT;
+ DAT_DATA_OUT <= buf_DAT_DATA_OUT;
+ DAT_READ_ENABLE_OUT <= buf_DAT_READ_ENABLE_OUT;
+ DAT_WRITE_ENABLE_OUT <= buf_DAT_WRITE_ENABLE_OUT;
+ DAT_ADDR_OUT <= buf_DAT_ADDR_OUT;
+ REGISTERS_OUT <= buf_REGISTERS_OUT;
- REGISTERS_OUT <= buf_REGISTERS_OUT;
+
+
+ process(current_state)
+ begin
+ case current_state is
+ when IDLE => state_bits <= "000";
+ when HEADER_RECV => state_bits <= "001";
+ when REG_READ => state_bits <= "010";
+ when REG_WRITE => state_bits <= "011";
+ when SEND_REPLY_DATA_finish => state_bits <= "100";
+ when SEND_REPLY_SHORT_TRANSFER => state_bits <= "101";
+ when SEND_REPLY_DATA => state_bits <= "110";
+ when others => state_bits <= "111";
+ end case;
+ end process;
+
end architecture;
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