fix of issue with dca bridge reset signal to get readout of registers working.

diff --git a/src/cri_trbnet_dca_bridge_handler.vhd b/src/cri_trbnet_dca_bridge_handler.vhd
index 0b704ca8440af211dcba5d38e07b4b8e0519168c..d95177d9e310927baf4635a7397781de1b4e1432 100644 (file)
--- a/src/cri_trbnet_dca_bridge_handler.vhd
+++ b/src/cri_trbnet_dca_bridge_handler.vhd
@@ -50,8 +50,6 @@ signal data_in_end_stb    : std_logic;
 type rx_state_t is (IDLE, PAYLOAD, END_PAYLOAD, FINISH);
 signal rx_state : rx_state_t;
 
-signal rst_n_i : std_logic;
-
 begin
 
 -- A register set is needed:
@@ -110,7 +108,7 @@ GEN_AGWB_HANDLER_REAL: if SIMULATION = c_NO generate
     TX_SIZE_i(15 downto  0) => TX_DATA_SIZE,
     TX_SIZE_i_ack           => TX_READ_SIZE_ACK,
 
-    rst_n_i                 => rst_n_i,
+    rst_n_i                 => RST_N,
     clk_sys_i               => CLK_DCA
   );
 end generate;