--- /dev/null
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+
+#################################################################
+# Basic Settings
+#################################################################
+
+SYSCONFIG MCCLK_FREQ = 20;
+
+FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
+FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
+FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+
+#################################################################
+# Clock I/O
+#################################################################
+LOCATE COMP "CLK_GPLL_LEFT" SITE "U25";
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1";
+LOCATE COMP "CLK_PCLK_LEFT" SITE "M4";
+LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20";
+LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";
+LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";
+
+DEFINE PORT GROUP "CLK_group" "CLK*" ;
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
+
+#################################################################
+# Trigger I/O
+#################################################################
+
+#Trigger from fan-out
+LOCATE COMP "TRIGGER_RIGHT" SITE "N24";
+IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25;
+
+LOCATE COMP "TRIGGER_LEFT" SITE "V3";
+IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25;
+
+#################################################################
+# To central FPGA
+#################################################################
+
+LOCATE COMP "FPGA5_COMM_0" SITE "AD4";
+LOCATE COMP "FPGA5_COMM_1" SITE "AE3";
+LOCATE COMP "FPGA5_COMM_2" SITE "AA7";
+LOCATE COMP "FPGA5_COMM_3" SITE "AB7";
+LOCATE COMP "FPGA5_COMM_4" SITE "AD3";
+LOCATE COMP "FPGA5_COMM_5" SITE "AC4";
+LOCATE COMP "FPGA5_COMM_6" SITE "AE2";
+LOCATE COMP "FPGA5_COMM_7" SITE "AF3";
+LOCATE COMP "FPGA5_COMM_8" SITE "AE4";
+LOCATE COMP "FPGA5_COMM_9" SITE "AF4";
+LOCATE COMP "FPGA5_COMM_10" SITE "V10";
+LOCATE COMP "FPGA5_COMM_11" SITE "W10";
+DEFINE PORT GROUP "FPGA5_group" "FPGA5*" ;
+IOBUF GROUP "FPGA5_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+
+LOCATE COMP "TEST_LINE_0" SITE "A5";
+LOCATE COMP "TEST_LINE_1" SITE "A6";
+LOCATE COMP "TEST_LINE_2" SITE "G8";
+LOCATE COMP "TEST_LINE_3" SITE "F9";
+LOCATE COMP "TEST_LINE_4" SITE "D9";
+LOCATE COMP "TEST_LINE_5" SITE "D10";
+LOCATE COMP "TEST_LINE_6" SITE "F10";
+LOCATE COMP "TEST_LINE_7" SITE "E10";
+LOCATE COMP "TEST_LINE_8" SITE "A8";
+LOCATE COMP "TEST_LINE_9" SITE "B8";
+LOCATE COMP "TEST_LINE_10" SITE "G10";
+LOCATE COMP "TEST_LINE_11" SITE "G9";
+LOCATE COMP "TEST_LINE_12" SITE "C9";
+LOCATE COMP "TEST_LINE_13" SITE "C10";
+LOCATE COMP "TEST_LINE_14" SITE "H10";
+LOCATE COMP "TEST_LINE_15" SITE "H11";
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12;
+
+LOCATE COMP "MBS_IN" SITE "P1";
+IOBUF PORT "MBS_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+
+#################################################################
+# Flash ROM and Reboot
+#################################################################
+
+LOCATE COMP "FLASH_CLK" SITE "B12";
+LOCATE COMP "FLASH_CS" SITE "E11";
+LOCATE COMP "FLASH_DIN" SITE "E12";
+LOCATE COMP "FLASH_DOUT" SITE "A12";
+
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+
+LOCATE COMP "PROGRAMN" SITE "B11";
+IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+
+
+#################################################################
+# Misc
+#################################################################
+LOCATE COMP "TEMPSENS" SITE "A13";
+IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+
+#coding of FPGA number
+LOCATE COMP "CODE_LINE_1" SITE "AA20";
+LOCATE COMP "CODE_LINE_0" SITE "Y21";
+IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+
+#terminated differential pair to pads
+#LOCATE COMP "SUPPL" SITE "C14";
+#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
+
+
+#################################################################
+# LED
+#################################################################
+LOCATE COMP "LED_GREEN" SITE "F12";
+LOCATE COMP "LED_ORANGE" SITE "G13";
+LOCATE COMP "LED_RED" SITE "A15";
+LOCATE COMP "LED_YELLOW" SITE "A16";
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12;
+
+
--- /dev/null
+#!/usr/bin/perl
+use warnings;
+use strict;
+use File::Basename;
+use Cwd 'realpath';
+
+my $TOPNAME = 'trb3_periph_billboard';
+my $workdir = './workdir';
+
+my $script_dir = dirname(realpath(__FILE__));
+$workdir = $ARGV[0] if (@ARGV);
+
+die("workdir has to be relative to compile_constraints.pl") if $workdir =~ m/^\//;
+die("workdir must not contain ..") if $workdir =~ m/\.\./;
+$workdir =~ s/(\.\/|\/$)//g; # remove ./ and trailing slash
+$workdir =~ s/\/{2,}/\//g; # remove multiple // in path
+
+my $back = "../" x ($workdir =~ tr/\///);
+$back = './' unless $back;
+
+chdir($script_dir);
+
+unless(-e $workdir) {
+ print "Creating workdir\n";
+ system ("mkdir $workdir");
+}
+
+system("cp ../base/$TOPNAME.lpf $workdir/$TOPNAME.lpf");
+system("cat ".$TOPNAME."_constraints.lpf >> $workdir/$TOPNAME.lpf");
+
+chdir($workdir);
+system ("$back/../../base/linkdesignfiles.sh '$back'");
\ No newline at end of file
--- /dev/null
+#!/usr/bin/perl
+use Data::Dumper;
+use warnings;
+use strict;
+use Term::ANSIColor;
+use File::stat;
+use POSIX;
+
+
+###################################################################################
+#Settings for this project
+my $TOPNAME = "trb3_periph_billboard"; #Name of top-level entity
+my $BasePath = "../base/"; #path to "base" directory
+my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
+my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
+my $synplify_path = '/d/jspc29/lattice/synplify/I-2013.09-SP1/';
+my $lattice_path = '/d/jspc29/lattice/diamond/3.2_x64/';
+###################################################################################
+
+my $btype = 'slave';
+
+system("./compile_constraints.pl");
+
+use FileHandle;
+
+$ENV{'SYNPLIFY'}=$synplify_path;
+$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
+
+
+my $FAMILYNAME="LatticeECP3";
+my $DEVICENAME="LFE3-150EA";
+my $PACKAGE="FPBGA672";
+my $SPEEDGRADE="8";
+
+#generate timestamp
+my $t=time;
+my $fh = new FileHandle(">version.vhd");
+die "could not open file" if (! defined $fh);
+print $fh <<EOF;
+
+--## attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+ constant VERSION_NUMBER_TIME : integer := $t;
+
+end package version;
+EOF
+$fh->close;
+
+system("env| grep LM_");
+my $r = "";
+
+my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
+$r=execute($c, "do_not_exit" );
+
+chdir "workdir";
+
+$fh = new FileHandle("<$TOPNAME".".srr");
+my @a = <$fh>;
+$fh -> close;
+
+
+
+foreach (@a)
+{
+ if(/\@E:/)
+ {
+ print "\n";
+ $c="cat $TOPNAME.srr | grep \"\@E\"";
+ system($c);
+ print "\n\n";
+ exit 129;
+ }
+}
+
+
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
+
+$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
+execute($c);
+
+$c=qq'$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd" | grep -v -e "^WARNING.*has no load"';
+execute($c);
+
+my $tpmap = $TOPNAME . "_map" ;
+
+
+$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+execute($c);
+
+system("rm $TOPNAME.ncd");
+
+$c=qq|$lattice_path/ispfpga/bin/lin/par -w -l 5 -i 6 -t 3 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|;
+execute($c);
+
+# IOR IO Timing Report
+$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+# TWR Timing Report
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -p -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -p -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+chdir "..";
+
+
+sub execute {
+ my ($c, $op) = @_;
+ #print "option: $op \n";
+ $op = "" if(!$op);
+ print color 'blue bold';
+ print "\n\ncommand to execute: $c \n";
+ print color 'reset';
+ $r=system($c);
+ if($r) {
+ print "$!";
+ if($op ne "do_not_exit") {
+ wait;
+ }
+ }
+
+ return $r;
+
+}
+
--- /dev/null
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+
+package config is
+
+
+------------------------------------------------------------------------------
+--Begin of design configuration
+------------------------------------------------------------------------------
+
+ constant USE_DUMMY_READOUT : integer := c_NO; --use slowcontrol for readout, no trigger logic
+
+--Run wih 125 MHz instead of 100 MHz
+ constant USE_125_MHZ : integer := c_NO; --not implemented yet!
+ constant USE_EXTERNALCLOCK : integer := c_NO; --not implemented yet!
+
+--Use sync mode, RX clock for all parts of the FPGA
+ constant USE_RXCLOCK : integer := c_NO; --not implemented yet!
+
+
+--Address settings
+ constant INIT_ADDRESS : std_logic_vector := x"F30a";
+ constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"4b";
+
+------------------------------------------------------------------------------
+--End of design configuration
+------------------------------------------------------------------------------
+
+
+------------------------------------------------------------------------------
+--Select settings by configuration
+------------------------------------------------------------------------------
+ type intlist_t is array(0 to 7) of integer;
+ type hw_info_t is array(0 to 7) of unsigned(31 downto 0);
+ constant HW_INFO_BASE : unsigned(31 downto 0) := x"91009000";
+
+ constant CLOCK_FREQUENCY_ARR : intlist_t := (100,125, others => 0);
+ constant MEDIA_FREQUENCY_ARR : intlist_t := (200,125, others => 0);
+
+ --declare constants, filled in body
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0);
+ constant CLOCK_FREQUENCY : integer;
+ constant MEDIA_FREQUENCY : integer;
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0);
+
+
+end;
+
+package body config is
+--compute correct configuration mode
+
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector(
+ HW_INFO_BASE );
+ constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_125_MHZ);
+ constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_125_MHZ);
+
+
+
+function generateIncludedFeatures return std_logic_vector is
+ variable t : std_logic_vector(63 downto 0);
+begin
+ t := (others => '0');
+ t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 2
+ t(7 downto 0) := x"00"; --std_logic_vector(to_unsigned(USE_HPTDC_FASTMODE_PINOUT*3,8));
+ t(11 downto 8) := x"0"; --std_logic_vector(to_unsigned(USE_DOUBLE_EDGE*2,4));
+ t(15) := '0'; --TDC
+ t(42 downto 42) := "1"; --std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+ t(44 downto 44) := "0"; --std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+ t(51 downto 48) := x"0";--std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+ t(52 downto 52) := std_logic_vector(to_unsigned(USE_125_MHZ,0));
+ t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,0));
+ t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNALCLOCK,0));
+ return t;
+end function;
+
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;
+
+end package body;
\ No newline at end of file
--- /dev/null
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+library work;
+ use work.trb_net_std.all;
+ use work.trb_net_components.all;
+ use work.trb3_components.all;
+
+entity billboard is
+ generic (
+ BLOCK_ADDR_WIDTH : integer range 8 to 11 := 8 -- less than 8 no sensible because of EBR granuality
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ REGIO_IN : in CTRLBUS_RX;
+ REGIO_OUT : out CTRLBUS_TX;
+
+ RDO_IN : in READOUT_RX;
+ RDO_OUT: out READOUT_TX
+ );
+end billboard;
+
+architecture billboard_arch of billboard is
+-- configuration
+ constant MEM_BASE_ADDR_C : std_logic_vector(15 downto 0) := (BLOCK_ADDR_WIDTH=>'1', others =>'0');
+
+-- regio
+ signal regio_addr_rewrite_i, regio_ctrl_rx_i, regio_mem_rx_i : CTRLBUS_RX;
+ signal regio_ctrl_tx_i, regio_mem_tx_i : CTRLBUS_TX;
+ signal regio_mem_rack_delay_i : std_logic;
+
+-- control
+ type TRIGGER_SKIP_T is array(0 to 15) of unsigned(31 downto 0);
+ signal ctrl_trigger_skip_i : TRIGGER_SKIP_T;
+ signal ctrl_time_threshold_i : unsigned(31 downto 0);
+ signal ctrl_enabled_i : std_logic;
+
+ signal trigger_skip_cnt_i : TRIGGER_SKIP_T;
+ signal time_counter_i : unsigned(31 downto 0);
+
+
+-- stats
+ signal stat_frames_sent_i : unsigned(31 downto 0);
+ signal stat_words_sent_i : unsigned(31 downto 0);
+ signal stat_commits_i : unsigned(31 downto 0);
+ signal stat_last_commit_age_i : unsigned(31 downto 0);
+
+-- block handling
+ signal next_rdo_block_i : std_logic;
+ signal next_rdo_length_i : unsigned(BLOCK_ADDR_WIDTH-1 downto 0);
+
+ signal current_rdo_active : std_logic;
+ signal current_rdo_block_i : std_logic;
+ signal current_rdo_length_i : unsigned(BLOCK_ADDR_WIDTH-1 downto 0);
+
+ signal current_regio_block_i : std_logic;
+
+-- memory
+ type MEM_T is array(0 to 2**BLOCK_ADDR_WIDTH) of std_logic_vector(31 downto 0);
+ signal mem_i : MEM_T; -- will be dual port, single clock, output-registered EBR
+
+-- rdo
+ signal rdo_pointer_i : unsigned(BLOCK_ADDR_WIDTH downto 0);
+ type RDO_FSM_T is (IDLE, HEADER, TRANSMIT, FINISH, WAIT_UNTIL_IDLE);
+ signal rdo_fsm_i : RDO_FSM_T;
+ signal rdo_accept_trigger_i : std_logic;
+ signal rdo_mem_data_i : std_logic_vector(31 downto 0);
+
+begin
+ -- handles control and status registers
+ PROC_CTRL_REGIO: process is
+ variable addr : integer;
+ variable trg_addr : integer;
+
+ begin
+ wait until rising_edge(CLK_IN);
+ addr := to_integer(unsigned(regio_ctrl_rx_i.addr(4 downto 0)));
+ trg_addr := to_integer(unsigned(regio_ctrl_rx_i.addr(3 downto 0)));
+
+ regio_ctrl_tx_i.wack <= regio_ctrl_rx_i.write;
+ regio_ctrl_tx_i.rack <= regio_ctrl_rx_i.read;
+ regio_ctrl_tx_i.unknown <= '0';
+ regio_ctrl_tx_i.data <= (others => '0');
+ regio_ctrl_tx_i.nack <= '0';
+
+
+ stat_last_commit_age_i <= stat_last_commit_age_i + 1;
+
+ if RESET_IN='1' then
+ -- as disabled as it gets ;)
+ next_rdo_length_i <= (others => '0');
+ next_rdo_block_i <= '1';
+
+ ctrl_trigger_skip_i <= (others => (others => '1'));
+ ctrl_time_threshold_i <= (others => '0');
+
+ stat_commits_i <= (others => '0');
+ stat_last_commit_age_i <= (others => '0');
+
+ else
+ case addr is
+ when 0 => regio_ctrl_tx_i.data(BLOCK_ADDR_WIDTH-1 downto 0) <= next_rdo_length_i;
+ when 1 => regio_ctrl_tx_i.data <= ctrl_time_threshold_i;
+ when 2 => regio_ctrl_tx_i.data <= stat_frames_sent_i;
+ when 3 => regio_ctrl_tx_i.data <= stat_words_sent_i;
+ when 4 => regio_ctrl_tx_i.data <= stat_commits_i;
+ when 5 => regio_ctrl_tx_i.data <= stat_last_commit_age_i;
+
+ when 16#10# to 16#1f# =>
+ regio_ctrl_tx_i.data <= ctrl_trigger_skip_i(trg_addr);
+
+ when others =>
+ regio_ctrl_tx_i.unknown <= regio_ctrl_rx_i.write or regio_ctrl_rx_i.read;
+ end case;
+
+ if regio_ctrl_rx_i.write='1' then
+ case addr is
+ when 0 => -- commit
+ next_rdo_block_i <= current_regio_block_i;
+ next_rdo_length_i <= regio_ctrl_rx_i.data(BLOCK_ADDR_WIDTH-1 downto 0);
+ stat_last_commit_age_i <= (others => '0');
+ stat_commits_i <= stat_commits_i + 1;
+
+ when 1 =>
+ ctrl_time_threshold_i <= regio_ctrl_rx_i.data;
+
+ when 16#10# to 16#1f# =>
+ ctrl_trigger_skip_i(trg_addr) <= regio_ctrl_rx_i.data;
+
+ when others =>
+ regio_ctrl_tx_i.wack <= '0';
+ regio_ctrl_tx_i.nack <= '1';
+ end case;
+
+ end if;
+ end if;
+ end process;
+ current_regio_block_i <= not next_rdo_block_i;
+
+ PROC_MEM: process is
+ variable rdo_addr_u : unsigned(BLOCK_ADDR_WIDTH downto 0);
+ variable regio_addr, rdo_addr : integer range 0 to 2**BLOCK_ADDR_WIDTH;
+ variable regio_read_ack_delay_v : std_logic;
+ begin
+ wait until rising_edge(CLK_IN);
+
+ rdo_addr_u := rdo_pointer_i;
+ rdo_addr_u(BLOCK_ADDR_WIDTH) := current_rdo_block_i;
+ rdo_addr := to_integer(rdo_addr_u);
+ regio_addr := to_integer(unsigned(current_regio_block_i & regio_mem_rx_i.addr(BLOCK_ADDR_WIDTH-1 downto 0)));
+
+ -- dual read port
+ rdo_mem_data_i <= mem_i(rdo_addr);
+ regio_mem_tx_i.data <= mem_i(regio_addr);
+ regio_mem_rack_delay_i <= regio_mem_rx_i.read;
+
+ regio_mem_tx_i.wack <= '0';
+ -- single write port
+ if regio_mem_rx_i.write='1' then
+ -- is write protected, because rdo is currently reading from block and cell was not transmitted yet?
+ if not(current_rdo_active='1' and current_rdo_block_i=current_regio_block_i and regio_addr <= rdo_addr) then
+ mem_i(regio_addr) <= regio_mem_rx_i.data;
+ regio_mem_tx_i.wack <= '1';
+ end if;
+ end if;
+ end process;
+ regio_mem_tx_i.unknown <= '0';
+ regio_mem_tx_i.nack <= '0';
+ regio_mem_tx_i.rack <= regio_mem_rack_delay_i when rising_edge(CLK_IN);
+
+ PROC_RDO_DECISION: process is
+ variable accept_trigger : std_logic;
+ variable trg_type : integer range 0 to 15;
+ variable new_trigger : std_logic;
+ variable rdo_delay : std_logic;
+ begin
+ wait until rising_edge(CLK_IN);
+
+ accept_trigger := '0';
+ trg_type := to_integer(unsigned(RDO_IN.trg_type));
+ time_counter_i <= time_counter_i + 1;
+ new_trigger := RDO_IN.data_valid and not rdo_delay;
+
+ if RESET_IN='1' then
+ trigger_skip_cnt_i <= (others => (others => '0'));
+ time_counter_i <= (others => '0');
+ else
+ if trigger_skip_cnt_i(trg_type) >= ctrl_trigger_skip_i(trg_type) and trigger_skip_cnt_i(trg_type) /= x"ffffffff" then
+ accept_trigger := '1';
+ elsif new_trigger='1' then
+ trigger_skip_cnt_i(trg_type) <= trigger_skip_cnt_i(trg_type) + 1;
+ end if;
+
+ if time_counter_i >= ctrl_time_threshold_i and ctrl_time_threshold_i /= 0 then
+ accept_trigger := '1';
+ end if;
+
+ if accept_trigger = '1' and new_trigger = '1' then
+ trigger_skip_cnt_i(trg_type) <= (others => '0');
+ time_counter_i <= (others => '0');
+ end if;
+ end if;
+
+ rdo_accept_trigger_i <= accept_trigger;
+ rdo_delay := RDO_IN.data_valid;
+ end process;
+
+
+ PROC_RDO: process is
+ begin
+ wait until rising_edge(CLK_IN);
+
+ -- RDO state machine
+ current_rdo_active <= '1';
+ rdo_pointer_i <= (others => '0'); -- only incremented in TRANSMIT
+
+ RDO_OUT.data <= rdo_mem_data_i;
+ RDO_OUT.data_finished <= '0';
+ RDO_OUT.busy_release <= '0';
+ RDO_OUT.data_write <= '0';
+
+ if RESET_IN = '1' then
+ rdo_fsm_i <= IDLE;
+ current_rdo_active <= '0';
+
+ else
+ case rdo_fsm_i is
+ when IDLE =>
+ current_rdo_active <= '0';
+ current_rdo_block_i <= next_rdo_block_i;
+ current_rdo_length_i <= next_rdo_length_i;
+
+ if RDO_IN.data_valid = '1' then
+ rdo_fsm_i <= HEADER;
+ end if;
+
+ when HEADER =>
+ RDO_OUT.data <= (others => '0');
+ RDO_OUT.data(current_rdo_length_i'HIGH-1 downto 0) <= current_rdo_length_i(current_rdo_length_i'HIGH-1 downto 0);
+ RDO_OUT.data(15 downto 12) <= stat_commits_i(3 downto 0);
+ RDO_OUT.data(30 downto 16) <= stat_last_commit_age_i(31 downto 17);
+ RDO_OUT.data(31) <= rdo_accept_trigger_i;
+ RDO_OUT.data_write <= '1';
+
+ if rdo_accept_trigger_i = '1' and current_rdo_length_i /= 0 then
+ current_rdo_active <= '1';
+ stat_frames_sent_i <= stat_frames_sent_i + 1;
+ rdo_fsm_i <= TRANSMIT;
+ else
+ rdo_fsm_i <= FINISH;
+ end if;
+
+ stat_words_sent_i <= stat_words_sent_i + 1;
+
+ when TRANSMIT =>
+ if rdo_pointer_i+1 = current_rdo_length_i then
+ rdo_fsm_i <= FINISH;
+ end if;
+
+ stat_words_sent_i <= stat_words_sent_i + 1;
+ RDO_OUT.data_write <= '1';
+ rdo_pointer_i <= rdo_pointer_i + 1;
+
+ when FINISH =>
+ RDO_OUT.data_finished <= '1';
+ RDO_OUT.busy_release <= '1';
+ rdo_fsm_i <= WAIT_UNTIL_IDLE;
+
+ when WAIT_UNTIL_IDLE =>
+ if RDO_IN.data_valid = '0' then
+ rdo_fsm_i <= IDLE;
+ end if;
+
+ end case;
+
+ end if;
+ end process;
+
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
+ generic map(
+ PORT_NUMBER => 2,
+ PORT_ADDRESSES => (0 => x"0000", 1 => MEM_BASE_ADDR_C, others => x"0000"),
+ PORT_ADDR_MASK => (0 => 5, 1 => BLOCK_ADDR_WIDTH, others => 0),
+ PORT_MASK_ENABLE => 1
+ )
+ port map(
+ CLK => CLK_IN,
+ RESET => RESET_IN,
+
+ REGIO_RX => regio_addr_rewrite_i,
+ REGIO_TX => REGIO_OUT,
+
+ BUS_RX(0) => regio_ctrl_rx_i,
+ BUS_RX(1) => regio_mem_rx_i,
+ BUS_TX(0) => regio_ctrl_tx_i,
+ BUS_TX(1) => regio_mem_tx_i,
+
+ STAT_DEBUG => open
+ );
+
+ PROC_ADDR_REWRITE: process(REGIO_IN) is
+ begin
+ regio_addr_rewrite_i <= REGIO_IN;
+ regio_addr_rewrite_i.addr(15 downto BLOCK_ADDR_WIDTH+1) <= (others => '0');
+ end process;
+end architecture;
+
\ No newline at end of file
--- /dev/null
+
+# implementation: "workdir"
+impl -add workdir -type fpga
+
+# device options
+set_option -technology LATTICE-ECP3
+set_option -part LFE3_150EA
+set_option -package FN672C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -top_module "trb3_periph_billboard"
+set_option -resource_sharing true
+
+# map options
+set_option -frequency 200
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 0
+#set_option -force_gsr
+set_option -force_gsr false
+set_option -fixgatedclocks false #3
+set_option -fixgeneratedclocks false #3
+set_option -compiler_compatible true
+
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+# set result format/file last
+project -result_format "edif"
+project -result_file "workdir/trb3_periph_billboard.edf"
+
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
+
+####################
+
+
+
+#add_file options
+
+add_file -vhdl -lib work "version.vhd"
+add_file -vhdl -lib work "config.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib "work" "../base/trb3_components.vhd"
+
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
+add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
+
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
+
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
+
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
+
+add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
+add_file -vhdl -lib "work" "../base/cores/pll_in200_out40.vhd"
+#add_file -vhdl -lib "work" "../base/cores/dqsinput_7x5.vhd"
+#add_file -vhdl -lib "work" "../base/cores/dqsinput_5x5.vhd"
+add_file -vhdl -lib "work" "../base/cores/fifo_cdt_200_50.vhd"
+
+add_file -vhdl -lib work "../base/code/mbs_vulom_recv.vhd"
+
+add_file -vhdl -lib "work" "source/billboard.vhd"
+add_file -vhdl -lib "work" "trb3_periph_billboard.vhd"
+add_file -constraint "trb3_periph_billboard.sdc"
--- /dev/null
+# Synopsys, Inc. constraint file
+# /d/jspc22/trb/git/trb3/ADC/trb3_periph_adc.sdc
+# Written on Tue Aug 26 14:58:43 2014
+# by Synplify Pro, F-2012.03-SP1 Scope Editor
+
+#
+# Collections
+#
+
+#
+# Clocks
+#
+define_clock {CLK_PCLK_RIGHT} -name {CLK_PCLK_RIGHT} -freq 200 -clockgroup default_clkgroup_0
+define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -freq 100 -clockgroup default_clkgroup_1
+define_clock {TRIGGER_LEFT} -name {TRIGGER_LEFT} -freq 10 -clockgroup default_clkgroup_2
+define_clock {n:THE_MAIN_PLL.CLKOP} -name {n:THE_MAIN_PLL.CLKOP} -freq 100 -clockgroup default_clkgroup_5
+define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -freq 100 -clockgroup default_clkgroup_6
+define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_rx_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_rx_ch1} -freq 100 -clockgroup default_clkgroup_7
+define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_tx_ch} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_tx_ch} -freq 100 -clockgroup default_clkgroup_8
+
+#
+# Clock to Clock
+#
+
+#
+# Inputs/Outputs
+#
+
+#
+# Registers
+#
+
+#
+# Delay Paths
+#
+
+#
+# Attributes
+#
+
+#
+# I/O Standards
+#
+
+#
+# Compile Points
+#
+
+#
+# Other
+#
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.config.all;
+use work.version.all;
+
+entity trb3_periph_billboard is
+ port(
+ --Clocks
+ CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
+ CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
+ CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+ CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+
+ --Trigger
+ TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
+ TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out
+
+ MBS_IN : in std_logic;
+
+ --Serdes
+ CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible
+ CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems
+ SERDES_INT_TX : out std_logic_vector(3 downto 0);
+ SERDES_INT_RX : in std_logic_vector(3 downto 0);
+
+ --Inter-FPGA Communication
+ FPGA5_COMM : inout std_logic_vector(11 downto 0);
+ --Bit 0/1 input, serial link RX active
+ --Bit 2/3 output, serial link TX active
+ --Flash ROM & Reboot
+ FLASH_CLK : out std_logic;
+ FLASH_CS : out std_logic;
+ FLASH_DIN : out std_logic;
+ FLASH_DOUT : in std_logic;
+ PROGRAMN : out std_logic; --reboot FPGA
+
+ --Misc
+ TEMPSENS : inout std_logic; --Temperature Sensor
+ CODE_LINE : in std_logic_vector(1 downto 0);
+ LED_GREEN : out std_logic;
+ LED_ORANGE : out std_logic;
+ LED_RED : out std_logic;
+ LED_YELLOW : out std_logic;
+ SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
+
+ --Test Connectors
+ TEST_LINE : out std_logic_vector(15 downto 0)
+ );
+ attribute syn_useioff : boolean;
+ --no IO-FF for LEDs relaxes timing constraints
+ attribute syn_useioff of LED_GREEN : signal is false;
+ attribute syn_useioff of LED_ORANGE : signal is false;
+ attribute syn_useioff of LED_RED : signal is false;
+ attribute syn_useioff of LED_YELLOW : signal is false;
+ attribute syn_useioff of TEMPSENS : signal is false;
+ attribute syn_useioff of PROGRAMN : signal is false;
+ attribute syn_useioff of CODE_LINE : signal is false;
+ attribute syn_useioff of TRIGGER_LEFT : signal is false;
+ attribute syn_useioff of TRIGGER_RIGHT : signal is false;
+ attribute syn_useioff of MBS_IN : signal is false;
+ --important signals
+ attribute syn_useioff of FLASH_CLK : signal is true;
+ attribute syn_useioff of FLASH_CS : signal is true;
+ attribute syn_useioff of FLASH_DIN : signal is true;
+ attribute syn_useioff of FLASH_DOUT : signal is true;
+ attribute syn_useioff of FPGA5_COMM : signal is true;
+ attribute syn_useioff of TEST_LINE : signal is true;
+
+
+end entity;
+
+architecture trb3_periph_billboard_arch of trb3_periph_billboard is
+ constant DEVICES : integer := 2;
+
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ --Clock / Reset
+ signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+ signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+ signal clk_125_i : std_logic; -- 125 MHz, via Clock Manager and bypassed PLL
+ signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
+ signal clear_i : std_logic;
+ signal reset_i : std_logic;
+ signal GSR_N : std_logic;
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+
+ --Media Interface
+ signal med_stat_op : std_logic_vector (1*16-1 downto 0);
+ signal med_ctrl_op : std_logic_vector (1*16-1 downto 0);
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
+ signal med_data_out : std_logic_vector (1*16-1 downto 0);
+ signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
+ signal med_dataready_out : std_logic;
+ signal med_read_out : std_logic;
+ signal med_data_in : std_logic_vector (1*16-1 downto 0);
+ signal med_packet_num_in : std_logic_vector (1*3-1 downto 0);
+ signal med_dataready_in : std_logic;
+ signal med_read_in : std_logic;
+
+ --LVL1 channel
+ signal timing_trg_received_i : std_logic;
+
+ --Slow Control channel
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
+ signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+
+ --Timer
+ signal global_time : std_logic_vector(31 downto 0);
+ signal local_time : std_logic_vector(7 downto 0);
+ signal time_since_last_trg : std_logic_vector(31 downto 0);
+ signal timer_ticks : std_logic_vector(1 downto 0);
+
+ signal regio_rx, busmem_rx, regio_bb_rx, regio_mbs_rx : CTRLBUS_RX;
+ signal regio_tx, busmem_tx, regio_bb_tx, regio_mbs_tx : CTRLBUS_TX;
+ signal readout_rx : READOUT_RX;
+ signal readout_tx : readout_tx_array_t(0 to DEVICES-1);
+
+ signal fee_data_finished_in : std_logic_vector(DEVICES-1 downto 0);
+ signal fee_data_write_in : std_logic_vector(DEVICES-1 downto 0);
+ signal fee_trg_release_in : std_logic_vector(DEVICES-1 downto 0);
+ signal fee_data_in : std_logic_vector(32*DEVICES-1 downto 0);
+ signal fee_trg_statusbits_in : std_logic_vector(32*DEVICES-1 downto 0);
+
+ signal mbs_ctrl_i : std_logic_vector(31 downto 0);
+ signal mbs_status_i : std_logic_vector(31 downto 0);
+ signal mbs_trg_sync_i : std_logic;
+ signal mbs_trg_async_i : std_logic;
+
+begin
+---------------------------------------------------------------------------
+-- Reset Generation
+---------------------------------------------------------------------------
+ GSR_N <= pll_lock;
+
+ THE_RESET_HANDLER : trb_net_reset_handler
+ generic map(
+ RESET_DELAY => x"FEEE"
+ )
+ port map(
+ CLEAR_IN => '0', -- reset input (high active, async)
+ CLEAR_N_IN => '1', -- reset input (low active, async)
+ CLK_IN => CLK_PCLK_RIGHT, -- raw master clock, NOT from PLL/DLL!
+ SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock
+ PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
+ RESET_IN => '0', -- general reset signal (SYSCLK)
+ TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
+ CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
+ DEBUG_OUT => open
+ );
+
+
+---------------------------------------------------------------------------
+-- Clock Handling
+---------------------------------------------------------------------------
+ THE_MAIN_PLL : pll_in200_out100
+ port map(
+ CLK => CLK_PCLK_RIGHT,
+ RESET => '0',
+ CLKOP => clk_100_i,
+ CLKOK => clk_200_i,
+ LOCK => pll_lock
+ );
+
+
+
+
+---------------------------------------------------------------------------
+-- The TrbNet media interface (to other FPGA)
+---------------------------------------------------------------------------
+ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
+ generic map(
+ SERDES_NUM => 1, --number of serdes in quad
+ EXT_CLOCK => c_NO, --use internal clock
+ USE_200_MHZ => c_YES, --run on 200 MHz clock
+ USE_125_MHZ => c_NO,
+ USE_CTC => c_NO
+ )
+ port map(
+ CLK => CLK_PCLK_RIGHT,
+ SYSCLK => clk_100_i,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ CLK_EN => '1',
+ --Internal Connection
+ MED_DATA_IN => med_data_out,
+ MED_PACKET_NUM_IN => med_packet_num_out,
+ MED_DATAREADY_IN => med_dataready_out,
+ MED_READ_OUT => med_read_in,
+ MED_DATA_OUT => med_data_in,
+ MED_PACKET_NUM_OUT => med_packet_num_in,
+ MED_DATAREADY_OUT => med_dataready_in,
+ MED_READ_IN => med_read_out,
+ REFCLK2CORE_OUT => open,
+ --SFP Connection
+ SD_RXD_P_IN => SERDES_INT_RX(2),
+ SD_RXD_N_IN => SERDES_INT_RX(3),
+ SD_TXD_P_OUT => SERDES_INT_TX(2),
+ SD_TXD_N_OUT => SERDES_INT_TX(3),
+ SD_REFCLK_P_IN => open,
+ SD_REFCLK_N_IN => open,
+ SD_PRSNT_N_IN => FPGA5_COMM(0),
+ SD_LOS_IN => FPGA5_COMM(0),
+ SD_TXDIS_OUT => FPGA5_COMM(2),
+ -- Status and control port
+ STAT_OP => med_stat_op,
+ CTRL_OP => med_ctrl_op,
+ STAT_DEBUG => med_stat_debug,
+ CTRL_DEBUG => (others => '0')
+ );
+
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+
+ THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
+ generic map(
+ REGIO_NUM_STAT_REGS => 0,
+ REGIO_NUM_CTRL_REGS => 0,
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"ff",
+ BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR,
+ REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
+ REGIO_HARDWARE_VERSION => HARDWARE_INFO,
+ REGIO_INIT_ADDRESS => INIT_ADDRESS,
+ REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+ REGIO_INCLUDED_FEATURES => INCLUDED_FEATURES,
+ CLOCK_FREQUENCY => CLOCK_FREQUENCY,
+ TIMING_TRIGGER_RAW => c_YES,
+ --Configure data handler
+ DATA_INTERFACE_NUMBER => DEVICES,
+ DATA_BUFFER_DEPTH => 10,
+ DATA_BUFFER_WIDTH => 32,
+ DATA_BUFFER_FULL_THRESH => 2**10-511,
+ TRG_RELEASE_AFTER_DATA => c_YES,
+ HEADER_BUFFER_DEPTH => 9,
+ HEADER_BUFFER_FULL_THRESH => 2**9-16
+ )
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+ CLK_EN => '1',
+ MED_DATAREADY_OUT => med_dataready_out,
+ MED_DATA_OUT => med_data_out,
+ MED_PACKET_NUM_OUT => med_packet_num_out,
+ MED_READ_IN => med_read_in,
+ MED_DATAREADY_IN => med_dataready_in,
+ MED_DATA_IN => med_data_in,
+ MED_PACKET_NUM_IN => med_packet_num_in,
+ MED_READ_OUT => med_read_out,
+ MED_STAT_OP_IN => med_stat_op,
+ MED_CTRL_OP_OUT => med_ctrl_op,
+
+ --Timing trigger in
+ TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i,
+ --LVL1 trigger to FEE
+ LVL1_TRG_DATA_VALID_OUT => readout_rx.data_valid,
+ LVL1_VALID_TIMING_TRG_OUT => readout_rx.valid_timing_trg,
+ LVL1_VALID_NOTIMING_TRG_OUT => readout_rx.valid_notiming_trg,
+ LVL1_INVALID_TRG_OUT => readout_rx.invalid_trg,
+
+ LVL1_TRG_TYPE_OUT => readout_rx.trg_type,
+ LVL1_TRG_NUMBER_OUT => readout_rx.trg_number,
+ LVL1_TRG_CODE_OUT => readout_rx.trg_code,
+ LVL1_TRG_INFORMATION_OUT => readout_rx.trg_information,
+ LVL1_INT_TRG_NUMBER_OUT => readout_rx.trg_int_number,
+
+ --Information about trigger handler errors
+ TRG_MULTIPLE_TRG_OUT => readout_rx.trg_multiple,
+ TRG_TIMEOUT_DETECTED_OUT => readout_rx.trg_timeout,
+ TRG_SPURIOUS_TRG_OUT => readout_rx.trg_spurious,
+ TRG_MISSING_TMG_TRG_OUT => readout_rx.trg_missing,
+ TRG_SPIKE_DETECTED_OUT => readout_rx.trg_spike,
+
+ --Response from FEE
+ FEE_TRG_RELEASE_IN => fee_trg_release_in,
+ FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_in,
+ FEE_DATA_IN => fee_data_in,
+ FEE_DATA_WRITE_IN => fee_data_write_in,
+ FEE_DATA_FINISHED_IN => fee_data_finished_in,
+ FEE_DATA_ALMOST_FULL_OUT(0) => readout_rx.buffer_almost_full,
+
+ -- Slow Control Data Port
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
+ REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
+ REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
+ REGIO_STAT_REG_IN => (others => '0'),
+ REGIO_CTRL_REG_OUT => open,
+ REGIO_STAT_STROBE_OUT => open,
+ REGIO_CTRL_STROBE_OUT => open,
+ REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
+ REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+
+ BUS_ADDR_OUT => regio_rx.addr, --regio_addr_out,
+ BUS_READ_ENABLE_OUT => regio_rx.read, --regio_read_enable_out,
+ BUS_WRITE_ENABLE_OUT => regio_rx.write, --regio_write_enable_out,
+ BUS_DATA_OUT => regio_rx.data, --regio_data_out,
+ BUS_DATA_IN => regio_tx.data, --regio_data_in,
+ BUS_DATAREADY_IN => regio_tx.ack, --regio_dataready_in,
+ BUS_NO_MORE_DATA_IN => regio_tx.nack, --regio_no_more_data_in,
+ BUS_WRITE_ACK_IN => regio_tx.ack, --regio_write_ack_in,
+ BUS_UNKNOWN_ADDR_IN => regio_tx.unknown, --regio_unknown_addr_in,
+ BUS_TIMEOUT_OUT => regio_rx.timeout, --regio_timeout_out,
+ ONEWIRE_INOUT => TEMPSENS,
+ ONEWIRE_MONITOR_OUT => open,
+
+ TIME_GLOBAL_OUT => global_time,
+ TIME_LOCAL_OUT => local_time,
+ TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
+ TIME_TICKS_OUT => timer_ticks,
+
+ STAT_DEBUG_IPU => open,
+ STAT_DEBUG_1 => open,
+ STAT_DEBUG_2 => open,
+ STAT_DEBUG_DATA_HANDLER_OUT => open,
+ STAT_DEBUG_IPU_HANDLER_OUT => open,
+ STAT_TRIGGER_OUT => open,
+ CTRL_MPLEX => (others => '0'),
+ IOBUF_CTRL_GEN => (others => '0'),
+ STAT_ONEWIRE => open,
+ STAT_ADDR_DEBUG => open,
+ DEBUG_LVL1_HANDLER_OUT => open
+ );
+
+ timing_trg_received_i <= TRIGGER_LEFT; --TRIGGER_RIGHT; --
+ common_stat_reg <= (others => '0');
+
+gen_rdo_tx : for i in 0 to DEVICES-1 generate
+ fee_trg_release_in(i) <= readout_tx(i).busy_release;
+ fee_trg_statusbits_in(i*32+31 downto i*32) <= readout_tx(i).statusbits;
+ fee_data_in(i*32+31 downto i*32) <= readout_tx(i).data;
+ fee_data_write_in(i) <= readout_tx(i).data_write;
+ fee_data_finished_in(i) <= readout_tx(i).data_finished;
+end generate;
+
+
+ THE_BILLBOARD: entity work.billboard
+ generic map (
+ BLOCK_ADDR_WIDTH => 8
+ ) port map (
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ REGIO_IN => regio_bb_rx,
+ REGIO_OUT => regio_bb_tx,
+ RDO_IN => readout_rx,
+ RDO_OUT => readout_tx(1)
+ );
+
+ THE_MBS_RECV: entity work.mbs_vulom_recv
+ port map (
+ CLK => clk_100_i , -- in std_logic; -- e.g. 100 MHz
+ RESET_IN => reset_i, -- in std_logic; -- could be used after busy_release to make sure entity is in correct state
+
+ --Module inputs
+ MBS_IN => MBS_IN, -- in std_logic; -- raw input
+ CLK_200 => clk_200_i, -- in std_logic; -- internal sampling clock
+
+ --trigger outputs
+ TRG_ASYNC_OUT => open, -- out std_logic; -- asynchronous rising edge, length varying, here=> , -- approx. 110 ns
+ TRG_SYNC_OUT => mbs_trg_sync_i, -- out std_logic; -- sync. to CLK
+
+ --data output for read-out
+ TRIGGER_IN => readout_rx.data_valid, -- in std_logic;
+ DATA_OUT => readout_tx(0).data , -- out std_logic_vector(31 downto 0);
+ WRITE_OUT => readout_tx(0).data_write, -- out std_logic;
+ STATUSBIT_OUT=> readout_tx(0).statusbits, -- out std_logic_vector(31 downto 0) => , --= (others => '0');
+ FINISHED_OUT => readout_tx(0).data_finished, -- out std_logic;
+
+ --Registers / Debug
+ CONTROL_REG_IN => mbs_ctrl_i, -- in std_logic_vector(31 downto 0);
+ STATUS_REG_OUT => mbs_status_i, -- out std_logic_vector(31 downto 0) => , --= (others => '0');
+ HEADER_REG_OUT => open, -- out std_logic_vector(1 downto 0);
+ DEBUG => open -- out std_logic_vector(31 downto 0)
+ );
+ readout_tx(0).busy_release <= readout_tx(0).data_finished;
+
+ THE_MBS_REGIO: process is
+ begin
+ wait until rising_edge(clk_100_i);
+
+ regio_mbs_tx.wack <= regio_mbs_rx.write;
+ regio_mbs_tx.rack <= regio_mbs_rx.read;
+ regio_mbs_tx.nack <= '0';
+ regio_mbs_tx.unknown <= '0';
+
+ if regio_mbs_rx.write='1' then
+ mbs_ctrl_i <= regio_mbs_rx.data;
+ end if;
+
+ regio_mbs_tx.data <= mbs_status_i;
+ end process;
+
+ FPGA5_COMM(10 downto 7) <= "00" & mbs_trg_sync_i & mbs_trg_async_i;
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
+ generic map(
+ PORT_NUMBER => 3,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 1, others => 0),
+ PORT_MASK_ENABLE => 1
+ )
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+
+ REGIO_RX => regio_rx,
+ REGIO_TX => regio_tx,
+
+ BUS_RX(0) => busmem_rx, --Flash
+ BUS_RX(1) => regio_bb_rx, -- Billboard
+ BUS_RX(2) => regio_mbs_rx, -- MBS
+ BUS_TX(0) => busmem_tx,
+ BUS_TX(1) => regio_bb_tx,
+ BUS_TX(2) => regio_mbs_tx,
+
+ STAT_DEBUG => open
+ );
+
+
+---------------------------------------------------------------------------
+-- SPI / Flash
+---------------------------------------------------------------------------
+
+THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload
+ port map(
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+
+ BUS_ADDR_IN => busmem_rx.addr(8 downto 0),
+ BUS_READ_IN => busmem_rx.read,
+ BUS_WRITE_IN => busmem_rx.write,
+ BUS_DATAREADY_OUT => busmem_tx.rack,
+ BUS_WRITE_ACK_OUT => busmem_tx.wack,
+ BUS_UNKNOWN_ADDR_OUT => busmem_tx.unknown,
+ BUS_NO_MORE_DATA_OUT => busmem_tx.nack,
+ BUS_DATA_IN => busmem_rx.data,
+ BUS_DATA_OUT => busmem_tx.data,
+
+ DO_REBOOT_IN => common_ctrl_reg(15),
+ PROGRAMN => PROGRAMN,
+
+ SPI_CS_OUT => FLASH_CS,
+ SPI_SCK_OUT => FLASH_CLK,
+ SPI_SDO_OUT => FLASH_DIN,
+ SPI_SDI_IN => FLASH_DOUT
+ );
+
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+ LED_GREEN <= not med_stat_op(9);
+ LED_ORANGE <= not med_stat_op(10);
+ LED_RED <= MBS_IN;
+ LED_YELLOW <= not med_stat_op(11);
+
+---------------------------------------------------------------------------
+-- Test Connector - Logic Analyser
+---------------------------------------------------------------------------
+
+ TEST_LINE <= (others => '0');
+
+end architecture;
--- /dev/null
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+#################################################################
+# Basic Settings
+#################################################################
+
+SYSCONFIG MCCLK_FREQ = 20;
+
+FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+#FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
+#FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+#FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
+
+#################################################################
+# Reset Nets
+#################################################################
+GSR_NET NET "GSR_N";
+
+MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 20 ns;
+
+#################################################################
+# Locate Serdes and media interfaces
+#################################################################
+
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+REGION "MEDIA_UPLINK" "R102C95D" 13 25;
+LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
+
+MULTICYCLE TO CELL "THE_SPI_RELOAD_THE_SPI_MASTER_THE_SPI_SLIM_tx_sreg_oregio*" 20 ns;
+
+#################################################################
+# Clocks
+#################################################################
jspc29 / trb3.git / commitdiff