gbe update

diff --git a/gbe2_ecp3/tb_gbe_buf.vhd b/gbe2_ecp3/tb_gbe_buf.vhd
index e2d5b8f5d9e5e9faa830b87cbb8d33e70d923a9d..959173bf57a367b1e2e9c09f131ae82575efdfe1 100755 (executable)
--- a/gbe2_ecp3/tb_gbe_buf.vhd
+++ b/gbe2_ecp3/tb_gbe_buf.vhd
@@ -163,9 +163,14 @@ ARCHITECTURE behavior OF testbench IS
        
        signal reply_busy, reply_dataready : std_logic;
        signal reply_data : std_logic_vector(15 downto 0);
+       
+       signal RX_MAC_CLK : std_logic;
+
 
 BEGIN
 
+RX_MAC_CLK <= test_clk;
+
 -- Please check and add your generic clause manually
        uut: trb_net16_gbe_buf
        GENERIC MAP( DO_SIMULATION => 1, USE_125MHZ_EXTCLK => 1 )
@@ -403,6 +408,168 @@ begin
        trigger_loop    := 5000;
        
        wait until rising_edge(test_clk);
+       
+               -- FIRST FRAME UDP - DHCP Offer
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RX_EN_IN <= '1';
+-- dest mac
+       MAC_RXD_IN              <= x"02";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"be";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+-- src mac
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"aa";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"bb";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"cc";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"dd";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"ee";
+       wait until rising_edge(RX_MAC_CLK);
+-- frame type
+       MAC_RXD_IN              <= x"08";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+-- ip headers
+       MAC_RXD_IN              <= x"45";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"10";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"01";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"5a";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"49";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"ff";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"11";  -- udp
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"cc";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"cc";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"c0";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"a8";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"01";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"c0";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"a8";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"02";
+-- udp headers
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"43";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"44";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"02";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"2c";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"aa";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"bb";
+-- dhcp data
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"02";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"01";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"06";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"de";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"ad";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"fa";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"ce";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"c0";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"a8";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"10";
+       
+       for i in 0 to 219 loop
+               wait until rising_edge(RX_MAC_CLK);
+               MAC_RXD_IN              <= x"00";
+       end loop;
+       
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"35";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"01";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"02";
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RXD_IN              <= x"00";
+       wait until rising_edge(RX_MAC_CLK);
+               MAC_RX_EOF_IN <= '1';
+       
+       wait until rising_edge(RX_MAC_CLK);
+       MAC_RX_EN_IN <='0';
+       MAC_RX_EOF_IN <= '0';
+       
+       wait for 1 us;
+       
+       
+       
+       
+       
+       
+       
 
 --     RECEIVE_LOOP: for J in 0 to 1 loop
 --
@@ -430,171 +597,171 @@ begin
 --     end loop RECEIVE_LOOP;
                test_data_len := 20; -- + (1 - J) * 200;
 
-       MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop
-               -- generate a real random byte for CTS
-               UNIFORM(seed1, seed2, rand);
-               int_rand := INTEGER(TRUNC(rand*256.0));
-               cts_random_number := std_logic_vector(to_unsigned(int_rand, cts_random_number'LENGTH));
-       
-               -- IPU transmission starts
-               wait until rising_edge(clk);
-               cts_number_in <= std_logic_vector( trigger_counter );
-               cts_code_in <= cts_random_number;
-               cts_information_in <= x"d2"; -- cts_information_in <= x"de"; -- gk 29.03.10
-               cts_readout_type_in <= x"1";
-               cts_start_readout_in <= '1';
-               wait until rising_edge(clk);
-               wait for 400 ns;
-
-               wait until rising_edge(clk);
-               fee_busy_in <= '1';
-               wait for 300 ns;
-               wait until rising_edge(clk);
-
-               -- ONE DATA TRANSMISSION
-               -- dice a length
-               UNIFORM(seed1, seed2, rand);
-               --test_data_len := INTEGER(TRUNC(rand * 800.0)) + 1;
-               
-               --test_data_len := 9685;
---             test_data_len := 2000; -- + (1 - J) * 200;
-
-               --test_data_len := INTEGER(TRUNC(rand*7500.0)); --20; -- + (1 - J) * 200;
-               test_data_len := 349;
-               
-               -- calculate the needed variables
-               test_loop_len := 2*(test_data_len - 1) + 1;
-               test_hdr_len := to_unsigned( test_data_len + 1, 16 );
-               test_evt_len := to_unsigned( test_data_len, 16 );
-
-               -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21)
-               fee_dataready_in <= '1';
-               fee_data_in <= x"1111"; --x"10" & cts_random_number;
-               wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of first data word
-               fee_dataready_in <= '0';
-               wait until rising_edge(clk); -- BLA
-               wait until rising_edge(clk); -- BLA
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               fee_dataready_in <= '1';
-               fee_data_in <= x"2222"; --std_logic_vector( trigger_counter );
-               wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of second data word
-               fee_dataready_in <= '0';
-               wait until rising_edge(clk); -- BLA
-               wait until rising_edge(clk); -- BLA
-               wait until rising_edge(clk); -- BLA
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               fee_dataready_in <= '1';
-               fee_data_in <= std_logic_vector( test_hdr_len );
-               wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of third data word
-               fee_data_in <= x"3333"; --x"ff21";
-               wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of fourth data word
-               fee_dataready_in <= '0';
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               fee_dataready_in <= '1';
-               fee_data_in <= std_logic_vector( test_evt_len );
-               wait until rising_edge(clk) and (fee_read_out = '1');
-               fee_data_in <= x"ff22"; 
-               wait until rising_edge(clk) and (fee_read_out = '1');
-               fee_dataready_in <= '0';
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-
-               test_data     := x"ffff";
-               MY_DATA_LOOP: for J in 0 to test_loop_len loop
-                       test_data := test_data + 1;
-                       wait until rising_edge(clk) and (fee_read_out = '1');
-                       fee_data_in <= std_logic_vector(test_data); 
---                     if( (test_data MOD 5) = 0 ) then
---                             fee_dataready_in <= '0';
---                             wait until rising_edge(clk);
---                             wait until rising_edge(clk);
---                             wait until rising_edge(clk);
---                             wait until rising_edge(clk);
-----                           wait until rising_edge(clk);
-----                           wait until rising_edge(clk);
-----                           wait until rising_edge(clk);
-----                           wait until rising_edge(clk);
-----                           wait until rising_edge(clk);
-----                           wait until rising_edge(clk);
-----                           wait until rising_edge(clk);
+--     MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop
+--             -- generate a real random byte for CTS
+--             UNIFORM(seed1, seed2, rand);
+--             int_rand := INTEGER(TRUNC(rand*256.0));
+--             cts_random_number := std_logic_vector(to_unsigned(int_rand, cts_random_number'LENGTH));
+--     
+--             -- IPU transmission starts
+--             wait until rising_edge(clk);
+--             cts_number_in <= std_logic_vector( trigger_counter );
+--             cts_code_in <= cts_random_number;
+--             cts_information_in <= x"d2"; -- cts_information_in <= x"de"; -- gk 29.03.10
+--             cts_readout_type_in <= x"1";
+--             cts_start_readout_in <= '1';
+--             wait until rising_edge(clk);
+--             wait for 400 ns;
+--
+--             wait until rising_edge(clk);
+--             fee_busy_in <= '1';
+--             wait for 300 ns;
+--             wait until rising_edge(clk);
+--
+--             -- ONE DATA TRANSMISSION
+--             -- dice a length
+--             UNIFORM(seed1, seed2, rand);
+--             --test_data_len := INTEGER(TRUNC(rand * 800.0)) + 1;
+--             
+--             --test_data_len := 9685;
+----           test_data_len := 2000; -- + (1 - J) * 200;
+--
+--             --test_data_len := INTEGER(TRUNC(rand*7500.0)); --20; -- + (1 - J) * 200;
+--             test_data_len := 349;
+--             
+--             -- calculate the needed variables
+--             test_loop_len := 2*(test_data_len - 1) + 1;
+--             test_hdr_len := to_unsigned( test_data_len + 1, 16 );
+--             test_evt_len := to_unsigned( test_data_len, 16 );
+--
+--             -- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21)
+--             fee_dataready_in <= '1';
+--             fee_data_in <= x"1111"; --x"10" & cts_random_number;
+--             wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of first data word
+--             fee_dataready_in <= '0';
+--             wait until rising_edge(clk); -- BLA
+--             wait until rising_edge(clk); -- BLA
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             fee_dataready_in <= '1';
+--             fee_data_in <= x"2222"; --std_logic_vector( trigger_counter );
+--             wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of second data word
+--             fee_dataready_in <= '0';
+--             wait until rising_edge(clk); -- BLA
+--             wait until rising_edge(clk); -- BLA
+--             wait until rising_edge(clk); -- BLA
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             fee_dataready_in <= '1';
+--             fee_data_in <= std_logic_vector( test_hdr_len );
+--             wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of third data word
+--             fee_data_in <= x"3333"; --x"ff21";
+--             wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of fourth data word
+--             fee_dataready_in <= '0';
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             fee_dataready_in <= '1';
+--             fee_data_in <= std_logic_vector( test_evt_len );
+--             wait until rising_edge(clk) and (fee_read_out = '1');
+--             fee_data_in <= x"ff22"; 
+--             wait until rising_edge(clk) and (fee_read_out = '1');
+--             fee_dataready_in <= '0';
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--
+--             test_data     := x"ffff";
+--             MY_DATA_LOOP: for J in 0 to test_loop_len loop
+--                     test_data := test_data + 1;
+--                     wait until rising_edge(clk) and (fee_read_out = '1');
+--                     fee_data_in <= std_logic_vector(test_data); 
+----                   if( (test_data MOD 5) = 0 ) then
+----                           fee_dataready_in <= '0';
 ----                           wait until rising_edge(clk);
 ----                           wait until rising_edge(clk);
 ----                           wait until rising_edge(clk);
 ----                           wait until rising_edge(clk);
---                             fee_dataready_in <= '1';
---                     else
---                             fee_dataready_in <= '1';
---                     end if;
-                               fee_dataready_in <= '1';
-               end loop MY_DATA_LOOP;
-               -- there must be padding words to get multiple of four LWs
-       
-               wait until rising_edge(clk);
-               fee_dataready_in <= '0';
-               fee_data_in <= x"0000"; 
-
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               fee_busy_in <= '0';
-
-
-               trigger_loop    := trigger_loop + 1;
-               trigger_counter := trigger_counter + 1;
-
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               cts_read_in <= '1';
-               wait until rising_edge(clk);
-               cts_read_in <= '0';
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               cts_start_readout_in <= '0';
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);
-               wait until rising_edge(clk);    
-               
-               test_data_len := test_data_len + 111;
-               
-               --wait for 8 us;
-
-       end loop MY_TRIGGER_LOOP;
+------                         wait until rising_edge(clk);
+------                         wait until rising_edge(clk);
+------                         wait until rising_edge(clk);
+------                         wait until rising_edge(clk);
+------                         wait until rising_edge(clk);
+------                         wait until rising_edge(clk);
+------                         wait until rising_edge(clk);
+------                         wait until rising_edge(clk);
+------                         wait until rising_edge(clk);
+------                         wait until rising_edge(clk);
+------                         wait until rising_edge(clk);
+----                           fee_dataready_in <= '1';
+----                   else
+----                           fee_dataready_in <= '1';
+----                   end if;
+--                             fee_dataready_in <= '1';
+--             end loop MY_DATA_LOOP;
+--             -- there must be padding words to get multiple of four LWs
+--     
+--             wait until rising_edge(clk);
+--             fee_dataready_in <= '0';
+--             fee_data_in <= x"0000"; 
+--
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             fee_busy_in <= '0';
+--
+--
+--             trigger_loop    := trigger_loop + 1;
+--             trigger_counter := trigger_counter + 1;
+--
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             cts_read_in <= '1';
+--             wait until rising_edge(clk);
+--             cts_read_in <= '0';
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             cts_start_readout_in <= '0';
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);
+--             wait until rising_edge(clk);    
+--             
+--             test_data_len := test_data_len + 111;
+--             
+--             --wait for 8 us;
+--
+--     end loop MY_TRIGGER_LOOP;
 
 
 

diff --git a/gbe2_ecp3/trb_net16_gbe_buf.vhd b/gbe2_ecp3/trb_net16_gbe_buf.vhd
index 353a951811d739f7d8b398db5fb15eb56d5cbcb3..e37225a919f0e9854e18cf5b181595f583b2ab2d 100755 (executable)
--- a/gbe2_ecp3/trb_net16_gbe_buf.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_buf.vhd
@@ -534,6 +534,7 @@ signal dbg_select_rec                : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1
 signal dbg_select_sent               : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 signal dbg_select_rec_bytes          : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 signal dbg_select_sent_bytes         : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+signal dbg_select_gen                : std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0);
        
 signal serdes_rx_clk                 : std_logic;
 
@@ -596,6 +597,7 @@ signal mc_ident, mc_size_left : std_logic_vector(15 downto 0);
 signal monitor_tx_packets : std_logic_vector(31 downto 0);
 signal monitor_rx_bytes, monitor_rx_frames, monitor_tx_bytes, monitor_tx_frames : std_logic_vector(31 downto 0);
 signal insert_ttype, additional_hdr : std_logic;
+signal reset_dhcp : std_logic;
 
 begin
 
@@ -609,11 +611,14 @@ fc_ihl_version      <= x"45";
 fc_tos              <= x"10";
 fc_ttl              <= x"ff";
 
+--reset_dhcp <= not GSR_N;
+
 MAIN_CONTROL : trb_net16_gbe_main_control
   port map(
          CLK                   => CLK,
          CLK_125               => serdes_clk_125,
          RESET                 => RESET,
+         RESET_FOR_DHCP => '0', --reset_dhcp,
 
          MC_LINK_OK_OUT        => link_ok,
          MC_RESET_LINK_IN      => '0',
@@ -722,7 +727,8 @@ MAIN_CONTROL : trb_net16_gbe_main_control
          MONITOR_SELECT_REC_OUT                 => dbg_select_rec,
          MONITOR_SELECT_REC_BYTES_OUT   => dbg_select_rec_bytes,
          MONITOR_SELECT_SENT_BYTES_OUT  => dbg_select_sent_bytes,
-         MONITOR_SELECT_SENT_OUT            => dbg_select_sent
+         MONITOR_SELECT_SENT_OUT            => dbg_select_sent,
+         MONITOR_SELECT_GEN_DBG_OUT     => dbg_select_gen
   );
   
   MAKE_RESET_OUT <= make_reset; -- or idle_too_long;
@@ -812,7 +818,8 @@ port map(
        MONITOR_SELECT_REC_IN         => dbg_select_rec,
        MONITOR_SELECT_REC_BYTES_IN   => dbg_select_rec_bytes,
        MONITOR_SELECT_SENT_BYTES_IN  => dbg_select_sent_bytes,
-       MONITOR_SELECT_SENT_IN        => dbg_select_sent
+       MONITOR_SELECT_SENT_IN        => dbg_select_sent,
+       MONITOR_SELECT_GEN_DBG_IN     => dbg_select_gen
 );
 end generate;
 
@@ -828,7 +835,7 @@ port map(
        -- ports for user logic
        RESET                           => RESET,
        CLK                                 => CLK,
-       LINK_OK_IN                      => link_ok,
+       LINK_OK_IN                      => '1', --link_ok,
        --
        WR_EN_IN                        => fc_wr_en,
        DATA_IN                         => fc_data,
@@ -851,7 +858,7 @@ port map(
        FLAGS_OFFSET_IN                 => fc_flags_offset,
        TTL_IN                          => fc_ttl,
        PROTOCOL_IN                     => fc_protocol,
-       FRAME_DELAY_IN                  => frame_delay,
+       FRAME_DELAY_IN                  => (others => '0'),
        
        RD_CLK                          => serdes_clk_125,
        FT_DATA_OUT                     => ft_data,

diff --git a/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd b/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd
index db5f8fa1829e92750866d7d3bbcc8691863289d1..219e3cbac9d3d4a1598699e9723f5f26181f7a45 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd
@@ -95,6 +95,8 @@ signal bank_select : std_logic_vector(3 downto 0);
 signal readout_ctr : std_logic_vector(23 downto 0);
 signal pc_ready_q : std_logic;
 signal sf_afull_q : std_logic;
+signal sf_aempty : std_logic;
+signal rec_state, load_state : std_logic_vector(3 downto 0);
 
 begin
 
@@ -118,6 +120,7 @@ begin
        case (save_current_state) is
        
                when IDLE =>
+                       rec_state <= x"1";
                        if (CTS_START_READOUT_IN = '1') then
                                save_next_state <= SAVE_EVT_ADDR;
                        else
@@ -125,9 +128,11 @@ begin
                        end if;
                        
                when SAVE_EVT_ADDR =>
+                       rec_state <= x"2";
                        save_next_state <= WAIT_FOR_DATA;
                        
                when WAIT_FOR_DATA =>
+                       rec_state <= x"3";
                        if (FEE_BUSY_IN = '1') then
                                save_next_state <= SAVE_DATA;
                        else
@@ -135,6 +140,7 @@ begin
                        end if;  
                
                when SAVE_DATA =>
+                       rec_state <= x"4";
                        if (FEE_BUSY_IN = '0') then
                                save_next_state <= TERMINATE;
                        else
@@ -142,6 +148,7 @@ begin
                        end if;
                
                when TERMINATE =>
+                       rec_state <= x"5";
                        if (CTS_READ_IN = '1') then
                                save_next_state <= CLOSE;
                        else
@@ -149,6 +156,7 @@ begin
                        end if;
                        
                when CLOSE => 
+                       rec_state <= x"6";
                        if (CTS_START_READOUT_IN = '0') then
                                save_next_state <= ADD_SUBSUB1;
                        else
@@ -156,18 +164,23 @@ begin
                        end if;
                
                when ADD_SUBSUB1 =>
+                       rec_state <= x"7";
                        save_next_state <= ADD_SUBSUB2;
                
                when ADD_SUBSUB2 =>
+                       rec_state <= x"8";
                        save_next_state <= ADD_SUBSUB3;
                        
                when ADD_SUBSUB3 =>
+                       rec_state <= x"9";
                        save_next_state <= ADD_SUBSUB4;
                        
                when ADD_SUBSUB4 =>
+                       rec_state <= x"a";
                        save_next_state <= CLEANUP;
                        
                when CLEANUP =>
+                       rec_state <= x"b";
                        save_next_state <= IDLE;
                 
        end case;
@@ -353,8 +366,8 @@ port map(
        --WCNT              => open,
        --RCNT              => open,
        Empty             => sf_empty,
-       AlmostEmpty       => open,
-       Full              => open, --sf_afull  -- WARNING, JUST FOR DEBUG
+       AlmostEmpty       => sf_aempty,
+       Full              => sf_full,  -- WARNING, JUST FOR DEBUG
        AlmostFull        => sf_afull
 );
 
@@ -400,6 +413,7 @@ begin
        case (load_current_state) is
 
                when IDLE =>
+                       load_state <= x"1";
                        if (saved_events_ctr /= loaded_events_ctr) then
                                load_next_state <= REMOVE;
                        else
@@ -407,6 +421,7 @@ begin
                        end if;
                
                when REMOVE =>
+                       load_state <= x"2";
                        if (loaded_bytes_ctr = x"0008") then
                                load_next_state <= WAIT_ONE;
                        else
@@ -414,12 +429,15 @@ begin
                        end if;
                        
                when WAIT_ONE =>
+                       load_state <= x"3";
                        load_next_state <= DECIDE;
                
                when DECIDE =>
+                       load_state <= x"4";
                        load_next_state <= WAIT_FOR_LOAD;
                        
                when WAIT_FOR_LOAD =>
+                       load_state <= x"5";
                        if (PC_READY_IN = '1') then
                                load_next_state <= LOAD;
                        else
@@ -427,6 +445,7 @@ begin
                        end if;
                
                when LOAD =>
+                       load_state <= x"6";
                        if (sf_eod = '1') then
                                load_next_state <= CLOSE;
                        else
@@ -434,6 +453,7 @@ begin
                        end if;
                
                when CLOSE =>
+                       load_state <= x"7";
                        load_next_state <= IDLE;
                
                when others => load_next_state <= IDLE;
@@ -685,7 +705,20 @@ PC_TRIGGER_TYPE_OUT <= trigger_type;
 
 PC_PADDING_OUT <= '0'; --padding_needed; not used anymore
 
-DEBUG_OUT <= (others => '0');
+
+process(CLK_GBE)
+begin
+       if rising_edge(CLK_GBE) then
+               DEBUG_OUT(3 downto 0) <= rec_state;
+               DEBUG_OUT(7 downto 4) <= load_state;
+               DEBUG_OUT(8) <= sf_empty;
+               DEBUG_OUT(9) <= sf_aempty;
+               DEBUG_OUT(10) <= sf_full;
+               DEBUG_OUT(11) <= sf_afull;
+       end if;
+end process;
+
+DEBUG_OUT(383 downto 12) <= (others => '0');
 MONITOR_OUT <= (others => '0');
 
 end architecture RTL;

diff --git a/gbe2_ecp3/trb_net16_gbe_main_control.vhd b/gbe2_ecp3/trb_net16_gbe_main_control.vhd
index 8c68426a427e411dc33a52a564699d3b6f4f323c..3601893b118e8e183ed231a4f9fa4d212c659776 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_main_control.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_main_control.vhd
@@ -23,6 +23,7 @@ port (
        CLK                     : in    std_logic;  -- system clock
        CLK_125                 : in    std_logic;
        RESET                   : in    std_logic;
+       RESET_FOR_DHCP : in std_logic;
 
        MC_LINK_OK_OUT          : out   std_logic;
        MC_RESET_LINK_IN        : in    std_logic;
@@ -133,7 +134,8 @@ port (
        MONITOR_SELECT_REC_OUT        : out     std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
        MONITOR_SELECT_REC_BYTES_OUT  : out     std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
        MONITOR_SELECT_SENT_BYTES_OUT : out     std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-       MONITOR_SELECT_SENT_OUT       : out     std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0)
+       MONITOR_SELECT_SENT_OUT       : out     std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+       MONITOR_SELECT_GEN_DBG_OUT    : out     std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0)
 );
 end trb_net16_gbe_main_control;
 
@@ -237,6 +239,7 @@ protocol_selector : trb_net16_gbe_protocol_selector
 port map(
        CLK                     => CLK,
        RESET                   => RESET,
+       RESET_FOR_DHCP => RESET_FOR_DHCP,
        
        PS_DATA_IN              => rc_data_local, -- RC_DATA_IN,
        PS_WR_EN_IN             => ps_wr_en_qq, --ps_wr_en,
@@ -327,11 +330,11 @@ port map(
        STAT_DATA_RDY_IN   => stat_rdy,
        STAT_DATA_ACK_OUT  => stat_ack,
 
-
        MONITOR_SELECT_REC_OUT        => MONITOR_SELECT_REC_OUT,        
        MONITOR_SELECT_REC_BYTES_OUT  => MONITOR_SELECT_REC_BYTES_OUT,  
        MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT, 
-       MONITOR_SELECT_SENT_OUT       => MONITOR_SELECT_SENT_OUT
+       MONITOR_SELECT_SENT_OUT       => MONITOR_SELECT_SENT_OUT,
+       MONITOR_SELECT_GEN_DBG_OUT    => MONITOR_SELECT_GEN_DBG_OUT
 );
 
 TC_DATA_OUT <= tc_data;
@@ -575,11 +578,12 @@ end process;
 LINK_STATE_MACHINE_PROC : process(CLK)
 begin
        if rising_edge(CLK) then
-               if (RESET = '1') then
+               --if (RESET = '1') then
+               if (RESET_FOR_DHCP = '1') then
                        if (g_SIMULATE = 0) then
                                link_current_state <= INACTIVE;
                        else
-                               link_current_state <= ACTIVE; --GET_ADDRESS; --ACTIVE;
+                               link_current_state <= FINALIZE; --ACTIVE; --GET_ADDRESS; --ACTIVE;
                        end if;
                else
                        link_current_state <= link_next_state;
@@ -667,7 +671,8 @@ end process LINK_STATE_MACHINE;
 LINK_OK_CTR_PROC : process(CLK)
 begin
        if rising_edge(CLK) then
-               if (RESET = '1') or (link_current_state /= TIMEOUT) then
+               --if (RESET = '1') or (link_current_state /= TIMEOUT) then
+               if (RESET_FOR_DHCP = '1') or (link_current_state /= TIMEOUT) then
                        link_ok_timeout_ctr <= (others => '0');
                elsif (link_current_state = TIMEOUT) then
                        link_ok_timeout_ctr <= link_ok_timeout_ctr + x"1";
@@ -692,7 +697,8 @@ end process LINK_OK_CTR_PROC;
 WAIT_CTR_PROC : process(CLK)
 begin
        if rising_edge(CLK) then
-               if (RESET = '1') or (link_current_state = INACTIVE) then
+               --if (RESET = '1') or (link_current_state = INACTIVE) then
+               if (RESET_FOR_DHCP = '1') or (link_current_state = INACTIVE) then
                        wait_ctr <= (others => '0');
                elsif (link_current_state = WAIT_FOR_BOOT) then
                        wait_ctr <= wait_ctr + x"1";
@@ -738,7 +744,7 @@ g_MY_MAC <= unique_id(31 downto 8) & x"be0002";
 TSMAC_CONTROLLER : trb_net16_gbe_mac_control
 port map(
        CLK                             => CLK,
-       RESET                   => RESET,
+       RESET                   => RESET_FOR_DHCP, --RESET,
 
 -- signals to/from main controller
        MC_TSMAC_READY_OUT      => tsm_ready,
@@ -919,6 +925,4 @@ TSM_HWRITE_N_OUT  <= tsm_hwrite_n;
 
 
 
-end trb_net16_gbe_main_control;
-
-
+end trb_net16_gbe_main_control;
\ No newline at end of file

diff --git a/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd b/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd
index b8b5920038ce88e520db2c8abeb008ed6daa8643..01ddb3e4227b59d57ef840eae219da6ae62a2604 100755 (executable)
--- a/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd
@@ -252,7 +252,7 @@ constructMachine : process(constructCurrentState, PC_START_OF_SUB_IN, PC_WR_EN_I
 begin
        case constructCurrentState is
                when CIDLE =>
-                       constr_state <= x"0";
+                       constr_state <= x"1";
                        --if( PC_WR_EN_IN = '1' ) then
                        -- gk 04.12.10
                        if (PC_START_OF_SUB_IN = '1') then
@@ -262,21 +262,21 @@ begin
                                constructNextState <= CIDLE;
                        end if;
                when SAVE_DATA =>
-                       constr_state <= x"1";
+                       constr_state <= x"2";
                        if( PC_END_OF_DATA_IN = '1') then
                                constructNextState <= WAIT_FOR_LOAD;
                        else
                                constructNextState <= SAVE_DATA;
                        end if;
                when WAIT_FOR_LOAD =>
-                       constr_state <= x"2";
+                       constr_state <= x"3";
                        if( (df_empty = '1') and (loadCurrentState = LIDLE) ) then -- waits until the whole packet is transmitted
                                constructNextState <= CIDLE;
                        else
                                constructNextState <= WAIT_FOR_LOAD;
                        end if;
                when others =>
-                       constr_state <= x"f";
+                       constr_state <= x"4";
                        constructNextState <= CIDLE;
        end case;
 end process constructMachine;
@@ -1046,6 +1046,18 @@ TC_FLAGS_OFFSET_OUT           <= fc_flags_offset;
 TC_SOD_OUT                    <= fc_sod;
 TC_EOD_OUT                    <= fc_eod;
 
-DEBUG_OUT                     <= debug;
+process(CLK)
+begin
+       if rising_edge(CLK) then
+               DEBUG_OUT(3 downto 0) <= constr_state;
+               DEBUG_OUT(7 downto 4) <= load_state;
+               DEBUG_OUT(11 downto 8) <= save_state;
+               DEBUG_OUT(12) <= df_full;
+               DEBUG_OUT(13) <= df_empty;
+               DEBUG_OUT(14) <= shf_full;
+               DEBUG_OUT(15) <= shf_empty;
+       end if;
+end process;
+DEBUG_OUT(63 downto 16) <= (others => '0');
 
 end trb_net16_gbe_packet_constr;
\ No newline at end of file

diff --git a/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd b/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd
index b9358220c875dda39761a80a004abb455fca8f97..bc8386ca8049994ff169f0440e6f14a7e0df834b 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd
@@ -21,6 +21,7 @@ entity trb_net16_gbe_protocol_selector is
 port (
        CLK                     : in    std_logic;  -- system clock
        RESET                   : in    std_logic;
+       RESET_FOR_DHCP : in std_logic;
 
 -- signals to/from main controller
        PS_DATA_IN              : in    std_logic_vector(8 downto 0); 
@@ -118,7 +119,8 @@ port (
        MONITOR_SELECT_REC_OUT        : out     std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
        MONITOR_SELECT_REC_BYTES_OUT  : out     std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
        MONITOR_SELECT_SENT_BYTES_OUT : out     std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-       MONITOR_SELECT_SENT_OUT       : out     std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0) 
+       MONITOR_SELECT_SENT_OUT       : out     std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+       MONITOR_SELECT_GEN_DBG_OUT    : out     std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0)
 );
 end trb_net16_gbe_protocol_selector;
 
@@ -223,7 +225,7 @@ port map (
        STAT_DATA_ACK_IN                => stat_ack(0),
        RECEIVED_FRAMES_OUT             => open, --RECEIVED_FRAMES_OUT(1 * 16 - 1 downto 0 * 16),
        SENT_FRAMES_OUT                 => open, --SENT_FRAMES_OUT(1 * 16 - 1 downto 0 * 16),
-       DEBUG_OUT                               => open --PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32)
+       DEBUG_OUT                               => MONITOR_SELECT_GEN_DBG_OUT(1 * 64 - 1 downto 0 * 64) --PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32)
 -- END OF INTERFACE 
 );
 
@@ -233,7 +235,7 @@ generic map( STAT_ADDRESS_BASE => 0
 )
 port map (
        CLK                                 => CLK,
-       RESET                           => RESET,
+       RESET                           => RESET_FOR_DHCP, --RESET,
        
 -- INTERFACE   
        PS_DATA_IN                      => PS_DATA_IN,
@@ -275,7 +277,7 @@ port map (
        DHCP_START_IN               => DHCP_START_IN,
        DHCP_DONE_OUT               => DHCP_DONE_OUT,
         
-       DEBUG_OUT                       => open --PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32)
+       DEBUG_OUT                       => MONITOR_SELECT_GEN_DBG_OUT(2 * 64 - 1 downto 1 * 64) --PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32)
  );
 
  --protocol No. 3 Ping
@@ -321,7 +323,7 @@ port map (
        STAT_DATA_ACK_IN        => '0',
        RECEIVED_FRAMES_OUT     => open,
        SENT_FRAMES_OUT             => open,
-       DEBUG_OUT                       => open
+       DEBUG_OUT                               => MONITOR_SELECT_GEN_DBG_OUT(5 * 64 - 1 downto 4 * 64)
 -- END OF INTERFACE
 );
 
@@ -365,6 +367,8 @@ port map (
        STAT_ADDR_OUT           => stat_addr(3 * 8 - 1 downto 2 * 8),
        STAT_DATA_RDY_OUT       => stat_rdy(2),
        STAT_DATA_ACK_IN        => stat_ack(2),
+       
+       DEBUG_OUT                               => MONITOR_SELECT_GEN_DBG_OUT(3 * 64 - 1 downto 2 * 64),
        -- END OF INTERFACE
        
        GSC_CLK_IN              => GSC_CLK_IN,
@@ -424,6 +428,8 @@ port map (
        STAT_ADDR_OUT                           => stat_addr(4 * 8 - 1 downto 3 * 8),
        STAT_DATA_RDY_OUT                       => stat_rdy(3),
        STAT_DATA_ACK_IN                        => stat_ack(3),
+       
+       DEBUG_OUT                               => MONITOR_SELECT_GEN_DBG_OUT(4 * 64 - 1 downto 3 * 64),
 -- END OF INTERFACE
 
        TRANSMITTER_BUSY_IN         => '0',

diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd
index 6e48567925e6db5a51469b81e683fb54e6cf147a..42917529c064dfe33ebae19db27ee810419d07ef 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd
@@ -57,7 +57,7 @@ port (
 -- END OF INTERFACE
 
 -- debug
-       DEBUG_OUT               : out   std_logic_vector(31 downto 0)
+       DEBUG_OUT               : out   std_logic_vector(63 downto 0)
 );
 end trb_net16_gbe_response_constructor_ARP;
 

diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd
index 3a3a0f9b988248e9c47d82453c42c1d48e766810..b8af231bdf82765bfe37b646bd2af3bf6885e337 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd
@@ -60,7 +60,7 @@ port (
        DHCP_DONE_OUT           : out   std_logic;
 
 -- debug
-       DEBUG_OUT               : out   std_logic_vector(31 downto 0)
+       DEBUG_OUT               : out   std_logic_vector(63 downto 0)
 );
 end trb_net16_gbe_response_constructor_DHCP;
 

diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd
index 64299ef31783710f3318a94a7fd9d625a2ff9258..9cad4b478a6b6b021cf8f06672a4b5043a8c7799 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd
@@ -59,7 +59,7 @@ port (
 -- END OF INTERFACE
 
 -- debug
-       DEBUG_OUT               : out   std_logic_vector(31 downto 0)
+       DEBUG_OUT               : out   std_logic_vector(63 downto 0)
 );
 end trb_net16_gbe_response_constructor_Ping;
 

diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd
index 70883c79e14d0e8ef382f7d7b22a9df949fe1e8f..bc3b5257682f93e2b7cb6394f5729beba8af77b9 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd
@@ -50,6 +50,8 @@ generic ( STAT_ADDRESS_BASE : integer := 0
                STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
                STAT_DATA_RDY_OUT : out std_logic;
                STAT_DATA_ACK_IN  : in std_logic;
+               
+               DEBUG_OUT                 : out std_logic_vector(63 downto 0);
        -- END OF INTERFACE
        
        -- protocol specific ports
@@ -505,7 +507,7 @@ begin
                        end if;
                        
                when WAIT_FOR_HUB =>
-                       state <= x"5";
+                       state <= x"2";
                        if (GSC_INIT_READ_IN = '1') then
                                dissect_next_state <= LOAD_TO_HUB;
                        else
@@ -525,7 +527,7 @@ begin
                        end if; 
                        
                when WAIT_FOR_RESPONSE =>
-                       state <= x"6";
+                       state <= x"4";
                        if (GSC_REPLY_DATAREADY_IN = '1') then
                                dissect_next_state <= SAVE_RESPONSE;
                        else
@@ -533,7 +535,7 @@ begin
                        end if;
                        
                when SAVE_RESPONSE =>
-                       state <= x"7";
+                       state <= x"5";
                        if (GSC_REPLY_DATAREADY_IN = '0' and GSC_BUSY_IN = '0') then
                                if (too_much_data = '0') then
                                        dissect_next_state <= WAIT_FOR_LOAD;
@@ -545,7 +547,7 @@ begin
                        end if;                 
                        
                when WAIT_FOR_LOAD =>
-                       state <= x"8";
+                       state <= x"6";
                        if (PS_SELECTED_IN = '1') then
                                dissect_next_state <= LOAD_FRAME;
                        else
@@ -553,7 +555,7 @@ begin
                        end if;
                        
                when LOAD_FRAME =>
-                       state <= x"9";
+                       state <= x"7";
                        if (tx_loaded_ctr = tx_data_ctr) then
                                dissect_next_state <= CLEANUP;
                        else
@@ -561,7 +563,7 @@ begin
                        end if;
                
                when CLEANUP =>
-                       state <= x"b";
+                       state <= x"8";
                        dissect_next_state <= IDLE;
        
        end case;
@@ -592,6 +594,17 @@ end process DISSECT_MACHINE;
 
 
 -- monitoring
+
+
+DEBUG_OUT(0) <= rx_full;
+DEBUG_OUT(1) <= rx_empty;
+DEBUG_OUT(2) <= tx_full;
+DEBUG_OUT(3) <= tx_empty;
+
+DEBUG_OUT(7 downto 4) <= state;
+
+DEBUG_OUT(63 downto 8) <= (others => '0');
+
 process(CLK)
 begin
        if rising_edge(CLK) then

diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd
index 49de078c44c8330fa6f6389e2e5d42e1aabe7eb3..aa1c942db9f6263eaf803134038a9d55a2509370 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd
@@ -47,6 +47,8 @@ port (
        STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
        STAT_DATA_RDY_OUT : out std_logic;
        STAT_DATA_ACK_IN  : in std_logic;
+       
+       DEBUG_OUT                 : out std_logic_vector(63 downto 0);
 -- END OF INTERFACE
 
        TRANSMITTER_BUSY_IN         : in    std_logic;
@@ -141,6 +143,9 @@ signal loaded_bytes : std_logic_vector(15 downto 0);
 signal sent_packets : std_logic_vector(15 downto 0);
 
 signal mon_sent_frames, mon_sent_bytes : std_logic_vector(31 downto 0);
+signal ipu_dbg : std_logic_vector(383 downto 0);
+signal constr_dbg : std_logic_vector(63 downto 0);
+
 
 begin
 
@@ -238,7 +243,7 @@ port map(
        PC_TRIGGER_TYPE_OUT      => pc_trig_type,
        PC_PADDING_OUT                   => pc_padding,
        MONITOR_OUT              => open,
-       DEBUG_OUT                => open
+       DEBUG_OUT                => ipu_dbg
 );
 
 --TODO: add missing values from setup
@@ -269,7 +274,7 @@ port map(
        TC_DATA_OUT                             => tc_data,
        TC_EVENT_SIZE_OUT               => tc_size,
        TC_SOD_OUT                              => tc_sod,
-       DEBUG_OUT                               => open
+       DEBUG_OUT                               => constr_dbg
 );
 
 tc_rd_en <= '1' when PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1' else '0'; 
@@ -410,6 +415,9 @@ MONITOR_SELECT_SENT_BYTES_OUT <= mon_sent_bytes;
 MONITOR_SELECT_REC_BYTES_OUT  <= (others => '0');
 MONITOR_SELECT_REC_OUT        <= (others => '0');
 
+DEBUG_OUT(31 downto 0) <= ipu_dbg(31 downto 0);
+DEBUG_OUT(63 downto 32) <= constr_dbg(31 downto 0);
+
 end trb_net16_gbe_response_constructor_TrbNetData;
 
 

diff --git a/gbe2_ecp3/trb_net16_gbe_setup.vhd b/gbe2_ecp3/trb_net16_gbe_setup.vhd
index f6ef4600251bea6b38a5a2286669d017ec7e61d0..9030b3a58357e0d7473c9228085e5a35755c1ff5 100644 (file)
--- a/gbe2_ecp3/trb_net16_gbe_setup.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_setup.vhd
@@ -49,7 +49,8 @@ port(
        MONITOR_SELECT_REC_IN         : in      std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
        MONITOR_SELECT_REC_BYTES_IN   : in      std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
        MONITOR_SELECT_SENT_BYTES_IN  : in      std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-       MONITOR_SELECT_SENT_IN        : in      std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0)
+       MONITOR_SELECT_SENT_IN        : in      std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+       MONITOR_SELECT_GEN_DBG_IN     : in      std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0)
 );
 end entity;
 
@@ -286,7 +287,11 @@ begin
                                        data_out <= MONITOR_SELECT_SENT_IN(3 * 32 - 1 downto 2 * 32);
                                when x"a3" =>
                                        data_out <= MONITOR_SELECT_SENT_BYTES_IN(3 * 32 - 1 downto 2 * 32);
-                                       
+                               when x"a4" =>
+                                       data_out <= MONITOR_SELECT_GEN_DBG_IN(3 * 64 - 1 - 32 downto 2 * 64);
+                               when x"a5" =>
+                                       data_out <= MONITOR_SELECT_GEN_DBG_IN(3 * 64 - 1 downto 2 * 64 + 32);
+                                               
                                -- TrbnetData
                                when x"b0" =>
                                        data_out <= MONITOR_SELECT_REC_IN(4 * 32 - 1 downto 3 * 32);
@@ -296,7 +301,18 @@ begin
                                        data_out <= MONITOR_SELECT_SENT_IN(4 * 32 - 1 downto 3 * 32);
                                when x"b3" =>
                                        data_out <= MONITOR_SELECT_SENT_BYTES_IN(4 * 32 - 1 downto 3 * 32);
-
+                               when x"b4" =>
+                                       data_out <= MONITOR_SELECT_GEN_DBG_IN(4 * 64 - 1 - 32 downto 3 * 64);
+                               when x"b5" =>
+                                       data_out <= MONITOR_SELECT_GEN_DBG_IN(4 * 64 - 1 downto 3 * 64 + 32);
+                               
+                               -- for older network monitors   
+                               when x"f3" =>
+                                       data_out <= MONITOR_TX_BYTES_IN;
+                                       
+                               when x"f4" =>
+                                       data_out <= MONITOR_TX_FRAMES_IN;
+                                       
                                when others =>
                                        data_out <= (others => '0');
                        end case;

diff --git a/gbe2_ecp3/trb_net_gbe_components.vhd b/gbe2_ecp3/trb_net_gbe_components.vhd
index e3de90fb38d9a29223e590cfd0d4f50baba87927..a2c4b70b7139a769d7809ab95cd09736bc9a478c 100644 (file)
--- a/gbe2_ecp3/trb_net_gbe_components.vhd
+++ b/gbe2_ecp3/trb_net_gbe_components.vhd
@@ -278,6 +278,7 @@ component trb_net16_gbe_protocol_selector is
 port (
        CLK                     : in    std_logic;  -- system clock
        RESET                   : in    std_logic;
+       RESET_FOR_DHCP : in std_logic;
 
 -- signals to/from main controller
        PS_DATA_IN              : in    std_logic_vector(8 downto 0); 
@@ -374,7 +375,8 @@ port (
        MONITOR_SELECT_REC_OUT        : out     std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
        MONITOR_SELECT_REC_BYTES_OUT  : out     std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
        MONITOR_SELECT_SENT_BYTES_OUT : out     std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-       MONITOR_SELECT_SENT_OUT       : out     std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0)     
+       MONITOR_SELECT_SENT_OUT       : out     std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+       MONITOR_SELECT_GEN_DBG_OUT    : out     std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0)   
 );
 end component;
 
@@ -409,6 +411,7 @@ port (
        CLK                     : in    std_logic;  -- system clock
        CLK_125                 : in    std_logic;
        RESET                   : in    std_logic;
+       RESET_FOR_DHCP : in std_logic;
 
        MC_LINK_OK_OUT          : out   std_logic;
        MC_RESET_LINK_IN        : in    std_logic;
@@ -518,7 +521,8 @@ port (
        MONITOR_SELECT_REC_OUT        : out     std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
        MONITOR_SELECT_REC_BYTES_OUT  : out     std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
        MONITOR_SELECT_SENT_BYTES_OUT : out     std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-       MONITOR_SELECT_SENT_OUT       : out     std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0)
+       MONITOR_SELECT_SENT_OUT       : out     std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+       MONITOR_SELECT_GEN_DBG_OUT    : out     std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0)
 );
 end component;
 
@@ -925,7 +929,8 @@ port(
        MONITOR_SELECT_REC_IN         : in      std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
        MONITOR_SELECT_REC_BYTES_IN   : in      std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
        MONITOR_SELECT_SENT_BYTES_IN  : in      std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-       MONITOR_SELECT_SENT_IN        : in      std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0)
+       MONITOR_SELECT_SENT_IN        : in      std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+       MONITOR_SELECT_GEN_DBG_IN     : in      std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0)
 );
 end component;
 

diff --git a/gbe2_ecp3/trb_net_gbe_protocols.vhd b/gbe2_ecp3/trb_net_gbe_protocols.vhd
index efd2c7204ab7c816bebf20f38071fbe093301b97..75fb03552613dbe2fdea433151f0e5c36e7f1080 100644 (file)
--- a/gbe2_ecp3/trb_net_gbe_protocols.vhd
+++ b/gbe2_ecp3/trb_net_gbe_protocols.vhd
@@ -74,7 +74,7 @@ port (
 -- END OF INTERFACE
 
 -- debug
-       DEBUG_OUT               : out   std_logic_vector(31 downto 0)
+       DEBUG_OUT               : out   std_logic_vector(63 downto 0)
 );
 end component;
 
@@ -122,7 +122,7 @@ port (
 -- END OF INTERFACE
 
 -- debug
-       DEBUG_OUT               : out   std_logic_vector(31 downto 0)
+       DEBUG_OUT               : out   std_logic_vector(63 downto 0)
 );
 end component;
 
@@ -163,7 +163,7 @@ port (
 -- END OF INTERFACE
 
 -- debug
-       DEBUG_OUT               : out   std_logic_vector(31 downto 0)
+       DEBUG_OUT               : out   std_logic_vector(63 downto 0)
 );
 end component;
 
@@ -215,7 +215,7 @@ port (
 -- END OF INTERFACE
 
 -- debug
-       DEBUG_OUT               : out   std_logic_vector(31 downto 0)
+       DEBUG_OUT               : out   std_logic_vector(63 downto 0)
 );
 end component;
 
@@ -265,7 +265,7 @@ port (
        DHCP_START_IN           : in    std_logic;
        DHCP_DONE_OUT           : out   std_logic;
 -- debug
-       DEBUG_OUT               : out   std_logic_vector(31 downto 0)
+       DEBUG_OUT               : out   std_logic_vector(63 downto 0)
 );
 end component;
 
@@ -313,7 +313,7 @@ port (
 -- END OF INTERFACE
 
 -- debug
-       DEBUG_OUT               : out   std_logic_vector(31 downto 0)
+       DEBUG_OUT               : out   std_logic_vector(63 downto 0)
 );
 end component;
 
@@ -361,7 +361,7 @@ port (
 -- END OF INTERFACE
 
 -- debug
-       DEBUG_OUT               : out   std_logic_vector(31 downto 0)
+       DEBUG_OUT               : out   std_logic_vector(63 downto 0)
 );
 end component;
 
@@ -403,7 +403,7 @@ port (
 -- END OF INTERFACE
 
 -- debug
-       DEBUG_OUT               : out   std_logic_vector(31 downto 0)
+       DEBUG_OUT               : out   std_logic_vector(63 downto 0)
 );
 end component;
 
@@ -445,6 +445,8 @@ generic ( STAT_ADDRESS_BASE : integer := 0
                STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
                STAT_DATA_RDY_OUT : out std_logic;
                STAT_DATA_ACK_IN  : in std_logic;
+               
+               DEBUG_OUT               : out   std_logic_vector(63 downto 0);
        -- END OF INTERFACE
        
        -- protocol specific ports
@@ -522,7 +524,7 @@ port (
        STAT_DATA_ACK_OUT : out std_logic_vector((c_MAX_PROTOCOLS + 1) - 1 downto 0);
 
 -- debug
-       DEBUG_OUT               : out   std_logic_vector(31 downto 0)
+       DEBUG_OUT               : out   std_logic_vector(63 downto 0)
 );
 end component;
 
@@ -562,6 +564,9 @@ port (
        STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
        STAT_DATA_RDY_OUT : out std_logic;
        STAT_DATA_ACK_IN  : in std_logic;
+       
+       DEBUG_OUT               : out   std_logic_vector(63 downto 0);
+       
 -- END OF INTERFACE
 
        TRANSMITTER_BUSY_IN         : in    std_logic;