-- Data from Frontends
FEE_DATA_OUT : out std_logic_vector (31 downto 0); --data from FEE
FEE_DATAREADY_OUT : out std_logic; --data on data_out is valid
- FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready
+ FEE_READ_IN : in std_logic; --must be high always unless connected entity can not read data, otherwise you will never get a dataready
FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); --valid after busy is low again
FEE_BUSY_OUT : out std_logic; --goes high shortly after start_readout; goes low when last dataword from FEE
--has been read.
begin
+APL_CTS_TARGET_ADDRESS <= x"FFFF";
+APL_FEE_LENGTH_IN <= x"0000";
+
-------------------------------------------------------------------------------
--Application Interface, receiving request from CTS
-------------------------------------------------------------------------------
APL_FEE_SEND_IN <= cts_start_readout_rising;
APL_FEE_READ_IN <= FEE_READ_IN;
+ FEE_BUSY_OUT <= APL_FEE_RUN_OUT;
APL_FEE_ERROR_PATTERN_IN(15 downto 0) <= buf_CTS_NUMBER_OUT;
APL_FEE_ERROR_PATTERN_IN(23 downto 16) <= buf_CTS_CODE_OUT;
-
- PROC_IPU_DATA : process(CLK)
- begin
- if rising_edge(CLK) then
- if IPU_READ_IN = '1' then
- buf_IPU_DATAREADY_OUT <= '0';
- end if;
- if buf_APL_READ_IN(1) = '1' and buf_APL_DATAREADY_OUT(1) = '1' and buf_APL_TYP_OUT(5 downto 3) = TYPE_DAT then
- if buf_APL_PACKET_NUM_OUT(5 downto 3) = c_F0 or buf_APL_PACKET_NUM_OUT(5 downto 3) = c_F2 then
- buf_IPU_DATA_OUT(31 downto 16) <= buf_APL_DATA_OUT(31 downto 16);
- elsif buf_APL_PACKET_NUM_OUT(5 downto 3) = c_F1 or buf_APL_PACKET_NUM_OUT(5 downto 3) = c_F3 then
- buf_IPU_DATA_OUT(15 downto 0) <= buf_APL_DATA_OUT(31 downto 16);
- buf_IPU_DATAREADY_OUT <= '1';
- end if;
- end if;
- end if;
- end process;
-
end architecture;
\ No newline at end of file
signal HC_COMMON_STAT_REGS : std_logic_vector(std_COMSTATREG*32-1 downto 0);
signal HC_COMMON_CTRL_REGS : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
signal buf_HC_STAT_REGS : std_logic_vector (2**4*32-1 downto 0);
+ signal HC_STAT_ack_waiting : std_logic_vector(127 downto 0) := (others => '0');
signal HUB_MED_CONNECTED : std_logic_vector (31 downto 0);
hub_control : trb_net16_regIO
generic map(
NUM_STAT_REGS => 4,
- NUM_CTRL_REGS => 3,
+ NUM_CTRL_REGS => 4,
INIT_CTRL_REGS => x"00000000_00000000_00009999_00000000" &
x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF",
USED_CTRL_REGS => "00111111",
buf_HC_STAT_REGS(5*32-1 downto 4*32) <= HUB_MED_CONNECTED;
buf_HC_STAT_REGS(5*32+31 downto 5*32+17) <= (others => '0');
buf_HC_STAT_REGS(6*32+31 downto 6*32+17) <= (others => '0');
- buf_HC_STAT_REGS(16*32-1 downto 12*32) <= (others => '0'); --unused regs
+ buf_HC_STAT_REGS(16*32-1 downto 12*32) <= HC_STAT_ack_waiting;
loop_links : for i in 0 to 16 generate
buf_HC_STAT_REGS(5*32+i) <= '1' when i < MII_NUMBER and MII_IS_UPLINK(i) = 1 else '0';
end if;
end process;
+ gen_ack_waiting : for i in 0 to MII_NUMBER-1 generate
+ HC_STAT_ack_waiting(i) <= IOBUF_STAT_INIT_OBUF_DEBUG((2*MII_NUMBER+i)*32+19);
+ HC_STAT_ack_waiting(32+i) <= IOBUF_STAT_INIT_OBUF_DEBUG((1*MII_NUMBER+i)*32+19);
+ HC_STAT_ack_waiting(64+i) <= IOBUF_STAT_INIT_OBUF_DEBUG((2*MII_NUMBER+i)*32+19);
+ HC_STAT_ack_waiting(96+i) <= IOBUF_STAT_INIT_OBUF_DEBUG((3*MII_NUMBER+i)*32+19);
+ end generate;
+
---------------------------------------------------------------------
--Debugging Signals
if rising_edge(CLK) then
connection_timed_out(i) <= '0';
timeout_found <= or_all(connection_timed_out);
- if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' or locking_point(i) = '1' then
+ if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' or locking_point(i) = '1' or CTRL_TIMEOUT_TIME = 0 then
timeout_counter(i) <= (others => '0');
elsif timeout_counter(i)(to_integer(unsigned('0'&CTRL_TIMEOUT_TIME)+to_unsigned(16,5))) = '1' then
connection_timed_out(i) <= '1';
if rising_edge(CLK) then
connection_timed_out(i) <= '0';
timeout_found <= or_all(connection_timed_out);
- if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' or locking_point(i) = '1' then
+ if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' or locking_point(i) = '1' or CTRL_TIMEOUT_TIME = 0 then
timeout_counter(i) <= (others => '0');
elsif timeout_counter(i)(conv_integer(('0'&CTRL_TIMEOUT_TIME)+16)) = '1' then
connection_timed_out(i) <= '1';
STAT_DEBUG(12) <= RESET;
STAT_DEBUG(14 downto 13) <= TRANSMITTED_BUFFERS;
STAT_DEBUG(17 downto 15) <= REC_BUFFER_SIZE_IN(2 downto 0);
-STAT_DEBUG(19 downto 18) <= transfer_counter(1 downto 0);
+STAT_DEBUG(19 downto 18) <= transfer_counter(1 downto 0); --used in hub monitoring!
STAT_DEBUG(20) <= '1';
STAT_DEBUG(31 downto 21) <= (others => '0');
end architecture;
NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers
NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers
--standard values for output registers
- INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0');
+ INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');
--set to 0 for unused ctrl registers to save resources
- USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001";
+ USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1');
--set to 0 for each unused bit in a register
- USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1');
+ USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');
USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port
INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
NUM_STAT_REGS : integer range 0 to 6 := 4; --log2 of number of status registers
NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers
--standard values for output registers
- INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0');
+ INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');
--set to 0 for unused ctrl registers to save resources
- USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001";
+ USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1');
--set to 0 for each unused bit in a register
- USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1');
+ USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');
USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port
INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";