REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
- REGIO_USE_1WIRE_INTERFACE: integer := c_YES --c_YES,c_NO,c_MONITOR
+ REGIO_USE_1WIRE_INTERFACE: integer := c_YES; --c_YES,c_NO,c_MONITOR
+ CLOCK_FREQUENCY : integer range 1 to 200 := 100
);
port(
REGIO_ONEWIRE_INOUT : inout std_logic;
REGIO_ONEWIRE_MONITOR_IN : in std_logic;
REGIO_ONEWIRE_MONITOR_OUT : out std_logic;
+
+ TRIGGER_MONITOR_IN : in std_logic; --strobe when timing trigger received
+ GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds
+ LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency
+ TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger
+ TIMER_US_TICK_OUT : out std_logic; --1 tick every microsecond
+
--Debugging & Status information
STAT_DEBUG_IPU : out std_logic_vector (31 downto 0);
STAT_DEBUG_1 : out std_logic_vector (31 downto 0);
INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
- HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"
+ HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
+ CLOCK_FREQ : integer range 1 to 200 := 100 --MHz
);
port(
-- Misc
IDRAM_ADDR_IN : in std_logic_vector(2 downto 0);
IDRAM_WR_IN : in std_logic;
MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
+ TRIGGER_MONITOR : in std_logic; --strobe when timing trigger received
+ GLOBAL_TIME : out std_logic_vector(31 downto 0); --global time, microseconds
+ LOCAL_TIME : out std_logic_vector(7 downto 0); --local time running with chip frequency
+ TIME_SINCE_LAST_TRG : out std_logic_vector(31 downto 0); --local time, resetted with each trigger
+ TIMER_US_TICK : out std_logic; --1 tick every microsecond
--Common Register in / out
COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REG_WIDTH-1 downto 0);
INIT_UNIQUE_ID => REGIO_INIT_UNIQUE_ID,
COMPILE_TIME => REGIO_COMPILE_TIME,
COMPILE_VERSION => REGIO_COMPILE_VERSION,
- HARDWARE_VERSION => REGIO_HARDWARE_VERSION
+ HARDWARE_VERSION => REGIO_HARDWARE_VERSION,
+ CLOCK_FREQ => CLOCK_FREQUENCY
)
port map(
-- Misc
IDRAM_ADDR_IN => buf_IDRAM_ADDR_IN,
IDRAM_WR_IN => buf_IDRAM_WR_IN,
MY_ADDRESS_OUT => MY_ADDRESS,
+ TRIGGER_MONITOR => TRIGGER_MONITOR_IN,
+ GLOBAL_TIME => GLOBAL_TIME_OUT,
+ LOCAL_TIME => LOCAL_TIME_OUT,
+ TIME_SINCE_LAST_TRG => TIME_SINCE_LAST_TRG_OUT,
+ TIMER_US_TICK => TIMER_US_TICK_OUT,
--Common Register in / out
COMMON_STAT_REG_IN => buf_COMMON_STAT_REG_IN,
COMMON_CTRL_REG_OUT => REGIO_COMMON_CTRL_REG_OUT,
component trb_net16_regIO is
generic (
- NUM_STAT_REGS : integer range 0 to 6 := 1; --log2 of number of status registers
- NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers
+ NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers
+ NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers
--standard values for output registers
- INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) :=
- (others => '0');
+ INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0');
--set to 0 for unused ctrl registers to save resources
USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001";
--set to 0 for each unused bit in a register
- USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) :=
- (others => '1');
+ USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1');
USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port
INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
- HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"
+ HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
+ CLOCK_FREQ : integer range 1 to 200 := 100 --MHz
);
port(
-- Misc
API_RUN_IN : in std_logic;
API_SEQNR_IN : in std_logic_vector (7 downto 0);
- --Port to write Unique ID
+ --Port to write Unique ID (-> 1-wire)
IDRAM_DATA_IN : in std_logic_vector(15 downto 0);
IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);
IDRAM_ADDR_IN : in std_logic_vector(2 downto 0);
IDRAM_WR_IN : in std_logic;
+
+ --Informations
MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
+ TRIGGER_MONITOR : in std_logic;
+ GLOBAL_TIME : out std_logic_vector(31 downto 0); --global time, microseconds
+ LOCAL_TIME : out std_logic_vector(7 downto 0); --local time running with chip frequency
+ TIME_SINCE_LAST_TRG : out std_logic_vector(31 downto 0); --local time, resetted with each trigger
+ TIMER_US_TICK : out std_logic; --1 tick every microsecond
--Common Register in / out
- COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0);
- COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0);
+ COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REG_WIDTH-1 downto 0);
+ COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REG_WIDTH-1 downto 0);
--Custom Register in / out
- REGISTERS_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);
- REGISTERS_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);
+ REGISTERS_IN : in std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);
+ REGISTERS_OUT : out std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);
--Internal Data Port
DAT_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);
DAT_READ_ENABLE_OUT : out std_logic;
DAT_WRITE_ACK_IN : in std_logic;
DAT_UNKNOWN_ADDR_IN : in std_logic;
DAT_TIMEOUT_OUT : out std_logic;
- STAT : out std_logic_vector(31 downto 0)
+
+ --Additional write access to ctrl registers
+ STAT : out std_logic_vector(31 downto 0);
+ STAT_ADDR_DEBUG : out std_logic_vector(15 downto 0)
);
end component;
INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
- HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"
+ HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
+ CLOCK_FREQ : integer range 1 to 200 := 100 --MHz
);
port(
-- Misc
--Informations
MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
- GLOBAL_TIME : out std_logic_vector(31 downto 0);--global time, microseconds
- LOCAL_TIME : out std_logic_vector(7 downto 0); --local time running with chip frequency
+ TRIGGER_MONITOR : in std_logic; --strobe when timing trigger received
+ GLOBAL_TIME : out std_logic_vector(31 downto 0); --global time, microseconds
+ LOCAL_TIME : out std_logic_vector(7 downto 0); --local time running with chip frequency
+ TIME_SINCE_LAST_TRG : out std_logic_vector(31 downto 0); --local time, resetted with each trigger
TIMER_US_TICK : out std_logic; --1 tick every microsecond
--Common Register in / out
signal buf_STAT_ADDR_DEBUG : std_logic_vector(15 downto 0);
+ signal global_time_i : std_logic_vector(31 downto 0) := (others => '0');
+ signal time_since_last_trg_i : std_logic_vector(31 downto 0) := (others => '0');
+ signal local_time_i : std_logic_vector(7 downto 0) := (others => '0');
+ signal us_tick_i : std_logic := '0';
+
+
begin
+---------------------------------------------------------------------
+--5bit address decoder for registers
+---------------------------------------------------------------------
pattern_gen_inst : trb_net_pattern_gen
generic map(
WIDTH => 5
);
reg_enable_pattern(63 downto 32) <= (others => '0');
- addresses : trb_net16_addresses
+---------------------------------------------------------------------
+-- trbnet addresses
+---------------------------------------------------------------------
+
+ the_addresses : trb_net16_addresses
generic map(
INIT_ADDRESS => INIT_ADDRESS,
INIT_UNIQUE_ID => INIT_UNIQUE_ID,
STAT_DEBUG => buf_STAT_ADDR_DEBUG
);
- STAT_ADDR_DEBUG(2 downto 0) <= state_bits(2 downto 0);
- STAT_ADDR_DEBUG(3) <= ADR_DONT_UNDERSTAND;
- STAT_ADDR_DEBUG(4) <= API_DATAREADY_IN;
- STAT_ADDR_DEBUG(5) <= buf_API_SHORT_TRANSFER_OUT;
- STAT_ADDR_DEBUG(6) <= combined_API_SEND_OUT;
- STAT_ADDR_DEBUG(11 downto 7) <= buf_STAT_ADDR_DEBUG(11 downto 7);
- STAT_ADDR_DEBUG(12) <= combined_API_DATAREADY_OUT;
- STAT_ADDR_DEBUG(13) <= ADR_REJECTED;
- STAT_ADDR_DEBUG(14) <= ADR_SEND_OUT;
- STAT_ADDR_DEBUG(15) <= ADR_DATAREADY_OUT;
- buf_DAT_ADDR_OUT <= address;
- buf_DAT_DATA_OUT <= saved_Reg_high & saved_Reg_low;
+---------------------------------------------------------------------
+-- Main State Machine
+---------------------------------------------------------------------
fsm : process(API_DATA_IN, API_PACKET_NUM_IN, API_TYP_IN, API_DATAREADY_IN, API_READ_IN,
address, saved_Reg_high, saved_Reg_low, saved_operation, current_state,
next_nomoredata <= '0';
end if;
- when HEADER_RECV => --read and save HDR
+ when HEADER_RECV => --read HDR
if API_DATAREADY_IN = '1' then
case API_PACKET_NUM_IN is
when c_F3 =>
next_state <= REG_WRITE; --ctrl register
else
next_state <= SEND_REPLY_SHORT_TRANSFER;
+ next_dont_understand <= '1';
end if;
end if;
else
next_COMMON_REGISTERS_OUT_write_enable <= reg_enable_pattern(std_COMCTRLREG-1 downto 0);
end if;
- next_state <= REG_READ;
+ next_state <= SEND_REPLY_SHORT_TRANSFER; --REG_READ;
else
next_DAT_WRITE_ENABLE_OUT <= '1';
next_state <= WAIT_AFTER_REG_WRITE;
when c_F0 =>
next_API_DATA_OUT <= address;
when c_F1 =>
- if address(7 downto 6) = "01" then
+ if address(7 downto 6) = "01" then --0x40
next_API_DATA_OUT <= rom_read_dout;
rom_read_addr <= address(1 downto 0) & '0';
- elsif address(7 downto 6) = "10" then
+ elsif address(7 downto 6) = "10" then --0x80
next_API_DATA_OUT <= REGISTERS_IN(regnum_STAT*c_REGIO_REG_WIDTH+31 downto regnum_STAT*c_REGIO_REG_WIDTH+16);
- elsif address(7 downto 6) = "11" then
+ elsif address(7 downto 6) = "11" then --0xC0
next_API_DATA_OUT <= buf_REGISTERS_OUT(regnum_CTRL*c_REGIO_REG_WIDTH+31 downto regnum_CTRL*c_REGIO_REG_WIDTH+16);
- elsif address(5) = '0' then
+ elsif address(5) = '0' then --0x00
next_API_DATA_OUT <= COMMON_STAT_REG_IN(regnum_cSTAT*c_REGIO_REG_WIDTH+31 downto regnum_cSTAT*c_REGIO_REG_WIDTH+16);
- else --if address(5) = '1' then
+ elsif address(5) = '1' then --0x20
next_API_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*c_REGIO_REG_WIDTH+31 downto regnum_cCTRL*c_REGIO_REG_WIDTH+16);
+ else
+ next_API_DATA_OUT <= (others => '0');
end if;
when c_F2 =>
if address(7 downto 6) = "01" then
next_API_DATA_OUT <= buf_REGISTERS_OUT(regnum_CTRL*c_REGIO_REG_WIDTH+15 downto regnum_CTRL*c_REGIO_REG_WIDTH);
elsif address(5) = '0' then
next_API_DATA_OUT <= COMMON_STAT_REG_IN(regnum_cSTAT*c_REGIO_REG_WIDTH+15 downto regnum_cSTAT*c_REGIO_REG_WIDTH);
- else --if address(5) = '1' then
+ elsif address(5) = '1' then
next_API_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*c_REGIO_REG_WIDTH+15 downto regnum_cCTRL*c_REGIO_REG_WIDTH);
+ else
+ next_API_DATA_OUT <= (others => '0');
end if;
when c_F3 =>
next_API_DATA_OUT <= (others => '0');
end process;
---generate packet numbers
+---------------------------------------------------------------------
+-- Packet Numbers
+---------------------------------------------------------------------
reg_packet_counter : process(CLK)
begin
if rising_edge(CLK) then
end if;
end process;
+---------------------------------------------------------------------
+-- Generate output to API
+---------------------------------------------------------------------
process(CLK)
begin
if rising_edge(CLK) then
end if;
end process;
+ --combine signals from regio and addresses
+ process(current_state, ADR_READ_OUT, buf_API_READ_OUT, ADR_SEND_OUT, ADR_DATA_OUT, ADR_DATAREADY_OUT,
+ ADR_PACKET_NUM_OUT, buf_API_SEND_OUT, buf_API_DATA_OUT, buf_API_DATAREADY_OUT, buf_API_PACKET_NUM_OUT)
+ begin
+ if current_state = ADDRESS_RECV or current_state = ADDRESS_ACK then
+ combined_API_READ_OUT <= ADR_READ_OUT;
+ combined_API_SEND_OUT <= ADR_SEND_OUT;
+ combined_API_DATA_OUT <= ADR_DATA_OUT;
+ combined_API_DATAREADY_OUT <= ADR_DATAREADY_OUT;
+ combined_API_PACKET_NUM_OUT <= ADR_PACKET_NUM_OUT;
+ else
+ combined_API_READ_OUT <= buf_API_READ_OUT;
+ combined_API_SEND_OUT <= buf_API_SEND_OUT;
+ combined_API_DATA_OUT <= buf_API_DATA_OUT;
+ combined_API_DATAREADY_OUT <= buf_API_DATAREADY_OUT;
+ combined_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT;
+ end if;
+ end process;
+
+ buf_API_ERROR_PATTERN_OUT(31 downto 19) <= (others => '0');
+ buf_API_ERROR_PATTERN_OUT(18) <= nomoredata;
+ buf_API_ERROR_PATTERN_OUT(17) <= timeout;
+ buf_API_ERROR_PATTERN_OUT(16) <= unknown;
+ buf_API_ERROR_PATTERN_OUT(15 downto 5) <= (others => '0');
+ buf_API_ERROR_PATTERN_OUT(4) <= dont_understand;
+ buf_API_ERROR_PATTERN_OUT(3 downto 0) <= (others => '0');
+
+---------------------------------------------------------------------
+-- Read from DAT port
+---------------------------------------------------------------------
--save Dataready_in in case API can not read immediately
process(CLK)
begin
end if;
end process;
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ buf_DAT_DATA_IN <= (others => '0');
+ elsif DAT_DATAREADY_IN = '1' then
+ buf_DAT_DATA_IN <= DAT_DATA_IN;
+ end if;
+ end if;
+ end process;
+---------------------------------------------------------------------
+-- User defined CTRL registers
+---------------------------------------------------------------------
gen_regout : for i in 0 to 2**(NUM_CTRL_REGS)-1 generate
gen_regoutff1 : for j in i*c_REGIO_REG_WIDTH to (i+1)*c_REGIO_REG_WIDTH-1 generate
gen_regoutff : if USED_CTRL_REGS(i) = '1' and USED_CTRL_BITMASK(j) = '1' generate
end generate;
end generate;
-
+---------------------------------------------------------------------
+-- Common CTRL registers
+---------------------------------------------------------------------
gen_strobe_ctrl_regs : if std_COMCTRLREG >= 1 generate
process(CLK)
begin
end generate;
end generate;
- process(CLK)
+---------------------------------------------------------------------
+-- Global Time Register
+---------------------------------------------------------------------
+
+ proc_global_time : process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' then
- buf_DAT_DATA_IN <= (others => '0');
- elsif DAT_DATAREADY_IN = '1' then
- buf_DAT_DATA_IN <= DAT_DATA_IN;
+-- global_time(15 downto 0) <= next_global_time(15 downto 0);
+-- global_time_overflow <= '0';
+ if COMMON_REGISTERS_OUT_write_enable(2) = '1' then
+ global_time_i <= saved_Reg_high & saved_Reg_low;
+ elsif us_tick_i = '1' then
+ global_time_i <= global_time_i + 1;
+-- next_global_time(15 downto 0) <= global_time(15 downto 0) + 1;
+-- if or_all(global_time(15 downto 0)) = '1' then
+-- global_time_overflow <= '1';
+-- end if;
+-- elsif global_time_overflow = '1' then
+-- global_time_buf <= '0';
+-- global_time(31 downto 16) <= global_time(31 downto 16) + 1;
end if;
end if;
end process;
+ proc_us_tick : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if local_time_i = conv_std_logic_vector(CLOCK_FREQ - 1,8) then
+ local_time_i <= (others => '0');
+ us_tick_i <= '1';
+ else
+ local_time_i <= local_time_i + 1;
+ us_tick_i <= '0';
+ end if;
+ end if;
+ end process;
- --combine signals from regio and addresses
- process(current_state, ADR_READ_OUT, buf_API_READ_OUT, ADR_SEND_OUT, ADR_DATA_OUT, ADR_DATAREADY_OUT,
- ADR_PACKET_NUM_OUT, buf_API_SEND_OUT, buf_API_DATA_OUT, buf_API_DATAREADY_OUT, buf_API_PACKET_NUM_OUT)
+ proc_time_since_trg : process(CLK)
begin
- if current_state = ADDRESS_RECV or current_state = ADDRESS_ACK then
- combined_API_READ_OUT <= ADR_READ_OUT;
- combined_API_SEND_OUT <= ADR_SEND_OUT;
- combined_API_DATA_OUT <= ADR_DATA_OUT;
- combined_API_DATAREADY_OUT <= ADR_DATAREADY_OUT;
- combined_API_PACKET_NUM_OUT <= ADR_PACKET_NUM_OUT;
- else
- combined_API_READ_OUT <= buf_API_READ_OUT;
- combined_API_SEND_OUT <= buf_API_SEND_OUT;
- combined_API_DATA_OUT <= buf_API_DATA_OUT;
- combined_API_DATAREADY_OUT <= buf_API_DATAREADY_OUT;
- combined_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT;
+ if rising_edge(CLK) then
+ if TRIGGER_MONITOR = '1' then
+ time_since_last_trg_i <= (others => '0');
+ else
+ time_since_last_trg_i <= time_since_last_trg_i + 1;
+ end if;
end if;
end process;
+ GLOBAL_TIME <= global_time_i;
+ LOCAL_TIME <= local_time_i;
+ TIMER_US_TICK <= us_tick_i;
+ TIME_SINCE_LAST_TRG <= time_since_last_trg_i;
+---------------------------------------------------------------------
+-- ROM with board information
+---------------------------------------------------------------------
board_rom : rom_16x8
generic map(
INIT0 => COMPILE_TIME(15 downto 0),
dout => rom_read_dout
);
- buf_API_ERROR_PATTERN_OUT(31 downto 19) <= (others => '0');
- buf_API_ERROR_PATTERN_OUT(18) <= nomoredata;
- buf_API_ERROR_PATTERN_OUT(17) <= timeout;
- buf_API_ERROR_PATTERN_OUT(16) <= unknown;
- buf_API_ERROR_PATTERN_OUT(15 downto 5) <= (others => '0');
- buf_API_ERROR_PATTERN_OUT(4) <= dont_understand;
- buf_API_ERROR_PATTERN_OUT(3 downto 0) <= (others => '0');
+---------------------------------------------------------------------
+-- Assign signals to outputs
+---------------------------------------------------------------------
API_READ_OUT <= combined_API_READ_OUT;
API_SEND_OUT <= combined_API_SEND_OUT;
API_DATAREADY_OUT <= combined_API_DATAREADY_OUT;
REGISTERS_OUT <= buf_REGISTERS_OUT;
COMMON_CTRL_REG_OUT <= buf_COMMON_CTRL_REG_OUT;
+ buf_DAT_ADDR_OUT <= address;
+ buf_DAT_DATA_OUT <= saved_Reg_high & saved_Reg_low;
+
+---------------------------------------------------------------------
+-- Debugging Signals
+---------------------------------------------------------------------
+
STAT(3 downto 0) <= state_bits;
STAT(6 downto 4) <= buf_API_PACKET_NUM_OUT;
STAT(7) <= next_API_DATAREADY_OUT;
end process;
+ STAT_ADDR_DEBUG(2 downto 0) <= state_bits(2 downto 0);
+ STAT_ADDR_DEBUG(3) <= ADR_DONT_UNDERSTAND;
+ STAT_ADDR_DEBUG(4) <= API_DATAREADY_IN;
+ STAT_ADDR_DEBUG(5) <= buf_API_SHORT_TRANSFER_OUT;
+ STAT_ADDR_DEBUG(6) <= combined_API_SEND_OUT;
+ STAT_ADDR_DEBUG(11 downto 7) <= buf_STAT_ADDR_DEBUG(11 downto 7);
+ STAT_ADDR_DEBUG(12) <= combined_API_DATAREADY_OUT;
+ STAT_ADDR_DEBUG(13) <= ADR_REJECTED;
+ STAT_ADDR_DEBUG(14) <= ADR_SEND_OUT;
+ STAT_ADDR_DEBUG(15) <= ADR_DATAREADY_OUT;
+
+
end architecture;
jspc29 / trbnet.git / commitdiff