SFP_LOS : in std_logic;\r
SFP_MOD_0 : in std_logic;\r
\r
- \r
+ --ADC AddOn\r
+ GPIO : inout std_logic_vector(5 downto 0);\r
+\r
+ ADDON_LED : out std_logic_vector(7 downto 1);\r
+ ADDON_LED_RJ : out std_logic_vector(1 downto 0);\r
+\r
+ SCLK_A : out std_logic;\r
+ CSB_A : out std_logic;\r
+ SDIO_A : inout std_logic;\r
+ FCO_A : in std_logic;\r
+ DATA_A : in std_logic_vector(3 downto 0);\r
+ DCO_A : in std_logic;\r
+ CLK_A : out std_logic;\r
+\r
+ CLK_B : out std_logic;\r
+ TESTPAT_B : out std_logic;\r
+ DCO_B : in std_logic;\r
+ DATA_B : in std_logic;\r
+ CNV_B : out std_logic;\r
+\r
+ LEMO_OUT : out std_logic_vector(1 downto 0);\r
+ LEMO_OE : out std_logic_vector(1 downto 0);\r
+ LEMO_TTL : in std_logic_vector(1 downto 0);\r
+ LEMO_NIM : in std_logic_vector(1 downto 0);\r
+ ADDON_RJ : in std_logic_vector(3 downto 0);\r
+\r
--ADC\r
ADC_SCLK : out std_logic;\r
ADC_NCS : out std_logic;\r
\r
end entity;\r
\r
-architecture arch of trb5sc_adc is\r
+architecture arch of trb5sc_cts is\r
\r
constant ACTIVE_CHANNELS : integer := 5;\r
\r
signal readout_rx : READOUT_RX;\r
signal readout_tx : readout_tx_array_t(0 to ACTIVE_CHANNELS-1);\r
\r
- signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, bus_master_in, busadc_tx, busi2c_tx : CTRLBUS_TX;\r
- signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, bus_master_out, busadc_rx, busi2c_rx : CTRLBUS_RX;\r
+ signal ctrlbus_tx, bustools_tx, buscts_rx, bustc_tx, busgbeip_rx, busgbereg_rx, bus_master_in, busadc_tx : CTRLBUS_TX;\r
+ signal ctrlbus_rx, bustools_rx, buscts_tx, bustc_rx, busgbeip_tx, busgbereg_tx, bus_master_out, busadc_rx : CTRLBUS_RX;\r
\r
signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
signal clock_select : std_logic;\r
signal bus_master_active : std_logic;\r
signal flash_ncs_i : std_logic;\r
+ signal rdack, wrack : std_logic;\r
+\r
\r
signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);\r
signal header_io_i : std_logic_vector(10 downto 1);\r
\r
signal clk_350, clk_50, clk_200bypass : std_logic;\r
\r
- \r
+ signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0);\r
+ signal trigger_gen_outputs_i: std_logic_vector(TRIG_GEN_OUTPUT_NUM-1 downto 0);\r
+ signal trigger_busy_i : std_logic;\r
+ signal cts_trigger_out : std_logic;\r
+ signal cts_monitor_out : std_logic_vector(1 downto 0);\r
+\r
+ signal gbe_cts_number : std_logic_vector(15 downto 0);\r
+ signal gbe_cts_code : std_logic_vector(7 downto 0);\r
+ signal gbe_cts_information : std_logic_vector(7 downto 0);\r
+ signal gbe_cts_start_readout : std_logic;\r
+ signal gbe_cts_readout_type : std_logic_vector(3 downto 0);\r
+ signal gbe_cts_readout_finished : std_logic;\r
+ signal gbe_cts_status_bits : std_logic_vector(31 downto 0);\r
+ signal gbe_fee_data : std_logic_vector(15 downto 0);\r
+ signal gbe_fee_dataready : std_logic;\r
+ signal gbe_fee_read : std_logic;\r
+ signal gbe_fee_status_bits : std_logic_vector(31 downto 0);\r
+ signal gbe_fee_busy : std_logic;\r
+\r
+ signal gsc_init_data, gsc_reply_data : std_logic_vector(15 downto 0);\r
+ signal gsc_init_read, gsc_reply_read : std_logic;\r
+ signal gsc_init_dataready, gsc_reply_dataready : std_logic;\r
+ signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0);\r
+ signal gsc_busy : std_logic;\r
+\r
+ signal cts_rdo_trg_status_bits_cts : std_logic_vector(31 downto 0) := (others => '0');\r
+ signal cts_rdo_data : std_logic_vector(31 downto 0);\r
+ signal cts_rdo_write : std_logic;\r
+ signal cts_rdo_finished : std_logic;\r
+\r
+ -- signal cts_ext_trigger : std_logic;\r
+ -- signal cts_ext_status : std_logic_vector(31 downto 0) := (others => '0');\r
+ -- signal cts_ext_control : std_logic_vector(31 downto 0);\r
+ -- signal cts_ext_debug : std_logic_vector(31 downto 0);\r
+ -- signal cts_ext_header : std_logic_vector(1 downto 0) := "00";\r
+\r
+ signal cts_rdo_additional_data : std_logic_vector(32*cts_rdo_additional_ports-1 downto 0);\r
+ signal cts_rdo_additional_write : std_logic_vector(cts_rdo_additional_ports-1 downto 0) := (others => '0');\r
+ signal cts_rdo_additional_finished : std_logic_vector(cts_rdo_additional_ports-1 downto 0) := (others => '1');\r
+ signal cts_rdo_trg_status_bits_additional : std_logic_vector(32*cts_rdo_additional_ports-1 downto 0) := (others => '0');\r
+\r
+ signal cts_rdo_additional : readout_tx_array_t(0 to cts_rdo_additional_ports-1);\r
+ signal cts_rdo_rx : READOUT_RX;\r
+\r
+\r
+ signal cts_addon_triggers_in : std_logic_vector(ADDON_LINE_COUNT-1 downto 0);\r
+ signal cts_monitor_out : std_logic_vector(CTS_OUTPUT_MULTIPLEXERS-1 downto 0);\r
+\r
+\r
+ signal cts_trg_send : std_logic;\r
+ signal cts_trg_type : std_logic_vector(3 downto 0);\r
+ signal cts_trg_number : std_logic_vector(15 downto 0);\r
+ signal cts_trg_information : std_logic_vector(23 downto 0);\r
+ signal cts_trg_code : std_logic_vector(7 downto 0);\r
+ signal cts_trg_status_bits : std_logic_vector(31 downto 0);\r
+ signal cts_trg_busy : std_logic;\r
+\r
+ signal cts_ipu_send : std_logic;\r
+ signal cts_ipu_type : std_logic_vector(3 downto 0);\r
+ signal cts_ipu_number : std_logic_vector(15 downto 0);\r
+ signal cts_ipu_information : std_logic_vector(7 downto 0);\r
+ signal cts_ipu_code : std_logic_vector(7 downto 0);\r
+ signal cts_ipu_status_bits : std_logic_vector(31 downto 0);\r
+ signal cts_ipu_busy : std_logic;\r
+\r
+\r
begin\r
\r
- trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK);\r
+ -- trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK);\r
\r
---------------------------------------------------------------------------\r
-- Clock & Reset Handling\r
THE_CLOCK_RESET : entity work.clock_reset_handler\r
port map(\r
CLOCK_IN => CLK_200,\r
- RESET_FROM_NET => med2int(0).stat_op(13),\r
- SEND_RESET_IN => med2int(0).stat_op(15),\r
+ RESET_FROM_NET => '0',--med2int(0).stat_op(13),\r
+ SEND_RESET_IN => '0', --med2int(0).stat_op(15),\r
\r
BUS_RX => bustc_rx,\r
BUS_TX => bustc_tx,\r
\r
DEBUG_OUT => debug_clock_reset\r
);\r
+ \r
+\r
+\r
\r
THE_ADC_PLL : entity work.adc_pll\r
port map(\r
CLKOS => clk_50,\r
CLKOS2 => open\r
);\r
- \r
- CLK_A <= clk_50; \r
- \r
+\r
+ CLK_A <= clk_50;\r
\r
---------------------------------------------------------------------------\r
--- TrbNet Uplink\r
+-- GbE\r
---------------------------------------------------------------------------\r
-\r
- THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync\r
+ GBE : entity work.gbe_wrapper\r
generic map(\r
- SERDES_NUM => 0,\r
- USE_NEW_ECP5_RESET => 1,\r
- IS_SYNC_SLAVE => c_YES\r
+ DO_SIMULATION => 0,\r
+ INCLUDE_DEBUG => 0,\r
+ USE_INTERNAL_TRBNET_DUMMY => 0,\r
+ USE_EXTERNAL_TRBNET_DUMMY => 0,\r
+ RX_PATH_ENABLE => 1,\r
+ FIXED_SIZE_MODE => 1,\r
+ INCREMENTAL_MODE => 1,\r
+ FIXED_SIZE => 100,\r
+ FIXED_DELAY_MODE => 1,\r
+ UP_DOWN_MODE => 0,\r
+ UP_DOWN_LIMIT => 100,\r
+ FIXED_DELAY => 100,\r
+\r
+ NUMBER_OF_GBE_LINKS => 1,\r
+ LINKS_ACTIVE => "0001",\r
+\r
+ LINK_HAS_READOUT => "0001",\r
+ LINK_HAS_SLOWCTRL => "0001",\r
+ LINK_HAS_DHCP => "0001",\r
+ -- LINK_HAS_ARP => "0001",\r
+ LINK_HAS_PING => "0001",\r
+ LINK_HAS_FWD => "0000"\r
)\r
+\r
port map(\r
- CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full,\r
- CLK_INTERNAL_FULL => clk_full_osc,\r
- SYSCLK => clk_sys,\r
- RESET => reset_i,\r
- CLEAR => clear_i,\r
- --Internal Connection\r
- MEDIA_MED2INT => med2int(0),\r
- MEDIA_INT2MED => int2med(0),\r
-\r
- --Sync operation\r
- RX_DLM => open,\r
- RX_DLM_WORD => open,\r
- TX_DLM => open,\r
- TX_DLM_WORD => open,\r
-\r
- --SFP Connection\r
- SD_PRSNT_N_IN => sfp_prsnt_i,\r
- SD_LOS_IN => sfp_los_i,\r
- SD_TXDIS_OUT => sfp_txdis_i,\r
- --Control Interface\r
- BUS_RX => bussci_rx,\r
- BUS_TX => bussci_tx,\r
- -- Status and control port\r
- STAT_DEBUG => med_stat_debug(63 downto 0),\r
- CTRL_DEBUG => open\r
+ CLK_SYS_IN => clk_sys,\r
+ CLK_125_IN => CLK_SUPPL_PCLK,\r
+ RESET => reset_i,\r
+ GSR_N => GSR_N,\r
+\r
+ TRIGGER_IN => cts_rdo_rx.data_valid,\r
+\r
+ SD_PRSNT_N_IN(0) => SFP_MOD0,\r
+ SD_LOS_IN(0) => SFP_LOS,\r
+ SD_TXDIS_OUT(0) => SFP_TX_DIS,\r
+\r
+ CTS_NUMBER_IN => gbe_cts_number,\r
+ CTS_CODE_IN => gbe_cts_code,\r
+ CTS_INFORMATION_IN => gbe_cts_information,\r
+ CTS_READOUT_TYPE_IN => gbe_cts_readout_type,\r
+ CTS_START_READOUT_IN => gbe_cts_start_readout,\r
+ CTS_DATA_OUT => open,\r
+ CTS_DATAREADY_OUT => open,\r
+ CTS_READOUT_FINISHED_OUT => gbe_cts_readout_finished,\r
+ CTS_READ_IN => '1',\r
+ CTS_LENGTH_OUT => open,\r
+ CTS_ERROR_PATTERN_OUT => gbe_cts_status_bits,\r
+\r
+ FEE_DATA_IN => gbe_fee_data,\r
+ FEE_DATAREADY_IN => gbe_fee_dataready,\r
+ FEE_READ_OUT => gbe_fee_read,\r
+ FEE_STATUS_BITS_IN => gbe_fee_status_bits,\r
+ FEE_BUSY_IN => gbe_fee_busy,\r
+\r
+ MC_UNIQUE_ID_IN => timer.uid,\r
+ MY_TRBNET_ADDRESS_IN => timer.network_address,\r
+ ISSUE_REBOOT_OUT => reboot_from_gbe,\r
+\r
+ GSC_CLK_IN => clk_sys,\r
+ GSC_INIT_DATAREADY_OUT => gsc_init_dataready,\r
+ GSC_INIT_DATA_OUT => gsc_init_data,\r
+ GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num,\r
+ GSC_INIT_READ_IN => gsc_init_read,\r
+ GSC_REPLY_DATAREADY_IN => gsc_reply_dataready,\r
+ GSC_REPLY_DATA_IN => gsc_reply_data,\r
+ GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num,\r
+ GSC_REPLY_READ_OUT => gsc_reply_read,\r
+ GSC_BUSY_IN => gsc_busy,\r
+\r
+ BUS_IP_RX => busgbeip_rx,\r
+ BUS_IP_TX => busgbeip_tx,\r
+ BUS_REG_RX => busgbereg_rx,\r
+ BUS_REG_TX => busgbereg_tx,\r
+\r
+ MAKE_RESET_OUT => reset_via_gbe,\r
+ STATUS_OUT => status, --open,\r
+ DEBUG_OUT => open\r
);\r
\r
- gen_sfp_con : if SERDES_NUM = 1 generate\r
- sfp_los_i <= SFP_LOS;\r
- sfp_prsnt_i <= SFP_MOD_0;\r
- SFP_TX_DIS <= sfp_txdis_i;\r
- end generate;\r
- gen_bpl_con : if SERDES_NUM = 0 generate\r
- sfp_los_i <= BACK_GPIO(1);\r
- sfp_prsnt_i <= BACK_GPIO(1);\r
- BACK_GPIO(0) <= sfp_txdis_i;\r
- end generate;\r
-\r
-\r
---------------------------------------------------------------------------\r
--- Endpoint\r
+-- Hub\r
---------------------------------------------------------------------------\r
- THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record\r
- generic map (\r
- ADDRESS_MASK => x"FFFF",\r
- BROADCAST_BITMASK => BROADCAST_BITMASK,\r
- REGIO_INIT_ENDPOINT_ID => x"0001",\r
- REGIO_USE_1WIRE_INTERFACE => c_I2C,\r
- TIMING_TRIGGER_RAW => c_YES,\r
- --Configure data handler\r
- DATA_INTERFACE_NUMBER => ACTIVE_CHANNELS,\r
- DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE,\r
- DATA_BUFFER_WIDTH => 32,\r
- DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE,\r
- TRG_RELEASE_AFTER_DATA => c_YES,\r
- HEADER_BUFFER_DEPTH => 9,\r
- HEADER_BUFFER_FULL_THRESH => 2**9-16,\r
- USE_GBE => USE_GBE\r
+ THE_HUB : trb_net16_hub_streaming_port_sctrl_cts\r
+ generic map(\r
+ INIT_ADDRESS => INIT_ADDRESS,\r
+ MII_NUMBER => INTERFACE_NUM,\r
+ MII_IS_UPLINK => IS_UPLINK,\r
+ MII_IS_DOWNLINK => IS_DOWNLINK,\r
+ MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY,\r
+ HARDWARE_VERSION => HARDWARE_INFO,\r
+ INCLUDED_FEATURES => INCLUDED_FEATURES,\r
+ INIT_ENDPOINT_ID => x"0001",\r
+ BROADCAST_BITMASK => x"7E",\r
+ CLOCK_FREQUENCY => 100,\r
+ USE_ONEWIRE => c_YES,\r
+ BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR,\r
+ RDO_ADDITIONAL_PORT => cts_rdo_additional_ports,\r
+ RDO_DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE,\r
+ RDO_DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE,\r
+ RDO_HEADER_BUFFER_DEPTH => 9,\r
+ RDO_HEADER_BUFFER_FULL_THRESH => 2**9-16\r
)\r
-\r
- port map(\r
- -- Misc\r
- CLK => clk_sys,\r
- RESET => reset_i,\r
- CLK_125 => CLK_125,\r
- CLEAR_N => GSR_N,\r
-\r
- -- Media direction port\r
- MEDIA_MED2INT => med2int(0),\r
- MEDIA_INT2MED => int2med(0),\r
-\r
- --Timing trigger in\r
- TRG_TIMING_TRG_RECEIVED_IN => trigger_in_i,\r
-\r
- READOUT_RX => readout_rx,\r
- READOUT_TX => readout_tx,\r
-\r
- --Slow Control Port\r
- REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00\r
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20\r
- BUS_RX => ctrlbus_rx,\r
- BUS_TX => ctrlbus_tx,\r
+ port map (\r
+ CLK => clk_sys,\r
+ RESET => reset_i,\r
+ CLK_EN => '1',\r
+\r
+ -- Media interfacces ---------------------------------------------------------------\r
+ MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0) => open,\r
+ MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0) => open,\r
+ MED_PACKET_NUM_OUT(INTERFACE_NUM*3-1 downto 0) => open,\r
+ MED_READ_IN(INTERFACE_NUM*1-1 downto 0) => (others => '0'),\r
+ MED_DATAREADY_IN(INTERFACE_NUM*1-1 downto 0) => (others => '0'),\r
+ MED_DATA_IN(INTERFACE_NUM*16-1 downto 0) => (others => '0'),\r
+ MED_PACKET_NUM_IN(INTERFACE_NUM*3-1 downto 0) => (others => '0'),\r
+ MED_READ_OUT(INTERFACE_NUM*1-1 downto 0) => open,\r
+ MED_STAT_OP(INTERFACE_NUM*16-1 downto 0) => open,\r
+ MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => (others => '0'),\r
+\r
+ -- Gbe Read-out Path ---------------------------------------------------------------\r
+ --Event information coming from CTS for GbE\r
+ GBE_CTS_NUMBER_OUT => gbe_cts_number,\r
+ GBE_CTS_CODE_OUT => gbe_cts_code,\r
+ GBE_CTS_INFORMATION_OUT => gbe_cts_information,\r
+ GBE_CTS_READOUT_TYPE_OUT => gbe_cts_readout_type,\r
+ GBE_CTS_START_READOUT_OUT => gbe_cts_start_readout,\r
+ --Information sent to CTS\r
+ GBE_CTS_READOUT_FINISHED_IN => gbe_cts_readout_finished,\r
+ GBE_CTS_STATUS_BITS_IN => gbe_cts_status_bits,\r
+ -- Data from Frontends\r
+ GBE_FEE_DATA_OUT => gbe_fee_data,\r
+ GBE_FEE_DATAREADY_OUT => gbe_fee_dataready,\r
+ GBE_FEE_READ_IN => gbe_fee_read,\r
+ GBE_FEE_STATUS_BITS_OUT => gbe_fee_status_bits,\r
+ GBE_FEE_BUSY_OUT => gbe_fee_busy,\r
+\r
+ -- CTS Request Sending -------------------------------------------------------------\r
+ --LVL1 trigger\r
+ CTS_TRG_SEND_IN => cts_trg_send,\r
+ CTS_TRG_TYPE_IN => cts_trg_type,\r
+ CTS_TRG_NUMBER_IN => cts_trg_number,\r
+ CTS_TRG_INFORMATION_IN => cts_trg_information,\r
+ CTS_TRG_RND_CODE_IN => cts_trg_code,\r
+ CTS_TRG_STATUS_BITS_OUT => cts_trg_status_bits,\r
+ CTS_TRG_BUSY_OUT => cts_trg_busy,\r
+ --IPU Channel\r
+ CTS_IPU_SEND_IN => cts_ipu_send,\r
+ CTS_IPU_TYPE_IN => cts_ipu_type,\r
+ CTS_IPU_NUMBER_IN => cts_ipu_number,\r
+ CTS_IPU_INFORMATION_IN => cts_ipu_information,\r
+ CTS_IPU_RND_CODE_IN => cts_ipu_code,\r
+ -- Receiver port\r
+ CTS_IPU_STATUS_BITS_OUT => cts_ipu_status_bits,\r
+ CTS_IPU_BUSY_OUT => cts_ipu_busy,\r
+\r
+ -- CTS Data Readout ----------------------------------------------------------------\r
+ --Trigger to CTS out\r
+ RDO_TRIGGER_IN => cts_trigger_out,\r
+ RDO_TRG_DATA_VALID_OUT => cts_rdo_rx.data_valid,\r
+ RDO_VALID_TIMING_TRG_OUT => cts_rdo_rx.valid_timing_trg,\r
+ RDO_VALID_NOTIMING_TRG_OUT => cts_rdo_rx.valid_notiming_trg,\r
+ RDO_INVALID_TRG_OUT => cts_rdo_rx.invalid_trg,\r
+ RDO_TRG_TYPE_OUT => cts_rdo_rx.trg_type,\r
+ RDO_TRG_CODE_OUT => cts_rdo_rx.trg_code,\r
+ RDO_TRG_INFORMATION_OUT => cts_rdo_rx.trg_information,\r
+ RDO_TRG_NUMBER_OUT => cts_rdo_rx.trg_number,\r
+\r
+ --Data from CTS in\r
+ RDO_TRG_STATUSBITS_IN => cts_rdo_trg_status_bits_cts,\r
+ RDO_DATA_IN => cts_rdo_data,\r
+ RDO_DATA_WRITE_IN => cts_rdo_write,\r
+ RDO_DATA_FINISHED_IN => cts_rdo_finished,\r
+ --Data from additional modules\r
+ RDO_ADDITIONAL_STATUSBITS_IN => cts_rdo_trg_status_bits_additional,\r
+ RDO_ADDITIONAL_DATA => cts_rdo_additional_data,\r
+ RDO_ADDITIONAL_WRITE => cts_rdo_additional_write,\r
+ RDO_ADDITIONAL_FINISHED => cts_rdo_additional_finished,\r
+\r
+ -- Slow Control --------------------------------------------------------------------\r
+ COMMON_STAT_REGS => open,\r
+ COMMON_CTRL_REGS => common_ctrl_reg,\r
+ ONEWIRE => TEMPSENS,\r
+ ONEWIRE_MONITOR_IN => open,\r
+ MY_ADDRESS_OUT => timer.network_address,\r
+ UNIQUE_ID_OUT => timer.uid,\r
BUS_MASTER_IN => bus_master_in,\r
BUS_MASTER_OUT => bus_master_out,\r
BUS_MASTER_ACTIVE => bus_master_active,\r
-\r
- ONEWIRE_INOUT => open,\r
- I2C_SCL => I2C_SCL,\r
- I2C_SDA => I2C_SDA,\r
- --Timing registers\r
- TIMERS_OUT => timer,\r
- STATUS_GBE_OUT=> gbe_status\r
+ TIMER_TICKS_OUT(0) => timer.tick_us,\r
+ TIMER_TICKS_OUT(1) => timer.tick_ms,\r
+ TEMPERATURE_OUT => timer.temperature,\r
+ EXTERNAL_SEND_RESET => reset_via_gbe,\r
+\r
+ REGIO_ADDR_OUT => ctrlbus_rx.addr,\r
+ REGIO_READ_ENABLE_OUT => ctrlbus_rx.read,\r
+ REGIO_WRITE_ENABLE_OUT => ctrlbus_rx.write,\r
+ REGIO_DATA_OUT => ctrlbus_rx.data,\r
+ REGIO_DATA_IN => ctrlbus_tx.data,\r
+ REGIO_DATAREADY_IN => rdack,\r
+ REGIO_NO_MORE_DATA_IN => ctrlbus_tx.nack,\r
+ REGIO_WRITE_ACK_IN => wrack,\r
+ REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown,\r
+ REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout,\r
+\r
+ --Gbe Sctrl Input\r
+ GSC_INIT_DATAREADY_IN => gsc_init_dataready,\r
+ GSC_INIT_DATA_IN => gsc_init_data,\r
+ GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num,\r
+ GSC_INIT_READ_OUT => gsc_init_read,\r
+ GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready,\r
+ GSC_REPLY_DATA_OUT => gsc_reply_data,\r
+ GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num,\r
+ GSC_REPLY_READ_IN => gsc_reply_read,\r
+ GSC_BUSY_OUT => gsc_busy,\r
+\r
+ --status and control ports\r
+ HUB_STAT_CHANNEL => open,\r
+ HUB_STAT_GEN => open,\r
+ MPLEX_CTRL => (others => '0'),\r
+ MPLEX_STAT => open,\r
+ STAT_REGS => open,\r
+ STAT_CTRL_REGS => open,\r
+\r
+ --Fixed status and control ports\r
+ STAT_DEBUG => open,\r
+ CTRL_DEBUG => (others => '0')\r
);\r
\r
+\r
+ gen_addition_ports : for i in 0 to cts_rdo_additional_ports-1 generate\r
+ cts_rdo_additional_data(31 + i*32 downto 32*i) <= cts_rdo_additional(i).data;\r
+ cts_rdo_trg_status_bits_additional(31 + i*32 downto 32*i) <= cts_rdo_additional(i).statusbits;\r
+\r
+ cts_rdo_additional_write(i) <= cts_rdo_additional(i).data_write;\r
+ cts_rdo_additional_finished(i) <= cts_rdo_additional(i).data_finished;\r
+\r
+ end generate;\r
+\r
+\r
+ rdack <= ctrlbus_tx.ack or ctrlbus_tx.rack;\r
+ wrack <= ctrlbus_tx.ack or ctrlbus_tx.wack;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- CTS\r
+---------------------------------------------------------------------------\r
+ THE_CTS : CTS\r
+ generic map (\r
+ EXTERNAL_TRIGGER_ID => ETM_ID, -- fill in trigger logic enumeration id of external trigger logic\r
+ PLATTFORM => 6, --TRB5sc\r
+ OUTPUT_MULTIPLEXERS => CTS_OUTPUT_MULTIPLEXERS,\r
+ ADDON_GROUPS => 1,\r
+ ADDON_GROUP_UPPER => (12, others => 0)\r
+ )\r
+ port map (\r
+ CLK => clk_sys,\r
+ RESET => reset_i,\r
+\r
+ TRIGGER_BUSY_OUT => trigger_busy_i,\r
+ TIME_REFERENCE_OUT => cts_trigger_out,\r
+\r
+ ADDON_TRIGGERS_IN => cts_addon_triggers_in,\r
+ ADDON_GROUP_ACTIVITY_OUT => open,\r
+ ADDON_GROUP_SELECTED_OUT => open,\r
+\r
+ EXT_TRIGGER_IN => '0',\r
+ EXT_STATUS_IN => (others => '0'),\r
+ EXT_CONTROL_OUT => open,\r
+ EXT_HEADER_BITS_IN => (others => '0'),\r
+ EXT_FORCE_TRIGGER_INFO_IN => (others => '0'),\r
+\r
+ PERIPH_TRIGGER_IN => (others => '0'),\r
+\r
+ OUTPUT_MULTIPLEXERS_OUT => cts_monitor_out,\r
+\r
+ CTS_TRG_SEND_OUT => cts_trg_send,\r
+ CTS_TRG_TYPE_OUT => cts_trg_type,\r
+ CTS_TRG_NUMBER_OUT => cts_trg_number,\r
+ CTS_TRG_INFORMATION_OUT => cts_trg_information,\r
+ CTS_TRG_RND_CODE_OUT => cts_trg_code,\r
+ CTS_TRG_STATUS_BITS_IN => cts_trg_status_bits,\r
+ CTS_TRG_BUSY_IN => cts_trg_busy,\r
+\r
+ CTS_IPU_SEND_OUT => cts_ipu_send,\r
+ CTS_IPU_TYPE_OUT => cts_ipu_type,\r
+ CTS_IPU_NUMBER_OUT => cts_ipu_number,\r
+ CTS_IPU_INFORMATION_OUT => cts_ipu_information,\r
+ CTS_IPU_RND_CODE_OUT => cts_ipu_code,\r
+ CTS_IPU_STATUS_BITS_IN => cts_ipu_status_bits,\r
+ CTS_IPU_BUSY_IN => cts_ipu_busy,\r
+\r
+ CTS_REGIO_ADDR_IN => buscts_rx.addr,\r
+ CTS_REGIO_DATA_IN => buscts_rx.data,\r
+ CTS_REGIO_READ_ENABLE_IN => buscts_rx.read,\r
+ CTS_REGIO_WRITE_ENABLE_IN => buscts_rx.write,\r
+ CTS_REGIO_DATA_OUT => buscts_tx.data,\r
+ CTS_REGIO_DATAREADY_OUT => buscts_tx.rack,\r
+ CTS_REGIO_WRITE_ACK_OUT => buscts_tx.wack,\r
+ CTS_REGIO_UNKNOWN_ADDR_OUT => buscts_tx.unknown,\r
+\r
+ LVL1_TRG_DATA_VALID_IN => cts_rdo_rx.data_valid,\r
+ LVL1_VALID_TIMING_TRG_IN => cts_rdo_rx.valid_timing_trg,\r
+ LVL1_VALID_NOTIMING_TRG_IN => cts_rdo_rx.valid_notiming_trg,\r
+ LVL1_INVALID_TRG_IN => cts_rdo_rx.invalid_trg,\r
+\r
+ FEE_TRG_STATUSBITS_OUT => cts_rdo_trg_status_bits_cts,\r
+ FEE_DATA_OUT => cts_rdo_data,\r
+ FEE_DATA_WRITE_OUT => cts_rdo_write,\r
+ FEE_DATA_FINISHED_OUT => cts_rdo_finished\r
+ );\r
+\r
+ cts_addon_triggers_in(12 downto 4) <= HDR_IO(23 downto 16);\r
+ cts_addon_triggers_in( 3 downto 0) <= trigger_gen_outputs_i;\r
+\r
+ buscts_tx.nack <= '0';\r
+ buscts_tx.ack <= '0';\r
+\r
---------------------------------------------------------------------------\r
-- Bus Handler\r
---------------------------------------------------------------------------\r
THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record\r
generic map(\r
PORT_NUMBER => 4,\r
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"9000", others => x"0000"),\r
- PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, others => 0),\r
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"9000", 4 => x"8100", 5 => x"8300", 6 => x"a000", others => x"0000"),\r
+ PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 8, 5 => 8, 6 => 11, others => 0),\r
PORT_MASK_ENABLE => 1\r
)\r
port map(\r
BUS_RX(1) => bussci_rx, --SCI Serdes\r
BUS_RX(2) => bustc_rx, --Clock switch\r
BUS_RX(3) => busadc_rx,\r
+ BUS_RX(4) => busgbeip_rx,\r
+ BUS_RX(5) => busgbereg_rx,\r
+ BUS_RX(6) => buscts_rx,\r
+\r
BUS_TX(0) => bustools_tx,\r
BUS_TX(1) => bussci_tx,\r
BUS_TX(2) => bustc_tx,\r
BUS_TX(3) => busadc_tx,\r
+ BUS_TX(4) => busgbeip_tx,\r
+ BUS_TX(5) => busgbereg_tx,\r
+ BUS_TX(6) => buscts_tx,\r
STAT_DEBUG => open\r
);\r
\r
FLASH_IN => FLASH_MISO,\r
FLASH_OUT => FLASH_MOSI,\r
PROGRAMN => PROGRAMN,\r
- REBOOT_IN => common_ctrl_reg(15),\r
+ REBOOT_IN => common_ctrl_reg(15) or reboot_from_gbe,\r
--SPI\r
SPI_CS_OUT => spi_cs,\r
SPI_MOSI_OUT => spi_mosi,\r
TRIG_GEN_INPUTS(11 downto 0) => adc_trigger_i,\r
TRIG_GEN_INPUTS(15 downto 12) => x"0",\r
\r
- TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2),\r
- TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0),\r
+ TRIG_GEN_OUTPUTS(3 downto 0) => trigger_gen_outputs_i,\r
+\r
--SED\r
SED_ERROR_OUT => sed_error_i,\r
--Slowcontrol\r
SDIO_A <= spi_mosi(0);\r
spi_miso(0) <= SDIO_A when rising_edge(clk_sys);\r
\r
- \r
+\r
+\r
+\r
---------------------------------------------------------------------------\r
-- ADC ADDON\r
---------------------------------------------------------------------------- \r
+---------------------------------------------------------------------------\r
THE_ADDON : entity work.adc_addon\r
generic map(\r
ACTIVE_CHANNELS => ACTIVE_CHANNELS\r
CLK_ADCBRAW => clk_full_osc,\r
CLK_ADCRAW => clk_350,\r
RESET => reset_i,\r
- \r
+\r
FCO_A => FCO_A,\r
DATA_A => DATA_A,\r
DCO_A => DCO_A,\r
- \r
- DCO_B => DCO_B, \r
- DATA_B => DATA_B, \r
- CLK_B => CLK_B, \r
- CNV_B => CNV_B, \r
+\r
+ DCO_B => DCO_B,\r
+ DATA_B => DATA_B,\r
+ CLK_B => CLK_B,\r
+ CNV_B => CNV_B,\r
TESTPAT_B => TESTPAT_B,\r
- \r
+\r
TRIGGER_OUT => adc_trigger_i(ACTIVE_CHANNELS-1 downto 0),\r
READOUT_RX => readout_rx,\r
READOUT_TX => readout_tx,\r
- \r
+\r
BUS_RX => busadc_rx,\r
BUS_TX => busadc_tx\r
- \r
+\r
);\r
\r
\r
\r
FLASH_NCS <= flash_ncs_i;\r
\r
- \r
+-------------------------------------------------------------------------------\r
+-- No trigger/data endpoint included\r
+-------------------------------------------------------------------------------\r
+readout_tx(0).data_finished <= '1';\r
+readout_tx(0).data_write <= '0';\r
+readout_tx(0).busy_release <= '1';\r
\r
\r
end architecture;\r
jspc29 / trb5sc.git / commitdiff