*** empty log message ***

diff --git a/ebsetup.tex b/ebsetup.tex
index 4357a83f7eb45e974f6ac96d672885da309189ec..9f7b407f0511b4849469714a2bd9bea0378ba81e 100644 (file)
--- a/ebsetup.tex
+++ b/ebsetup.tex
@@ -39,12 +39,12 @@ MDC1/2 4 & 0x1030 & 50019 & 52019 & 54019 & 147 \\
 MDC1/2 5 & 0x1040 & 50020 & 52020 & 54020 & 148 \\
 MDC1/2 6 & 0x1050 & 50021 & 52021 & 54021 & 149 \\
 \hline
-MDC3/4 1 & 0x1100 & 50022 & 52016 & 54016 & 150 \\
-MDC3/4 2 & 0x1110 & 50023 & 52017 & 54017 & 151 \\
-MDC3/4 3 & 0x1120 & 50024 & 52018 & 54018 & 152 \\
-MDC3/4 4 & 0x1130 & 50025 & 52019 & 54019 & 153 \\
-MDC3/4 5 & 0x1140 & 50026 & 52020 & 54020 & 154 \\
-MDC3/4 6 & 0x1150 & 50027 & 52021 & 54021 & 155 \\
+MDC3/4 1 & 0x1100 & 50022 & 52022 & 54022 & 150 \\
+MDC3/4 2 & 0x1110 & 50023 & 52023 & 54023 & 151 \\
+MDC3/4 3 & 0x1120 & 50024 & 52024 & 54024 & 152 \\
+MDC3/4 4 & 0x1130 & 50025 & 52025 & 54025 & 153 \\
+MDC3/4 5 & 0x1140 & 50026 & 52026 & 54026 & 154 \\
+MDC3/4 6 & 0x1150 & 50027 & 52027 & 54027 & 155 \\
 \hline
 Shower 1 & 0x3200 & 50032 & 52032 & 54032 & 160 \\
 Shower 2 & 0x3210 & 50033 & 52033 & 54033 & 161 \\

diff --git a/installation_trbnet.tex b/installation_trbnet.tex
index 935aa5761940d5cbfd0c086f6af510d063f8f3b1..cbdd3efa4bc56f77fe8bdcd91054a766fd68ba66 100644 (file)
--- a/installation_trbnet.tex
+++ b/installation_trbnet.tex
@@ -53,7 +53,7 @@ The usage of physical ports 5 -- 16 on TrbNet Hubs is given in the following lis
  \item[Shower Hub (0x8501)] Port 1 to 6 connect to the Shower AddOn in each of the sectors.
  \item[TOF Hub (0x8601)] Port 1 to 6 connect to the TRBs in each of the sectors, Port 7 is used for the additional TRB.
  \item[Forward Wall (0x8701)] This hub connects the three TRB of Forward Wall. Ports 1 to 3 are used, connected in the same order as the TRB are numbered.
- \item[Start/Veto/CTS Hub (0x8801)] Port 1 connects to the Start-TRB, Port 2 to the Veto TRB, Port 3 to the CTS.
+ \item[Start/Veto/CTS Hub (0x8801)] Port 1 connects to the Start-TRB, Port 2 to the Veto TRB, Port 3 to the readout port of  the CTS.
 \end{description}
 
 \subsection{MDC Hub}

diff --git a/lvl1trigger.tex b/lvl1trigger.tex
index 68fa125c46ac75998564d5052cc89c93e12b5141..64ee5750b07ca782c572eafe9494710efccfcde3 100755 (executable)
--- a/lvl1trigger.tex
+++ b/lvl1trigger.tex
@@ -201,10 +201,10 @@ A & Shower Calibration\\
 B & Shower Pedestals\\
 C & RICH Calibration\\
 D & \\
-E & \\
+E & Status Information\\
 F & \\
 \end{tabular}
-\caption{Trigger Types. List is not complete. Triggers 8 to F are not sent in combination with a timing trigger.}
+\caption{Trigger Types. Triggers 8 to F are not sent in combination with a timing trigger.}
 \label{Triggertypes}
 \end{center}
 \end{table}
@@ -235,3 +235,8 @@ The CTS will include features to set these bits via slow control either to a sta
 \label{LVL1TrgInformation}
 \end{center}
 \end{table}
+
+
+
+
+\subsection{Trigger Types: 0xE - Status Information}

diff --git a/main.tex b/main.tex
index c7b9c8f29b104bfc84648b4e503fdb4b553be345..6f2f6fee464a26ee1bd3e7d9e5cf8f2f41dd9d7f 100755 (executable)
--- a/main.tex
+++ b/main.tex
@@ -106,6 +106,9 @@
 \part{Endpoints}
 \section{The Endpoint}
        \input{endpoint}
+\clearpage
+\section{The Media Interface}
+  \input{mediainterface}
 
 \clearpage
 \part{The Channels}

diff --git a/mdc.tex b/mdc.tex
index abe04a8d250a304108884ff9c37a45a438c1ab17..98c76d47607b4e40c2337f589c6a061383ff0717 100755 (executable)
--- a/mdc.tex
+++ b/mdc.tex
@@ -133,20 +133,27 @@ The bits of the common status and control registers used in the OEP are listed i
 
 \begin{table}
 \begin{center}
-\begin{tabular}{|c|l|l|}
+\begin{tabularx}{\textwidth}{|c|l|X|}
 \hline
 \textbf{Reg.} & \textbf{Bit} & \textbf{Description}\\
 \hline\hline
-C0       & 5 -- 4 & 1: short MBO, 2: long MBO\\
-C1       & 27 -- 16 & Number of dummy data words (if enabled)\\
-C1       & 0        & Switch on blinking of LED to identify a board\\
+C0 & 5 -- 4 & 1: short MBO, 2: long MBO\\
+C0 & 25 -- 16 & Maximum number of data words per event \\
+C1 & 0        & Switch on blinking of LED to identify a board\\
+C1 & 8        & Suppress sending of a hit 0 without preceeding hit 1 from one channel. Note that this also suppresses double or triple hit 0. \\
+C1 & 9        & Suppress sending of a hit 1 without subsequent hit 0 from one channel \\
+C1 & 10       & Enable automatic reconfiguration in case of no token return \\
+C1 & 27 -- 16 & Number of dummy data words (if enabled)\\
+C2 & 10 -- 0  & Lower Threshold of TDC data for hit 0. Only data greater or equal are transported.\\
+C2 & 26 -- 16 & Lower Threshold of TDC data for hit 1. Only data greater or equal are transported.\\
 \hline
-\end{tabular}
+\end{tabularx}
 \caption{Control Registers on MDC OEP}
 \label{MDCControlRegisters}
 \end{center}
 \end{table}
 
+
 \begin{table}
 \begin{center}
 \begin{tabularx}{\textwidth}{|c|l|X|}

diff --git a/slowcontrol.tex b/slowcontrol.tex
index 418974a4e812ad067e28cb02219fe225177e3fb2..e89ab55ebb43043d14ca92a6a1be1fd64c0bfd6f 100755 (executable)
--- a/slowcontrol.tex
+++ b/slowcontrol.tex
@@ -211,6 +211,7 @@ The common status and control registers are further explained in the next sectio
 01 & common status register 1      & CSR1 & LVL1 trigger number (Bits 15..0), timing Trigger number (Bits 31..16) (r) \\
 02 & common status register 2      & CSR2 & Status of LVL1 handler \\
 03 & common status register 3      & CSR3 & Trigger input monitor. Bit 15..0: Edge count, Bit 31..16: Length of last pulse \\
+04 & common status register 4      & CSR4 & Link and reset status register \\
 20 & common control register 0     & CCR0 & Strobes for board resets and test triggers (see below) (w)\\
 21 & common control register 1     & CCR1 & Sets LVL1 trigger number (Bits 15..0) (r/w)\\
 22 & common control register 2     & CCR2 & frontend enable, trigger enable, debug enable (r/w)\\
@@ -294,7 +295,7 @@ A detailed bit definition can be found in table~\ref{CommonCtrlReg2}.
 0  & serious error flag \\
 \hline
 \end{tabular}
-\caption{Common Status Register 0}
+\caption{Common Status Register 0 (CSR0)}
 \label{CommonStatReg0}
 \end{center}
 \end{table}
@@ -322,6 +323,23 @@ A detailed bit definition can be found in table~\ref{CommonCtrlReg2}.
 \end{table}
 
 
+\begin{table}
+\begin{center}
+\begin{tabular}{|c|c|}
+\hline
+\textbf{Bits} & \textbf{Description} \\
+\hline\hline
+31 -- 9 & reserved \\
+8       & link error, e.g. code violation received \\
+7 -- 4  & reserved \\
+3 -- 0  & counter for received network resets \\
+\hline
+\end{tabular}
+\caption{Common Status Register 4 (CSR4)}
+\label{CommonCtrlReg4}
+\end{center}
+\end{table}
+
 
 \begin{table}
 \begin{center}