Register the global epoch counter when distributing

diff --git a/ADC/source/adc_processor_cfd.vhd b/ADC/source/adc_processor_cfd.vhd
index eb1707d6db524451552d7dfa9cbf7b406d376423..c81b264d6be19cf9a054cc96989d984b14503232 100644 (file)
--- a/ADC/source/adc_processor_cfd.vhd
+++ b/ADC/source/adc_processor_cfd.vhd
@@ -68,9 +68,8 @@ architecture arch of adc_processor_cfd is
   signal RDO_write : std_logic := '0';
   signal RDO_data  : std_logic_vector(31 downto 0) := (others => '0');
   
-  --type epoch_counter_t is array(CHANNELS - 1 downto 0) of unsigned(23 downto 0);
-  --signal epoch_counter, epoch_counter_save : epoch_counter_t;
-  --signal epoch_counter_sys, epoch_counter_adc : epoch_counter_t;
+  type epoch_counter_t is array(CHANNELS - 1 downto 0) of unsigned(EPOCH_COUNTER_SIZE-1 downto 0);
+  signal epoch_counter : epoch_counter_t;
   
 begin
   CONF_adc <= CONF_sys when rising_edge(CLK_ADC);
@@ -83,6 +82,7 @@ begin
   busy_in_adc <= busy_in_sys when rising_edge(CLK_ADC);
   busy_out_sys <= busy_out_adc when rising_edge(CLK_SYS);
   
+  epoch_counter <= (others => EPOCH_COUNTER_IN) when rising_edge(CLK_ADC);
   
   gen_cfd : for i in 0 to CHANNELS - 1 generate
     trigger_gen(i) <= debug_sys(i).Trigger;
@@ -105,7 +105,7 @@ begin
                RAM_BSY_IN => busy_in_adc,
                RAM_BSY_OUT => busy_out_adc(i),
                DEBUG    => debug_adc(i),
-               EPOCH_COUNTER_IN => EPOCH_COUNTER_IN
+               EPOCH_COUNTER_IN => epoch_counter(i)
       );
     
     ram_addr_sys(i) <= std_logic_vector(resize(ram_counter(i),ram_addr_sys(i)'length));

diff --git a/ADC/source/adc_processor_cfd_ch.vhd b/ADC/source/adc_processor_cfd_ch.vhd
index c26e19c6becdc55d9b0feb1f5ec9d83d7ad37f56..aee508cf97b6a1f4b35c91ed47430780b52f7850 100644 (file)
--- a/ADC/source/adc_processor_cfd_ch.vhd
+++ b/ADC/source/adc_processor_cfd_ch.vhd
@@ -93,7 +93,7 @@ architecture arch of adc_processor_cfd_ch is
 
   signal integral_sum                      : signed(RESOLUTION_CFD - 1 downto 0) := (others => '0');
 
-  signal epoch_counter_save : unsigned(EPOCH_COUNTER_SIZE-1 downto 0) := (others => '0');
+  signal epoch_counter, epoch_counter_save : unsigned(EPOCH_COUNTER_SIZE-1 downto 0) := (others => '0');
   type state_t is (IDLE, INTEGRATE, WRITE1, WRITE2, WRITE3, FINISH, LOCKED, DEBUG_DUMP);
   signal state : state_t := IDLE;
 
@@ -234,6 +234,8 @@ begin
   begin
     wait until rising_edge(CLK);
 
+    epoch_counter <= EPOCH_COUNTER_IN;
+
     cfd_prev <= cfd.value;
     if cfd_prev < 0 and cfd.value >= 0 and cfd.thresh = '1' then
       zeroX := '1';
@@ -253,7 +255,7 @@ begin
           integral_sum <= resize(delay_integral_out, RESOLUTION_CFD);
           cfd_prev_save <= cfd_prev; 
           cfd_save <= cfd.value;
-          epoch_counter_save <= EPOCH_COUNTER_IN;
+          epoch_counter_save <= epoch_counter;
         elsif CONF.DebugMode = 0 and RAM_BSY_IN = '1' then
           state <= LOCKED;
         elsif CONF.DebugMode /= 0 and RAM_BSY_IN = '1' then