SERDES config files added. soda_hub constraint-file added.

diff --git a/soda_client/serdes_sync_upstream.txt b/soda_client/serdes_sync_upstream.txt
new file mode 100644 (file)
index 0000000..a057cb3
--- /dev/null
+++ b/soda_client/serdes_sync_upstream.txt
@@ -0,0 +1,58 @@
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSD quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSD quad to the final design requirements.
+
+DEVICE_NAME "LFE3-150EA"
+CH3_PROTOCOL            "G8B10B"
+CH0_MODE                "DISABLED"
+CH1_MODE                "DISABLED"
+CH2_MODE                "DISABLED"
+CH3_MODE                "RXTX"
+CH3_CDR_SRC       "REFCLK_CORE"
+PLL_SRC                 "REFCLK_CORE"
+TX_DATARATE_RANGE       "MEDHIGH"
+CH3_RX_DATARATE_RANGE   "MEDHIGH"
+REFCK_MULT              "10X"
+#REFCLK_RATE            200
+CH3_RX_DATA_RATE        "FULL"
+CH3_TX_DATA_RATE        "FULL"
+CH3_TX_DATA_WIDTH       "8"
+CH3_RX_DATA_WIDTH        "8"
+CH3_TX_FIFO       "DISABLED"
+CH3_RX_FIFO        "DISABLED"
+CH3_TDRV      "0"
+#CH3_TX_FICLK_RATE      200
+#CH3_RXREFCLK_RATE        "200"
+#CH3_RX_FICLK_RATE      200
+CH3_TX_PRE              "DISABLED"
+CH3_RTERM_TX            "50"
+CH3_RX_EQ               "DISABLED"
+CH3_RTERM_RX            "50"
+CH3_RX_DCC              "DC"
+CH3_LOS_THRESHOLD_LO       "2"
+PLL_TERM                "50"
+PLL_DCC                 "AC"
+PLL_LOL_SET             "0"
+CH3_TX_SB               "DISABLED"
+CH3_RX_SB               "DISABLED"
+CH3_TX_8B10B            "ENABLED"
+CH3_RX_8B10B            "ENABLED"
+CH3_COMMA_A             "1100000101"
+CH3_COMMA_B             "0011111010"
+CH3_COMMA_M             "1111111100"
+CH3_RXWA                "ENABLED"
+CH3_ILSM                "ENABLED"
+CH3_CTC                 "DISABLED"
+CH3_CC_MATCH4           "0100011100"
+CH3_CC_MATCH_MODE       "1"
+CH3_CC_MIN_IPG          "3"
+CCHMARK                 "9"
+CCLMARK                 "7"
+CH3_SSLB                "DISABLED"
+CH3_SPLBPORTS           "DISABLED"
+CH3_PCSLBPORTS          "DISABLED"
+INT_ALL                 "DISABLED"
+QD_REFCK2CORE           "ENABLED"
+
+

diff --git a/soda_hub.ldf b/soda_hub.ldf
index e628cc1b9c35f5307374096d2b63525eae9201a1..ae19f78bb27e7528ade175b2d8140f0405c6f5a4 100644 (file)
--- a/soda_hub.ldf
+++ b/soda_hub.ldf
@@ -4,7 +4,7 @@
         <Option name="HDL type" value="VHDL"/>
     </Options>
     <Implementation title="soda_hub" dir="soda_hub" description="soda_hub" synthesis="synplify" default_strategy="Strategy1">
-        <Options top="trb3_periph_sodahub"/>
+        <Options def_top="trb3_periph_sodahub" top="trb3_periph_sodahub"/>
         <Source name="code/version.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
@@ -44,9 +44,6 @@
         <Source name="code/soda_packet_builder.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="code/dff_re.vhd" type="VHDL" type_short="VHDL" excluded="TRUE">
-            <Options/>
-        </Source>
         <Source name="code/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
@@ -347,7 +344,7 @@
         <Source name="soda_hub.lpf" type="Logic Preference" type_short="LPF">
             <Options/>
         </Source>
-        <Source name="soda_hub_probe.rvl" type="Reveal" type_short="Reveal">
+        <Source name="soda_hub_probe.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
             <Options/>
         </Source>
         <Source name="trb3_soda_hub.xcf" type="Programming Project File" type_short="Programming">

diff --git a/soda_hub.lpf b/soda_hub.lpf
new file mode 100644 (file)
index 0000000..5f8e0a5
--- /dev/null
+++ b/soda_hub.lpf
@@ -0,0 +1,207 @@
+rvl_alias "rxup_full_clk" "the_hub_sync_uplink/rx_full_clk_out";
+RVL_ALIAS "clk_raw_internal" "the_hub_sync_downlink/oscclk"; 
+RVL_ALIAS "clk_raw_internal" "the_hub_sync_downlink/oscclk"; 
+RVL_ALIAS "reveal_ist_577" "the_hub_sync_downlink/the_serdes/rx_full_clk_ch0"; 
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+#################################################################
+# Basic Settings
+#################################################################
+SYSCONFIG MCCLK_FREQ=20 ;
+#  FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+#  FREQUENCY PORT "CLK_PCLK_LEFT" 200.000000 MHz ;
+#  FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
+#################################################################
+# Clock I/O
+#################################################################
+#LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
+#LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
+#LOCATE COMP  "CLK_SERDES_INT_RIGHT" SITE "AC18";
+#LOCATE COMP  "CLK_SERDES_INT_LEFT"  SITE "AC10";s
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;
+#LOCATE COMP  "CLK_GPLL_LEFT"        SITE "U25";
+DEFINE PORT GROUP "CLK_group" "CLK*" ;
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
+#################################################################
+# To central FPGA
+#################################################################
+#LOCATE COMP  "FPGA5_COMM_0"   SITE "AD4";
+#LOCATE COMP  "FPGA5_COMM_1"   SITE "AE3";
+#LOCATE COMP  "FPGA5_COMM_2"   SITE "AA7";
+#LOCATE COMP  "FPGA5_COMM_3"   SITE "AB7";
+#LOCATE COMP  "FPGA5_COMM_4"   SITE "AD3";
+#LOCATE COMP  "FPGA5_COMM_5"   SITE "AC4";
+#LOCATE COMP  "FPGA5_COMM_6"   SITE "AE2";
+#LOCATE COMP  "FPGA5_COMM_7"   SITE "AF3";
+#LOCATE COMP  "FPGA5_COMM_8"   SITE "AE4";
+#LOCATE COMP  "FPGA5_COMM_9"   SITE "AF4";
+#LOCATE COMP  "FPGA5_COMM_10"  SITE "V10";
+#LOCATE COMP  "FPGA5_COMM_11"  SITE "W10";
+#DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
+#IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+LOCATE COMP "TEST_LINE[0]" SITE "A5" ;
+LOCATE COMP "TEST_LINE[1]" SITE "A6" ;
+LOCATE COMP "TEST_LINE[2]" SITE "G8" ;
+LOCATE COMP "TEST_LINE[3]" SITE "F9" ;
+LOCATE COMP "TEST_LINE[4]" SITE "D9" ;
+LOCATE COMP "TEST_LINE[5]" SITE "D10" ;
+LOCATE COMP "TEST_LINE[6]" SITE "F10" ;
+LOCATE COMP "TEST_LINE[7]" SITE "E10" ;
+LOCATE COMP "TEST_LINE[8]" SITE "A8" ;
+LOCATE COMP "TEST_LINE[9]" SITE "B8" ;
+LOCATE COMP "TEST_LINE[10]" SITE "G10" ;
+LOCATE COMP "TEST_LINE[11]" SITE "G9" ;
+LOCATE COMP "TEST_LINE[12]" SITE "C9" ;
+LOCATE COMP "TEST_LINE[13]" SITE "C10" ;
+LOCATE COMP "TEST_LINE[14]" SITE "H10" ;
+LOCATE COMP "TEST_LINE[15]" SITE "H11" ;
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
+#################################################################
+# Connection to AddOn
+#################################################################
+LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0   #1
+LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1   #3
+LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2   #5
+LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3   #7
+#LOCATE COMP  "SFP_MOD1_1"    SITE "R1";     #DQLL0_4   #9
+#LOCATE COMP  "SFP_MOD2_1"    SITE "R2";     #DQLL0_5   #11
+#LOCATE COMP  "SFP_RATESEL_1" SITE "N3";     #DQSLL0_T  #13
+LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C  #15
+LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6   #17
+#LOCATE COMP  "SFP_TXFAULT_1" SITE "P6";     #DQLL0_7   #19
+LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8   #21
+LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9   #23
+LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0   #25
+LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1   #27
+#LOCATE COMP  "SFP_MOD1_2"    SITE "AB1";    #DQLL2_2   #29
+#LOCATE COMP  "SFP_MOD2_2"    SITE "AC1";    #DQLL2_3   #31
+#LOCATE COMP  "SFP_RATESEL_2" SITE "AA1";    #DQLL2_4   #33
+LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5   #35
+LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T   #37  #should be DQSLL2
+#LOCATE COMP  "SFP_TXFAULT_2" SITE "W6";     #DQLL2_C   #39  #should be DQSLL2
+LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0   #2
+LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1   #4
+LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2   #6
+LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3   #8
+#LOCATE COMP  "SFP_MOD1_3"      SITE "AB3";    #DQLL3_4   #10
+#LOCATE COMP  "SFP_MOD2_3"      SITE "AB4";    #DQLL3_5   #12
+#LOCATE COMP  "SFP_RATESEL_3"   SITE "Y6";     #DQLL3_T   #14  #should be DQSLL3
+LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C   #16  #should be DQSLL3
+LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6   #18
+#LOCATE COMP  "SFP_TXFAULT_3"   SITE "AA4";    #DQLL3_7   #20
+LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8   #22
+LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9   #24
+LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0   #26
+LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1   #28
+#LOCATE COMP  "SFP_MOD1_4"      SITE "T1";     #DQLL1_2   #30
+#LOCATE COMP  "SFP_MOD2_4"      SITE "U1";     #DQLL1_3   #32
+#LOCATE COMP  "SFP_RATESEL_4"   SITE "P4";     #DQLL1_4   #34
+LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5   #36
+LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T  #38
+#LOCATE COMP  "SFP_TXFAULT_4"   SITE "R4";     #DQSLL1_C  #40
+LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0   #169
+LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1   #171
+LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2   #173
+LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3   #175
+#LOCATE COMP  "SFP_MOD1_5"     SITE "AA26";   #DQLR1_4   #177
+#LOCATE COMP  "SFP_MOD2_5"     SITE "AB26";   #DQLR1_5   #179
+#LOCATE COMP  "SFP_RATESEL_5"  SITE "W21";    #DQSLR1_T  #181
+LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C  #183
+LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6   #185
+#LOCATE COMP  "SFP_TXFAULT_5"  SITE "AA23";   #DQLR1_7   #187
+LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0   #170
+LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1   #172
+LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2   #174
+LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3   #176
+#LOCATE COMP  "SFP_MOD1_6"     SITE "T26";    #DQLR2_4   #178
+#LOCATE COMP  "SFP_MOD2_6"     SITE "U26";    #DQLR2_5   #180
+#LOCATE COMP  "SFP_RATESEL_6"  SITE "V21";    #DQSLR2_T  #182
+LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C  #184
+LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6   #186
+#LOCATE COMP  "SFP_TXFAULT_6"  SITE "V24";    #DQLR2_7   #188
+DEFINE PORT GROUP "SFP_group" "SFP*" ;
+IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+#################################################################
+# Additional Lines to AddOn
+#################################################################
+#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
+#all lines are input only
+#line 4/5 go to PLL input
+#LOCATE COMP  "SPARE_LINE_0"    SITE "M25"; #194
+#LOCATE COMP  "SPARE_LINE_1"    SITE "M26"; #196
+#LOCATE COMP  "SPARE_LINE_2"    SITE "W4";  #198
+#LOCATE COMP  "SPARE_LINE_3"    SITE "W5";  #200
+#LOCATE COMP  "SPARE_LINE_4"    SITE "M3";  #DQUL3_8_OUTOFLANE_FPGA__3 #69
+#LOCATE COMP  "SPARE_LINE_5"    SITE "M2";  #DQUL3_9_OUTOFLANE_FPGA__3 #71  
+#################################################################
+# Flash ROM and Reboot
+#################################################################
+LOCATE COMP "FLASH_CLK" SITE "B12" ;
+LOCATE COMP "FLASH_CS" SITE "E11" ;
+LOCATE COMP "FLASH_DIN" SITE "E12" ;
+LOCATE COMP "FLASH_DOUT" SITE "A12" ;
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
+LOCATE COMP "PROGRAMN" SITE "B11" ;
+IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+#################################################################
+# Misc
+#################################################################
+LOCATE COMP "TEMPSENS" SITE "A13" ;
+IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+#coding of FPGA number
+LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;
+LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;
+IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+#terminated differential pair to pads
+LOCATE COMP "SUPPL" SITE "C14" ;
+#IOBUF  PORT "SUPPL" IO_TYPE=LVDS25;
+#################################################################
+# LED
+#################################################################
+LOCATE COMP "LED_GREEN" SITE "F12" ;
+LOCATE COMP "LED_ORANGE" SITE "G13" ;
+LOCATE COMP "LED_RED" SITE "A15" ;
+LOCATE COMP "LED_YELLOW" SITE "A16" ;
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+#################################################################
+#GSR_NET NET "GSR_N";  
+#################################################################
+# Locate Serdes and media interfaces
+#################################################################
+LOCATE COMP "THE_HUB_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "THE_HUB_SYNC_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;
+#REGION "UPLINK_REGION" "R90C45D" 25 35 DEVSIZE;       # Uplink is now fiber !
+#REGION "SPI_REGION"   "R3C77D" 15 16 DEVSIZE; #"R13C150D" 15 18 DEVSIZE;
+#REGION "IOBUF_REGION" "R10C43D"  88 86 DEVSIZE;
+#LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "SPI_REGION" ; 
+#LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "SPI_REGION" ;
+#LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK_REGION" ; No longer present in copper
+#LOCATE UGROUP "THE_SYNC_LINK/media_uplink_group" REGION "UPLINK_REGION" ;
+MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
+MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ;
+MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;
+MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;
+#MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/wa_pos*" 20.000000 ns ;       # to debug only\r
+MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/SCI_DATA_OUT*" 20.000000 ns ;
+MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;
+MULTICYCLE FROM CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;
+#MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/wa_pos*" 20.000000 ns ;     # to debug only
+#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
+BLOCK JTAGPATHS ;
+## IOBUF ALLPORTS ;
+#USE SECONDARY NET "THE_SYNC_LINK/sci_read_i" ;
+#USE SECONDARY NET "THE_SYNC_LINK/sci_write_i" ;
+#USE PRIMARY NET "THE_HUB_SYNC_DOWNLINK/soda_rxdn_clock_full[1]" ;
+USE PRIMARY NET "clk_raw_internal_c" ;
+USE PRIMARY NET "clk_soda_i" ;
+USE PRIMARY NET "clk_sys_internal_c" ;
+MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
+MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_position[0]" 20.000000 ns ;

diff --git a/soda_hub/serdes_4_sync_downstream.txt b/soda_hub/serdes_4_sync_downstream.txt
new file mode 100644 (file)
index 0000000..8e076a7
--- /dev/null
+++ b/soda_hub/serdes_4_sync_downstream.txt
@@ -0,0 +1,163 @@
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSD quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSD quad to the final design requirements.
+
+DEVICE_NAME "LFE3-150EA"
+CH0_PROTOCOL            "G8B10B"
+CH1_PROTOCOL            "G8B10B"
+CH2_PROTOCOL            "G8B10B"
+CH3_PROTOCOL            "G8B10B"
+CH0_MODE                "RXTX"
+CH1_MODE                "RXTX"
+CH2_MODE                "RXTX"
+CH3_MODE                "RXTX"
+CH0_CDR_SRC       "REFCLK_CORE"
+CH1_CDR_SRC       "REFCLK_CORE"
+CH2_CDR_SRC       "REFCLK_CORE"
+CH3_CDR_SRC       "REFCLK_CORE"
+PLL_SRC                 "REFCLK_CORE"
+TX_DATARATE_RANGE       "MEDHIGH"
+CH0_RX_DATARATE_RANGE   "MEDHIGH"
+CH1_RX_DATARATE_RANGE   "MEDHIGH"
+CH2_RX_DATARATE_RANGE   "MEDHIGH"
+CH3_RX_DATARATE_RANGE   "MEDHIGH"
+REFCK_MULT              "10X"
+#REFCLK_RATE            200
+CH0_RX_DATA_RATE        "FULL"
+CH1_RX_DATA_RATE        "FULL"
+CH2_RX_DATA_RATE        "FULL"
+CH3_RX_DATA_RATE        "FULL"
+CH0_TX_DATA_RATE        "FULL"
+CH1_TX_DATA_RATE        "FULL"
+CH2_TX_DATA_RATE        "FULL"
+CH3_TX_DATA_RATE        "FULL"
+CH0_TX_DATA_WIDTH       "8"
+CH1_TX_DATA_WIDTH       "8"
+CH2_TX_DATA_WIDTH       "8"
+CH3_TX_DATA_WIDTH       "8"
+CH0_RX_DATA_WIDTH        "8"
+CH1_RX_DATA_WIDTH        "8"
+CH2_RX_DATA_WIDTH        "8"
+CH3_RX_DATA_WIDTH        "8"
+CH0_TX_FIFO       "DISABLED"
+CH1_TX_FIFO       "DISABLED"
+CH2_TX_FIFO       "DISABLED"
+CH3_TX_FIFO       "DISABLED"
+CH0_RX_FIFO        "ENABLED"
+CH1_RX_FIFO        "ENABLED"
+CH2_RX_FIFO        "ENABLED"
+CH3_RX_FIFO        "ENABLED"
+CH0_TDRV      "0"
+CH1_TDRV      "0"
+CH2_TDRV      "0"
+CH3_TDRV      "0"
+#CH0_TX_FICLK_RATE      200
+#CH1_TX_FICLK_RATE      200
+#CH2_TX_FICLK_RATE      200
+#CH3_TX_FICLK_RATE      200
+#CH0_RXREFCLK_RATE        "200"
+#CH1_RXREFCLK_RATE        "200"
+#CH2_RXREFCLK_RATE        "200"
+#CH3_RXREFCLK_RATE        "200"
+#CH0_RX_FICLK_RATE      200
+#CH1_RX_FICLK_RATE      200
+#CH2_RX_FICLK_RATE      200
+#CH3_RX_FICLK_RATE      200
+CH0_TX_PRE              "DISABLED"
+CH1_TX_PRE              "DISABLED"
+CH2_TX_PRE              "DISABLED"
+CH3_TX_PRE              "DISABLED"
+CH0_RTERM_TX            "50"
+CH1_RTERM_TX            "50"
+CH2_RTERM_TX            "50"
+CH3_RTERM_TX            "50"
+CH0_RX_EQ               "DISABLED"
+CH1_RX_EQ               "DISABLED"
+CH2_RX_EQ               "DISABLED"
+CH3_RX_EQ               "DISABLED"
+CH0_RTERM_RX            "50"
+CH1_RTERM_RX            "50"
+CH2_RTERM_RX            "50"
+CH3_RTERM_RX            "50"
+CH0_RX_DCC              "DC"
+CH1_RX_DCC              "DC"
+CH2_RX_DCC              "DC"
+CH3_RX_DCC              "DC"
+CH0_LOS_THRESHOLD_LO       "2"
+CH1_LOS_THRESHOLD_LO       "2"
+CH2_LOS_THRESHOLD_LO       "2"
+CH3_LOS_THRESHOLD_LO       "2"
+PLL_TERM                "50"
+PLL_DCC                 "DC"
+PLL_LOL_SET             "0"
+CH0_TX_SB               "DISABLED"
+CH1_TX_SB               "DISABLED"
+CH2_TX_SB               "DISABLED"
+CH3_TX_SB               "DISABLED"
+CH0_RX_SB               "DISABLED"
+CH1_RX_SB               "DISABLED"
+CH2_RX_SB               "DISABLED"
+CH3_RX_SB               "DISABLED"
+CH0_TX_8B10B            "ENABLED"
+CH1_TX_8B10B            "ENABLED"
+CH2_TX_8B10B            "ENABLED"
+CH3_TX_8B10B            "ENABLED"
+CH0_RX_8B10B            "ENABLED"
+CH1_RX_8B10B            "ENABLED"
+CH2_RX_8B10B            "ENABLED"
+CH3_RX_8B10B            "ENABLED"
+CH0_COMMA_A             "1100000101"
+CH1_COMMA_A             "1100000101"
+CH2_COMMA_A             "1100000101"
+CH3_COMMA_A             "1100000101"
+CH0_COMMA_B             "0011111010"
+CH1_COMMA_B             "0011111010"
+CH2_COMMA_B             "0011111010"
+CH3_COMMA_B             "0011111010"
+CH0_COMMA_M             "1111111100"
+CH1_COMMA_M             "1111111100"
+CH2_COMMA_M             "1111111100"
+CH3_COMMA_M             "1111111100"
+CH0_RXWA                "ENABLED"
+CH1_RXWA                "ENABLED"
+CH2_RXWA                "ENABLED"
+CH3_RXWA                "ENABLED"
+CH0_ILSM                "ENABLED"
+CH1_ILSM                "ENABLED"
+CH2_ILSM                "ENABLED"
+CH3_ILSM                "ENABLED"
+CH0_CTC                 "DISABLED"
+CH1_CTC                 "DISABLED"
+CH2_CTC                 "DISABLED"
+CH3_CTC                 "DISABLED"
+CH0_CC_MATCH4           "0000011100"
+CH1_CC_MATCH4           "0000011100"
+CH2_CC_MATCH4           "0000011100"
+CH3_CC_MATCH4           "0000011100"
+CH0_CC_MATCH_MODE       "1"
+CH1_CC_MATCH_MODE       "1"
+CH2_CC_MATCH_MODE       "1"
+CH3_CC_MATCH_MODE       "1"
+CH0_CC_MIN_IPG          "3"
+CH1_CC_MIN_IPG          "3"
+CH2_CC_MIN_IPG          "3"
+CH3_CC_MIN_IPG          "3"
+CCHMARK                 "9"
+CCLMARK                 "7"
+CH0_SSLB                "DISABLED"
+CH1_SSLB                "DISABLED"
+CH2_SSLB                "DISABLED"
+CH3_SSLB                "DISABLED"
+CH0_SPLBPORTS           "DISABLED"
+CH1_SPLBPORTS           "DISABLED"
+CH2_SPLBPORTS           "DISABLED"
+CH3_SPLBPORTS           "DISABLED"
+CH0_PCSLBPORTS          "DISABLED"
+CH1_PCSLBPORTS          "DISABLED"
+CH2_PCSLBPORTS          "DISABLED"
+CH3_PCSLBPORTS          "DISABLED"
+INT_ALL                 "DISABLED"
+QD_REFCK2CORE           "ENABLED"
+
+

diff --git a/soda_hub/serdes_sync_upstream.txt b/soda_hub/serdes_sync_upstream.txt
new file mode 100644 (file)
index 0000000..a057cb3
--- /dev/null
+++ b/soda_hub/serdes_sync_upstream.txt
@@ -0,0 +1,58 @@
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSD quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSD quad to the final design requirements.
+
+DEVICE_NAME "LFE3-150EA"
+CH3_PROTOCOL            "G8B10B"
+CH0_MODE                "DISABLED"
+CH1_MODE                "DISABLED"
+CH2_MODE                "DISABLED"
+CH3_MODE                "RXTX"
+CH3_CDR_SRC       "REFCLK_CORE"
+PLL_SRC                 "REFCLK_CORE"
+TX_DATARATE_RANGE       "MEDHIGH"
+CH3_RX_DATARATE_RANGE   "MEDHIGH"
+REFCK_MULT              "10X"
+#REFCLK_RATE            200
+CH3_RX_DATA_RATE        "FULL"
+CH3_TX_DATA_RATE        "FULL"
+CH3_TX_DATA_WIDTH       "8"
+CH3_RX_DATA_WIDTH        "8"
+CH3_TX_FIFO       "DISABLED"
+CH3_RX_FIFO        "DISABLED"
+CH3_TDRV      "0"
+#CH3_TX_FICLK_RATE      200
+#CH3_RXREFCLK_RATE        "200"
+#CH3_RX_FICLK_RATE      200
+CH3_TX_PRE              "DISABLED"
+CH3_RTERM_TX            "50"
+CH3_RX_EQ               "DISABLED"
+CH3_RTERM_RX            "50"
+CH3_RX_DCC              "DC"
+CH3_LOS_THRESHOLD_LO       "2"
+PLL_TERM                "50"
+PLL_DCC                 "AC"
+PLL_LOL_SET             "0"
+CH3_TX_SB               "DISABLED"
+CH3_RX_SB               "DISABLED"
+CH3_TX_8B10B            "ENABLED"
+CH3_RX_8B10B            "ENABLED"
+CH3_COMMA_A             "1100000101"
+CH3_COMMA_B             "0011111010"
+CH3_COMMA_M             "1111111100"
+CH3_RXWA                "ENABLED"
+CH3_ILSM                "ENABLED"
+CH3_CTC                 "DISABLED"
+CH3_CC_MATCH4           "0100011100"
+CH3_CC_MATCH_MODE       "1"
+CH3_CC_MIN_IPG          "3"
+CCHMARK                 "9"
+CCLMARK                 "7"
+CH3_SSLB                "DISABLED"
+CH3_SPLBPORTS           "DISABLED"
+CH3_PCSLBPORTS          "DISABLED"
+INT_ALL                 "DISABLED"
+QD_REFCK2CORE           "ENABLED"
+
+

diff --git a/soda_hub_probe.rvl b/soda_hub_probe.rvl
index 9f04a86c2b322e433b9181aefa3c0b0aef3861db..8516c6e4b030b04119eb47514bf1ef1243faeda7 100644 (file)
--- a/soda_hub_probe.rvl
+++ b/soda_hub_probe.rvl
@@ -1,7 +1,7 @@
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_hub_probe.rvl" Date="2014-08-18">
+<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_hub_probe.rvl" Date="2014-08-21">
     <IP Version="1_5_062609"/>
     <Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_hub"/>
-    <Core InsertDataset="0" Insert="1" Reveal_sig="2049251810" Name="trb3_periph_sodahub_LA0" ID="0">
+    <Core InsertDataset="0" Insert="1" Reveal_sig="2049630853" Name="trb3_periph_sodahub_LA0" ID="0">
         <Setting>
             <Clock SampleClk="the_hub_sync_uplink/rx_full_clk_out" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
             <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="256"/>
@@ -193,9 +193,15 @@
                 <TU Serialbits="0" Type="0" ID="1" Sig="a_soda_hub/start_of_superburst_s,"/>
                 <TU Serialbits="0" Type="0" ID="2" Sig="(BUS)a_soda_hub/send_start_calibration_s[3:0],"/>
                 <TU Serialbits="0" Type="0" ID="3" Sig="a_soda_hub/soda_cmd_valid_s,"/>
+                <TU Serialbits="0" Type="0" ID="4" Sig="the_hub_sync_uplink/watchdog_trigger,"/>
+                <TU Serialbits="0" Type="0" ID="5" Sig="the_hub_sync_uplink/rx_error,"/>
+                <TU Serialbits="0" Type="0" ID="6" Sig="(BUS)the_hub_sync_downlink/rx_error[3:0],"/>
                 <TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
                 <TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
                 <TE MaxSequence="2" MaxEvnCnt="1" ID="3" Resource="0"/>
+                <TE MaxSequence="2" MaxEvnCnt="1" ID="4" Resource="0"/>
+                <TE MaxSequence="2" MaxEvnCnt="1" ID="5" Resource="0"/>
+                <TE MaxSequence="2" MaxEvnCnt="1" ID="6" Resource="0"/>
             </Trigger>
         </Dataset>
     </Core>

diff --git a/soda_source/serdes_sync_source_downstream.txt b/soda_source/serdes_sync_source_downstream.txt
new file mode 100644 (file)
index 0000000..400122b
--- /dev/null
+++ b/soda_source/serdes_sync_source_downstream.txt
@@ -0,0 +1,58 @@
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSD quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSD quad to the final design requirements.
+
+DEVICE_NAME "LFE3-150EA"
+CH0_PROTOCOL            "G8B10B"
+CH0_MODE                "RXTX"
+CH1_MODE                "DISABLED"
+CH2_MODE                "DISABLED"
+CH3_MODE                "DISABLED"
+CH0_CDR_SRC       "REFCLK_CORE"
+PLL_SRC                 "REFCLK_CORE"
+TX_DATARATE_RANGE       "MEDHIGH"
+CH0_RX_DATARATE_RANGE   "MEDHIGH"
+REFCK_MULT              "10X"
+#REFCLK_RATE            200
+CH0_RX_DATA_RATE        "FULL"
+CH0_TX_DATA_RATE        "FULL"
+CH0_TX_DATA_WIDTH       "8"
+CH0_RX_DATA_WIDTH        "8"
+CH0_TX_FIFO       "DISABLED"
+CH0_RX_FIFO        "ENABLED"
+CH0_TDRV      "0"
+#CH0_TX_FICLK_RATE      200
+#CH0_RXREFCLK_RATE        "200"
+#CH0_RX_FICLK_RATE      200
+CH0_TX_PRE              "DISABLED"
+CH0_RTERM_TX            "50"
+CH0_RX_EQ               "DISABLED"
+CH0_RTERM_RX            "50"
+CH0_RX_DCC              "DC"
+CH0_LOS_THRESHOLD_LO       "2"
+PLL_TERM                "50"
+PLL_DCC                 "AC"
+PLL_LOL_SET             "0"
+CH0_TX_SB               "DISABLED"
+CH0_RX_SB               "DISABLED"
+CH0_TX_8B10B            "ENABLED"
+CH0_RX_8B10B            "ENABLED"
+CH0_COMMA_A             "1100000101"
+CH0_COMMA_B             "0011111010"
+CH0_COMMA_M             "1111111100"
+CH0_RXWA                "ENABLED"
+CH0_ILSM                "ENABLED"
+CH0_CTC                 "DISABLED"
+CH0_CC_MATCH4           "0000011100"
+CH0_CC_MATCH_MODE       "1"
+CH0_CC_MIN_IPG          "3"
+CCHMARK                 "9"
+CCLMARK                 "7"
+CH0_SSLB                "DISABLED"
+CH0_SPLBPORTS           "DISABLED"
+CH0_PCSLBPORTS          "DISABLED"
+INT_ALL                 "DISABLED"
+QD_REFCK2CORE           "ENABLED"
+
+

diff --git a/soda_source_probe.rvl b/soda_source_probe.rvl
index ae036baaddca03b8ed758aba012196fd0dfbf938..0b0c9dd6b0fae30d2915a5b8beb1b49a57f5775c 100644 (file)
--- a/soda_source_probe.rvl
+++ b/soda_source_probe.rvl
@@ -1,7 +1,7 @@
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_source_probe.rvl" Date="2014-08-07">
+<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_source_probe.rvl" Date="2014-08-21">
     <IP Version="1_5_062609"/>
     <Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_source"/>
-    <Core InsertDataset="0" Insert="1" Reveal_sig="2047787212" Name="trb3_periph_sodasource_LA0" ID="0">
+    <Core InsertDataset="0" Insert="1" Reveal_sig="2049636072" Name="trb3_periph_sodasource_LA0" ID="0">
         <Setting>
             <Clock SampleClk="clk_raw_internal" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
             <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="128"/>
@@ -57,12 +57,17 @@
                 </Bus>
                 <Sig Type="SIG" Name="the_sync_link/tx_dlm"/>
                 <Sig Type="SIG" Name="the_sync_link/tx_k"/>
+                <Sig Type="SIG" Name="link_phase_s"/>
             </Trace>
             <Trigger>
                 <TU Serialbits="0" Type="0" ID="1" Sig="the_soda_source/start_of_superburst_s,"/>
                 <TU Serialbits="0" Type="0" ID="2" Sig="the_soda_source/soda_cmd_strobe_s,"/>
+                <TU Serialbits="0" Type="0" ID="3" Sig="the_sync_link/rx_error,"/>
+                <TU Serialbits="0" Type="0" ID="4" Sig="the_sync_link/tx_dlm,"/>
                 <TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
                 <TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
+                <TE MaxSequence="2" MaxEvnCnt="1" ID="3" Resource="0"/>
+                <TE MaxSequence="2" MaxEvnCnt="1" ID="4" Resource="0"/>
             </Trigger>
         </Dataset>
     </Core>