Speedgrade => '8',
-TOPNAME => "dirich",
+TOPNAME => "dirich5s",
lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
lm_license_file_for_par => "1702\@jspc29",
lattice_path => '/d/jspc29/lattice/diamond/3.10_x64',
Speedgrade => '8',
-TOPNAME => "dirich",
+TOPNAME => "dirich5s",
lm_license_file_for_synplify => "7788\@fb07pc-u102325",
lm_license_file_for_par => "7788\@fb07pc-u102325",
lattice_path => '/usr/local/diamond/3.11_x64/',
Package => 'CABGA381',
Speedgrade => '8',
-TOPNAME => "dirich",
+TOPNAME => "dirich5s",
lm_license_file_for_synplify => "27000\@lxcad01.gsi.de",
lm_license_file_for_par => "1702\@hadeb05.gsi.de",
lattice_path => '/opt/lattice/diamond/3.8_x64',
# compilation/mapping options
set_option -default_enum_encoding sequential
set_option -symbolic_fsm_compiler 1
-set_option -top_module "dirich"
+set_option -top_module "dirich5s"
set_option -resource_sharing false
# map options
# set result format/file last
project -result_format "edif"
-project -result_file "workdir/dirich.edf"
-set_option log_file "workdir/dirich_project.srf"
+project -result_file "workdir/dirich5s.edf"
+set_option log_file "workdir/dirich5s_project.srf"
#implementation attributes
set_option -vlog_std v2001
add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd"
-add_file -vhdl -lib work "./dirich.vhd"
+add_file -vhdl -lib work "./dirich5s.vhd"
#add_file -fpga_constraint "./synplify.fdc"
use work.trb3_components.all;
use work.med_sync_define.all;
-entity dirich is
+entity dirich5s is
port(
CLOCK_CORE : in std_logic; --Main Oscillator
CLOCK_IN : in std_logic; --external Clock
end entity;
-architecture dirich_arch of dirich is
+architecture dirich5s_arch of dirich5s is
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
#-m nodelist.txt # Controlled by the compile.pl script.
#-n 2 # Controlled by the compile.pl script.
-s 10
--t 89
+-t 93
-c 2
-e 2
-i 10